Manufacturing method of array substrate, array substrate and display panel

Abstract

The embodiments of the present application disclose a method for manufacturing an array substrate, an array substrate, and a display panel. The method for manufacturing the array substrate includes providing a base substrate; sequentially forming a conductive layer and a photoresist layer on the base substrate; patterning the photoresist layer and the conductive layer, wherein the patterned conductive layer includes an electrically connected conductive area and an electroplating area; removing the photoresist layer; forming an electroplating layer on the conductive layer at a position corresponding to the electroplating area; and disconnecting the electroplating area from the conductive area. In the present application, the photoresist layer on the conductive layer is removed before forming the electroplating layer, so that the photoresist layer is only used to pattern the conductive layer. This allows for the use of a thinner photoresist layer, reduces the use of the photoresist layer, and thus reduces the manufacturing cost and energy consumption of the array substrate.

Description

Technical Field

[0001] The present application relates to the display field, and in particular to a method for manufacturing an array substrate, an array substrate, and a display panel. Background Art

[0002] With the development of display technology, Mini-LED and Micro-LED are gaining popularity. However, Mini-LED and Micro-LED require higher currents to drive, which increases the thickness of the metal film layer in the corresponding array substrate. Currently, electroplating is commonly used to produce thicker metal film layers. However, in existing array substrate manufacturing methods, thicker photoresist layers are often required to meet the production requirements of thick metal film layers, resulting in higher production costs and energy consumption for the array substrate. Summary of the Invention

[0003] The embodiments of the present application provide a method for manufacturing an array substrate, an array substrate, and a display panel, which can solve the problems of high manufacturing cost and energy consumption in the existing array substrate manufacturing process.

[0004] The present invention provides a method for manufacturing an array substrate, comprising:

[0005] providing a substrate;

[0006] forming a conductive layer and a photoresist layer in sequence on the base substrate;

[0007] performing patterning on the photoresist layer and the conductive layer, wherein the conductive layer after patterning comprises an electrically connected conductive area and an electroplating area;

[0008] removing the photoresist layer;

[0009] forming an electroplating layer on the conductive layer at a position corresponding to the electroplating area;

[0010] The electroplating area is disconnected from the conductive area.

[0011] Optionally, in some embodiments of the present application, patterning the photoresist layer and the conductive layer includes:

[0012] performing patterning on the photoresist layer to partially expose the conductive layer;

[0013] The conductive layer is patterned to remove the exposed portion of the conductive layer to form a conductive electrode, a connecting portion, a routing portion and a seed portion, wherein the conductive electrode and the connecting portion constitute a conductive area, and the routing portion and the seed portion constitute an electroplating area; the routing portion is electrically connected to the seed portion, and the connecting portion is connected between the conductive electrode and the routing portion, so that the electroplating area is electrically connected to the conductive area.

[0014] Optionally, in some embodiments of the present application, forming an electroplating layer at a position on the conductive layer corresponding to the electroplating area includes:

[0015] Providing an electrolytic cell comprising an anode, a cathode, and an electrolyte electrically connected between the anode and the cathode;

[0016] placing the routing portion and the seed portion in an electrolyte of an electrolytic cell;

[0017] electrically connecting the conductive electrode to the cathode of the electrolytic cell;

[0018] A preset current is applied between the anode and cathode of the electrolytic cell to form an electroplating layer on the wiring portion and the seed portion.

[0019] Optionally, in some embodiments of the present application, disconnecting the electroplating area from the conductive area includes:

[0020] The connecting portion is removed or cut off to disconnect the conductive electrode from the wiring portion, thereby disconnecting the electroplating area from the conductive area.

[0021] Optionally, in some embodiments of the present application, the method further includes:

[0022] The routing portion and the electroplating layer on the routing portion are patterned to form a conductive routing, so that the conductive routing is electrically connected to the seed portion.

[0023] Optionally, in some embodiments of the present application, the thickness of the photoresist layer is greater than or equal to 1 micron and less than or equal to 1.5 microns.

[0024] Accordingly, an embodiment of the present application further provides an array substrate, comprising:

[0025] substrate;

[0026] A conductive layer is provided on the base substrate, wherein the conductive layer comprises a conductive area and an electroplating area distributed in a pattern, and the conductive area and the electroplating area are spaced apart;

[0027] The electroplating layer is arranged on the conductive layer corresponding to the electroplating area.

[0028] Optionally, in some embodiments of the present application, the conductive area includes a conductive electrode, the electroplating area includes a routing portion and a seed portion, the routing portion is electrically connected to the seed portion; and the electroplating layer is arranged on the routing portion and the seed portion.

[0029] Optionally, in some embodiments of the present application, the electroplating area includes a plurality of the routing portions and a plurality of the seed portions, and each of the routing portions is electrically connected to a plurality of the seed portions.

[0030] Optionally, in some embodiments of the present application, the conductive electrode is in a strip shape, and a plurality of the routing portions are arranged in parallel along an extension direction of the conductive electrode.

[0031] Optionally, in some embodiments of the present application, the thickness of the conductive layer is greater than or equal to 0.5 micrometers and less than or equal to 0.6 micrometers; the thickness of the electroplating layer is greater than or equal to 6 micrometers.

[0032] Optionally, in some embodiments of the present application, the material of the conductive layer is the same as the material of the electroplating layer.

[0033] Accordingly, an embodiment of the present application further provides a display panel, comprising:

[0034] The array substrate described in any one of the above items;

[0035] A light emitting device is provided on the array substrate;

[0036] The packaging component is arranged on the light-emitting device.

[0037] The method for manufacturing an array substrate in an embodiment of the present application includes providing a base substrate; sequentially forming a conductive layer and a photoresist layer on the base substrate; patterning the photoresist layer and the conductive layer, wherein the patterned conductive layer includes electrically connected conductive areas and electroplating areas; removing the photoresist layer; forming an electroplating layer on the conductive layer at locations corresponding to the electroplating areas; and disconnecting the electroplating areas from the conductive areas. In the present application, the photoresist layer on the conductive layer is removed before forming the electroplating layer, so that the photoresist layer is only used for patterning the conductive layer. This allows for the use of a thinner photoresist layer, reduces the use of the photoresist layer, and thus reduces the manufacturing cost and energy consumption of the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 This is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0040] Figure 2 This embodiment of the present application provides Figure 1 Flowchart of step S300;

[0041] Figure 3 This embodiment of the present application provides Figure 1 A schematic structural diagram of step S200;

[0042] Figure 4 This embodiment of the present application provides Figure 1 A schematic structural diagram of step S300;

[0043] Figure 5 This embodiment of the present application provides Figure 1 A schematic structural diagram of step S400;

[0044] Figure 6 This embodiment of the present application provides Figure 1 A top view of the structure of step S400;

[0045] Figure 7 This embodiment of the present application provides Figure 1 A schematic structural diagram of step S500;

[0046] Figure 8 This embodiment of the present application provides Figure 1 A top view of the structure of step S600;

[0047] Figure 9 This is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0048] Figure 10 Schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0049] Description of reference numerals:

[0050] DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0052] The embodiments of the present application provide a method for manufacturing an array substrate, an array substrate, and a display panel. Detailed descriptions are provided below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0053] First, the present invention provides a method for manufacturing an array substrate. Figure 1 and Figure 9 As shown, the method for manufacturing the array substrate mainly includes the following steps:

[0054] S100: Provide a base substrate 110. The base substrate 110 serves as the support structure of the array substrate 100, and is used to support other functional film layers in the array substrate 100 to ensure the overall structural stability of the array substrate 100. The base substrate 110 can be made of a glass substrate or other materials, as long as the base substrate 110 has sufficient supporting capacity.

[0055] Before making other film layers on the base substrate 110, the base substrate 110 needs to be cleaned first to ensure that there is no oil stains or other pollutants on the surface of the base substrate 110 to avoid affecting the connection strength between the subsequent film layers and the base substrate 110, thereby ensuring the structural stability between the film layers of the array substrate 100 and the base substrate 110.

[0056] S200 , forming a conductive layer 120 and a photoresist layer 200 in sequence on the base substrate 110 .

[0057] like Figure 3 As shown, after processing the base substrate 110, a conductive layer 120 is first deposited on the base substrate 110. The conductive layer 120 serves as a seed layer for the metal film layer in the array substrate 100 and is used for circuit conduction during the subsequent manufacturing process. The conductive layer 120 can be made of a metal material such as copper, aluminum, titanium, or molybdenum to ensure that the conductive layer 120 has good conductivity. In the embodiment of the present application, the conductive layer 120 is made of copper with a low resistivity to reduce the overall internal resistance of the array substrate 100 and prevent the internal resistance voltage drop caused by the conductive layer 120 from affecting the performance of the array substrate 100.

[0058] After the conductive layer 120 is formed, a photoresist layer 200 is formed on the conductive layer 120. The material of the photoresist layer 200 includes positive photoresist or negative photoresist. Depending on the type of photoresist, the exposure method used is also different, thereby forming different target patterns.

[0059] S300 , patterning the photoresist layer 200 and the conductive layer 120 , wherein the patterned conductive layer 120 includes an electrically connected conductive area 121 and an electroplating area 122 .

[0060] like Figure 4As shown, the conductive layer 120 and the photoresist layer 200 are both formed on the base substrate 110 using a full-surface fabrication method. Based on the structural design requirements of the array substrate 100, the conductive layer 120 needs to be patterned to form different conductive structures. During the patterning of the conductive layer 120, the photoresist layer 200 can serve as a mask for the conductive layer 120. That is, the target pattern of the conductive layer 120 can be formed based on the pattern of the photoresist layer 200 to form electrically connected conductive areas 121 and electroplating areas 122 on the base substrate 110.

[0061] The conductive region 121 primarily functions as a conductor, connecting the electroplating region 122 to an external circuit. The electroplating region 122, in turn, forms a plating structure to facilitate the formation of the target film layer. Furthermore, the electroplating region 122 is electrically connected to the conductive region 121, ensuring that the patterned conductive layer 120 maintains continuity throughout the entire circuit, facilitating subsequent fabrication processes.

[0062] Optional, such as Figure 2 As shown, step S300 in the embodiment of the present application mainly includes the following steps:

[0063] S310 , patterning the photoresist layer 200 to partially expose the conductive layer 120 .

[0064] After the conductive layer 120 and the photoresist layer 200 are sequentially formed on the base substrate 110 , the photoresist layer 200 needs to be patterned according to the design requirements of the array substrate 100 to form a target pattern. The patterned photoresist layer 200 can be used as a mask.

[0065] When the photoresist layer 200 is a positive photoresist, the portion of the photoresist layer 200 exposed to light will dissolve in the photoresist developer, while the portion not exposed to light will not dissolve in the photoresist developer. That is, the portion of the photoresist layer 200 not exposed to light remains and forms a target pattern. When the photoresist layer 200 is a negative photoresist, the portion of the photoresist layer 200 exposed to light will not dissolve in the photoresist developer, while the portion not exposed to light will dissolve in the photoresist developer. That is, the portion of the photoresist layer 200 exposed to light remains and forms a target pattern.

[0066] S320, patterning the conductive layer 120, removing the exposed portion of the conductive layer 120 to form a conductive electrode 1211, a connecting portion 1212, a routing portion 1221 and a seed portion 1223, the conductive electrode 1211 and the connecting portion 1212 constitute a conductive area 121, the routing portion 1221 and the seed portion 1223 constitute an electroplating area 122; the routing portion 1221 is electrically connected to the seed portion 1223, and the connecting portion 1212 is connected between the conductive electrode 1211 and the routing portion 1221, so that the electroplating area 122 is electrically connected to the conductive area 121.

[0067] After the photoresist layer 200 is patterned, a portion of the conductive layer 120 is exposed. The conductive layer 120 is then patterned using the patterned photoresist layer 200 as a mask, and the exposed portion of the conductive layer 120 is removed to obtain a target pattern of the conductive layer 120. That is, the pattern shapes of the conductive layer 120 and the photoresist layer 200 after patterning remain consistent. By adjusting the patterning method of the photoresist layer 200 according to the design requirements of the conductive layer 120, conductive layers 120 with different structures can be obtained.

[0068] After patterning the conductive layer 120, the conductive layer 120 is divided into a conductive area 121 and a plating area 122. The conductive area 121 includes a conductive electrode 1211 and a connecting portion 1212, and the plating area 122 includes a routing portion 1221 and a seed portion 1223. The routing portion 1221 is electrically connected to the seed portion 1223 to achieve circuit conductivity within the plating area 122. The connecting portion 1212 is connected between the conductive electrode 1211 and the routing portion 1221, thereby achieving conductivity between the conductive area 121 and the plating area 122. Furthermore, the conductive electrode 1211 is used to connect to an external circuit, and the connecting portion 1212 serves as a conductive channel to connect the plating area 122 to the external circuit, facilitating the subsequent electroplating process.

[0069] It should be noted that the conductive electrode 1211 is connected to the routing portion 1221 through the connecting portion 1212, so that when the structure and position of the conductive electrode 1211 remain unchanged, the setting position of the connecting portion 1212 can be adjusted accordingly according to the specific structure of the routing portion 1221 and the seed portion 1223 in the electroplating area 122, thereby making the electrical connection method between the conductive electrode 1211 and the routing portion 1221 more flexible, which is helpful to the overall structural layout design of the conductive layer 120.

[0070] In some embodiments, as Figure 6 As shown, when the conductive layer 120 is patterned, a plurality of seed portions 1223 can be formed, and the routing portion 1221 is electrically connected to the plurality of seed portions 1223 at the same time. The routing portion 1221 is electrically connected to the plurality of seed portions 1223 through one routing portion 1221, and then the routing portion 1221 is electrically connected to the conductive electrode 1211 through the connecting portion 1212. While ensuring that the conductive electrode 1211 is electrically connected to the plurality of seed portions 1223 at the same time, the connection method between the conductive electrode 1211 and the plurality of seed portions 1223 is simplified.

[0071] In other embodiments, the conductive layer 120 includes multiple routing portions 1221, each of which is electrically connected to the multiple seed portions 1223. Furthermore, the conductive layer 120 includes multiple connecting portions 1212, each of which is connected one-to-one with the multiple routing portions 1221 to achieve electrical connection between the conductive electrodes 1211 and the multiple routing portions 1221. The distribution of the multiple routing portions 1221 can meet different structural design requirements for the conductive layer 120, thereby expanding the scope of application of the array substrate 100.

[0072] Among them, such as Figure 6 As shown, the conductive electrode 1211 is strip-shaped, and multiple wiring portions 1221 are arranged in parallel along the extension direction of the conductive electrode 1211, and multiple connecting portions 1212 are connected one-to-one between the conductive electrode 1211 and the wiring portion 1221. This structural design is conducive to the parallel arrangement of multiple seed portions 1223, avoiding mutual crosstalk and affecting the subsequent electroplating process.

[0073] It should be noted that, along the extension direction of the conductive electrode 1211, the width dimension of the connecting portion 1212 is smaller than the width dimension of the corresponding connected wiring portion 1221, so that the connecting portion 1212 and the wiring portion 1221 can be directly distinguished in appearance and shape. At the same time, this design method helps to disconnect the conductive electrode 1211 from the wiring portion 1221 by subsequent processing of the connecting portion 1212.

[0074] S400 , removing the photoresist layer 200 .

[0075] like Figure 5 and Figure 6 As shown, after the patterning process of the conductive layer 120 is completed, the photoresist layer 200 covering the conductive layer 120 needs to be removed to facilitate the production of subsequent film layers on the conductive layer 120, that is, the photoresist layer 200 in the embodiment of the present application is only used to pattern the conductive layer 120.

[0076] S500 , forming an electroplating layer 130 on the conductive layer 120 at a position corresponding to the electroplating area 122 .

[0077] like Figure 7As shown, after removing the photoresist layer 200, it is necessary to form an electroplating layer 130 on the conductive layer 120 to complete the fabrication of the metal layer in the array substrate 100. Since the electroplating area 122 in the conductive layer 120 is the functional area of ​​the array substrate 100, and the conductive area 121 is only used to connect the electroplating area 122 to the external circuit to facilitate the normal electroplating process, when forming the electroplating layer 130, it is sufficient to ensure that only one electroplating layer 130 is formed at the position of the conductive layer 120 corresponding to the electroplating area 122. This design not only ensures the normal use of the array substrate 100, but also reduces the formation of unnecessary electroplating layers 130, thereby reducing the manufacturing cost of the array substrate 100.

[0078] Specifically, forming an electroplating layer 130 at a position corresponding to the electroplating area 122 on the conductive layer 120 mainly includes the following steps:

[0079] First, an electrolytic cell is provided, which includes an anode, a cathode, and an electrolyte electrically connected between the anode and the cathode; then, the wiring portion 1221 and the seed portion 1223 of the conductive layer 120 are placed in the electrolyte of the electrolytic cell, and the conductive electrode 1211 of the conductive layer 120 is electrically connected to the cathode of the electrolytic cell; then, a preset current is applied between the anode and the cathode of the electrolytic cell to form a layer of electroplating 130 on the wiring portion 1221 and the seed portion 1223.

[0080] The electrolyte is a mixed solution containing plating ions. The type of plating ions is directly related to the material of the conductive layer 120. For example, in the embodiment of the present application, if the conductive layer 120 is made of copper, the electrolyte is a mixed solution containing copper ions. During the electroplating process, the plating ions migrate from the anode to the cathode of the electrolytic cell and are deposited at the cathode to form the plating layer 130.

[0081] In the embodiment of the present application, the wiring portion 1221 and the seed portion 1223 are placed in the electrolyte of the electrolytic cell, and the conductive electrode 1211 is electrically connected to the cathode of the electrolytic cell, and the anode of the electrolytic cell is also electrically connected to the electrolyte, thereby forming a conductive loop. Because the area where the wiring portion 1221 and the seed portion 1223 are located is the main functional area of ​​the array substrate 100, during electroplating, only the wiring portion 1221 and the seed portion 1223 can be placed in the electrolyte, so that the electroplating layer 130 is only formed on the wiring portion 1221 and the seed portion 1223, thereby maximizing the utilization of the electroplating layer 130 and avoiding the formation of the electroplating layer 130 in other unnecessary areas, which would increase production costs.

[0082] In some embodiments, since the connecting portion 1212 is connected between the conductive electrode 1211 and the routing portion 1221, although the connecting portion 1212 only serves as a conductive channel between the conductive electrode 1211 and the routing portion 1221, during electroplating, the connecting portion 1212 can be partially placed in the electrolyte to ensure that the routing portion 1221 and the seed portion 1223 can be completely immersed in the electrolyte, thereby ensuring that a uniform and stable electroplating layer 130 can be formed on the surface of the routing portion 1221 and the seed portion 1223.

[0083] Among them, the immersion degree of the connecting part 1212 in the electrolyte can be adjusted accordingly according to the actual situation. It is only necessary to ensure the stable formation of the electroplating layer 130 on the surface of the wiring part 1221 and the seed part 1223. No special limitation is made here.

[0084] It should be noted that the thickness and uniformity of the electroplating layer 130 are directly related to the concentration of the electroplating ions in the electrolyte, the electroplating time, and the electroplating current. If a thicker electroplating layer 130 is required, the concentration of the electroplating ions in the electrolyte and the electroplating time can be increased accordingly; if the uniformity of the electroplating layer 130 is required at the same time, the electroplating current can be reduced accordingly to reduce the deposition rate of the electroplating ions on the surface of the routing portion 1221 and the seed portion 1223, thereby ensuring uniform deposition of the electroplating layer 130. Among them, the concentration of the electroplating ions, the electroplating time, and the size of the electroplating current can be adjusted accordingly according to actual electroplating requirements and are not specifically limited here.

[0085] S600 , disconnecting the electroplating area 122 from the conductive area 121 .

[0086] like Figure 8 and Figure 9 As shown, after the electroplating layer 130 is completed, the electroplating current between the anode and cathode of the electrolytic cell is disconnected, the conductive electrode 1211 is disconnected from the cathode of the electrolytic cell, and the wiring portion 1221 and the seed portion 1223 are removed from the electrolyte. Since the electroplating area 122 and the conductive area 121 are still electrically connected at this time, that is, the conductive layer 120 as a whole is in a mutually conductive state, if the subsequent film layer is directly produced, the conductive and disconnected states of the entire conductive layer 120 and the electroplating layer 130 will always remain consistent during the use of the array substrate 100, and it is impossible to achieve independent control of a certain area on the array substrate 100. Therefore, it is necessary to disconnect the electroplating area 122 from the conductive area 121 and adjust the connection method between the wiring portion 1221 and the seed portion 1223 in the electroplating area 122 to achieve different control requirements of the array substrate 100.

[0087] Optionally, when disconnecting the electroplating area 122 from the conductive area 121, the connection portion 1212 can be removed or disconnected by laser to disconnect the conductive electrode 1211 from the wiring portion 1221, so as to disconnect the electroplating area 122 from the conductive area 121. This process further illustrates that the setting of the connection portion 1212 is only used as a conductive channel between the conductive electrode 1211 and the wiring portion 1221.

[0088] If the conductive electrode 1211 and the wiring portion 1221 are directly connected without the connection portion 1212, the conductive electrode 1211 needs to be partially removed when disconnecting the electroplating area 122 from the conductive area 121. However, the area of ​​the conductive electrode 1211 that needs to be removed is larger than that of the connection portion 1212, resulting in increased energy consumption. Alternatively, if the wiring portion 1221 is partially removed, the electroplating layer 130 formed on the wiring portion 1221 may be damaged, potentially affecting the overall performance of the array substrate 100. Therefore, the provision of the connection portion 1212 can also reduce production energy consumption and ensure the structural stability of the electroplating layer 130.

[0089] It should be noted that during electroplating, the connection portion 1212 can be partially placed in the electrolyte, and the electroplating layer 130 will also form on the surface of this portion, while the portion outside the electrolyte will not form the electroplating layer 130. When disconnecting the electroplating area 122 from the conductive area 121, a laser can be used to remove the portion of the connection portion 1212 where the electroplating layer 130 is not formed, thereby further reducing energy consumption in the production of the array substrate 100 and saving production costs.

[0090] Optionally, when laser treatment is used to remove the connection portion 1212, the routing portion 1221 and the electroplating layer 130 on the routing portion 1221 can be patterned simultaneously to form a conductive routing portion 1222, electrically connecting the conductive routing portion 1222 to the seed portion 1223. Patterning the routing portion 1221 to form the conductive routing portion 1222 facilitates routing design and electrical connection between the array substrate 100 and other functional layers.

[0091] In some embodiments, the conductive layer 120 includes a plurality of seed portions 1223 and a plurality of conductive traces 1222, and the plurality of seed portions 1223 are distributed in an array, that is, the plurality of seed portions 1223 are distributed in multiple rows and columns, and each conductive trace 1222 is electrically connected to each column of seed portions 1223, that is, during the use of the array substrate 100, the on and off states of the seed portions 1223 on each column remain consistent, thereby facilitating the synchronous control of the seed portions 1223 in the same column on the array substrate 100 and the electroplating layer 130 on the seed portions 1223, so as to simplify the control method of the array substrate 100.

[0092] It should be noted that the array substrate 100 includes a thin film transistor layer, which includes multiple metal layers, each of which can be manufactured using the above-described manufacturing method as required. In the embodiment of the present application, the seed portion 1223 and the electroplated layer 130 on the seed portion 1223 form one or more of a gate, a gate line, a source / drain electrode, and a data line. By designing the positions of the gate and the source / drain electrode, thin film transistor layers with different structures can be obtained.

[0093] Among them, the gate and the gate line are located in the same film layer, and the source, drain and data lines are located in the same film layer. This structural design facilitates the routing design between the gate line and the data line, avoiding mutual crosstalk or short circuit that may cause failure of the array substrate 100.

[0094] Optionally, in the embodiment of the present application, the thickness of the photoresist layer 200 is greater than or equal to 1 micron and less than or equal to 1.5 microns. If the thickness of the photoresist layer 200 is too thin, the photoresist layer 200 after patterning will not be able to effectively serve as a mask, thereby affecting the patterning process of the conductive layer 120. If the thickness of the photoresist layer 200 is too thick, the amount of photoresist layer 200 used will be too large, and the energy consumption during the patterning process of the photoresist layer 200 will also be high, resulting in higher production costs.

[0095] During the actual production process, the thickness of the photoresist layer 200 can be set to 1 micron, 1.2 microns, 1.4 microns, or 1.5 microns, etc. This can ensure that the photoresist layer 200 can serve as a mask for the patterning process of the conductive layer 120, while also preventing the photoresist layer 200 from being too thick, which would lead to excessive production costs and energy consumption. The specific value of the thickness of the photoresist layer 200 can be adjusted accordingly according to actual design requirements and is not specifically limited here.

[0096] The method for manufacturing the array substrate 100 in the embodiment of the present application includes providing a base substrate 110; sequentially forming a conductive layer 120 and a photoresist layer 200 on the base substrate 110; patterning the photoresist layer 200 and the conductive layer 120, wherein the patterned conductive layer 120 includes an electrically connected electroplating region 122 and a conductive region 121; removing the photoresist layer 200; forming an electroplating layer 130 on the conductive layer 120 at a location corresponding to the electroplating region 122; and disconnecting the electroplating region 122 from the conductive region 121. By removing the photoresist layer 200 on the conductive layer 120 before forming the electroplating layer 130, the photoresist layer 200 is used only for patterning the conductive layer 120. This allows for the use of a thinner photoresist layer 200, thereby reducing the use of the photoresist layer 200 and thereby reducing the manufacturing cost and energy consumption of the array substrate 100.

[0097] Secondly, an embodiment of the present application also provides an array substrate, which can be manufactured using the above-mentioned manufacturing method. Since this array substrate adopts all the technical solutions of all the above-mentioned embodiments, it at least has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.

[0098] Figure 9 is a structural diagram of an array substrate provided in an embodiment of the present application, such as Figure 9 As shown, the array substrate 100 includes a base substrate 110, which serves as a supporting structure of the array substrate 100 and is used to support other functional film layers in the array substrate 100 to ensure the overall structural stability of the array substrate 100. The base substrate 110 can be made of a glass substrate or other types of materials.

[0099] The array substrate 100 includes a conductive layer 120 disposed on a base substrate 110. The conductive layer 120 includes a patterned conductive area 121 and an electroplating area 122, with the conductive area 121 and the electroplating area 122 spaced apart. The conductive area 121 primarily functions as a conductor, connecting the electroplating area 122 to an external circuit during fabrication of the array substrate 100. The electroplating area 122 forms an electroplating structure to facilitate the formation of the target film layer. After fabrication of the array substrate 100, however, the conductive area 121 and the electroplating area 122 are spaced apart to facilitate independent control of a specific area on the array substrate 100, thereby meeting the diverse control requirements of the array substrate 100.

[0100] The array substrate 100 includes an electroplating layer 130, which is disposed on the conductive layer 120 corresponding to the electroplating area 122. The electroplating layer 130 and the conductive layer 120 together form a target film layer. The array substrate 100 includes a thin film transistor layer, which includes multiple metal layers. The electroplating layer 130 and the conductive layer 120 corresponding to the electroplating area 122 together form a metal layer.

[0101] Optionally, the conductive area 121 includes a conductive electrode 1211 , the electroplating area 122 includes a routing portion 1221 and a seed portion 1223 , the routing portion 1221 is electrically connected to the seed portion 1223 , and the electroplating layer 130 is disposed on the routing portion 1221 and the seed portion 1223 .

[0102] Among them, such as Figure 8As shown, during the fabrication of the array substrate 100, the conductive electrode 1211 is used to connect to an external circuit to facilitate the electroplating process in the electroplating area 122. The electroplating area 122, as the primary functional area of ​​the array substrate 100, is used to form a target film layer. By electrically connecting the routing portion 1221 to the seed portion 1223, electrical conduction is achieved within the electroplating area 122, facilitating the fabrication of the target film layer in the electroplating area 122 and circuit control during the use of the array substrate 100.

[0103] Optionally, the electroplating area 122 includes multiple routing portions 1221 and multiple seed portions 1223, and each routing portion 1221 is electrically connected to multiple seed portions 1223. By electrically connecting one routing portion 1221 to multiple seed portions 1223, multiple seed portions 1223 can be synchronously controlled by one routing portion 1221 during use of the array substrate 100, thereby simplifying the overall circuit control on the array substrate 100.

[0104] In the embodiment of the present application, the seed portion 1223 and the electroplated layer 130 thereon form one or more of a gate, a gate line, a source / drain, and a data line. By designing the positions of the gate and the source / drain, thin film transistor layers with different structures can be obtained.

[0105] It should be noted that the thin film transistor layer includes multiple thin film transistors, and the multiple thin film transistors are distributed in an array. Each thin film transistor includes a gate and a source and drain, that is, each thin film transistor includes a seed portion 1223. Therefore, the conductive layer 120 includes multiple seed portions 1223, and the multiple seed portions 1223 are distributed in an array to form an array-distributed thin film transistor.

[0106] Among them, the routing portion 1221 and the electroplating layer 130 on the routing portion 1221 can form multiple conductive routing portions 1222, and each conductive routing portion 1222 can be electrically connected to a column of seed portions 1223, that is, each conductive routing portion 1222 is electrically connected to a column of thin-film transistors to achieve synchronous control of the column of thin-film transistors, which helps to simplify the circuit control method of the array substrate 100.

[0107] Optionally, the conductive electrode 1211 is strip-shaped, and the multiple routing portions 1221 are arranged in parallel along the extension direction of the conductive electrode 1211. Since each routing portion 1221 is electrically connected to multiple seed portions 1223 at the same time, this structural design facilitates the parallel arrangement of multiple seed portions 1223 connected to different routing portions 1221, avoiding crosstalk that affects the normal use of the array substrate 100.

[0108] It should be noted that the conductive electrode 1211 is located at the edge of the base substrate 110, that is, multiple wiring portions 1221 are arranged side by side on the same side of the conductive electrode 1211. This structural design ensures that when the array substrate 100 is in use, the conductive electrode 1211 will not affect the electrical connection between other functional film layers and the wiring portion 1221, which helps to optimize the circuit design in the array substrate 100.

[0109] Optionally, in the embodiment of the present application, the thickness of the conductive layer 120 is greater than or equal to 0.5 microns and less than or equal to 0.6 microns. If the thickness of the conductive layer 120 is too thin, the resistance of the conductive layer 120 will be too high, thereby affecting the electroplating process and hindering the stable formation of the electroplated layer 130. If the thickness of the conductive layer 120 is too thick, the energy consumption during the patterning process of the conductive layer 120 will be too high, thereby increasing production costs.

[0110] During the actual production process, the thickness of the conductive layer 120 can be set to 0.5 microns, 0.52 microns, 0.55 microns, 0.58 microns or 0.6 microns, etc., which can not only ensure the stable formation of the electroplating layer 130, but also avoid excessive energy consumption during the patterning process of the conductive layer 120. The specific value of the thickness of the conductive layer 120 can be adjusted accordingly according to actual design requirements, and no special limitation is made here.

[0111] Optionally, in the embodiment of the present application, the thickness of the electroplating layer 130 is greater than or equal to 6 microns. If the thickness of the electroplating layer 130 is too thin, the resistance of the metal layer in the array substrate 100 formed will be too high, resulting in an excessively high internal resistance of the metal layer itself, which will result in a greater internal resistance voltage drop, thereby affecting the overall performance of the array substrate 100.

[0112] In actual manufacturing, the thickness of the electroplating layer 130 can be set to 6 microns, 8 microns, 10 microns, or 12 microns, etc., to ensure that the internal resistance of the electroplating layer 130 itself is low, thereby ensuring stable use of the array substrate 100. The specific thickness of the electroplating layer 130 can be adjusted accordingly according to actual design requirements and is not particularly limited here.

[0113] It should be noted that in the embodiment of the present application, the material of the conductive layer 120 is the same as that of the electroplating layer 130. The electroplating layer 130 is formed by deposition of electroplating ions from an electrolyte on the conductive layer 120. That is, the type of electroplating ions and the material of the conductive layer 120 are the same. Using the same type of electroplating ions and conductive layer 120 can, on the one hand, avoid a significant difference in activity between the conductive layer 120 and the electroplating layer 130, which could affect the stability of the electroplating layer 130 and the conductive layer 120. On the other hand, it can help improve the connection strength between the electroplating layer 130 and the conductive layer 120, preventing delamination between the electroplating layer 130 and the conductive layer 120 during the manufacture or use of the array substrate 100, which could affect the structural stability of the array substrate 100.

[0114] Finally, an embodiment of the present application also provides a display panel, which includes an array substrate. The specific structure of the array substrate refers to the above embodiment. Since this display panel adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0115] Figure 10 is a schematic structural diagram of a display panel provided in an embodiment of the present application, such as Figure 10 As shown, the display panel 10 includes an array substrate 100 , a light emitting device 300 and a packaging component 400 . The light emitting device 300 is disposed on the array substrate 100 , and the packaging component 400 is disposed on the light emitting device 300 .

[0116] The light-emitting device 300 includes a plurality of light-emitting pixels arranged in an array. Each light-emitting pixel is electrically connected to a corresponding thin-film transistor in the array substrate 100. The light emission of the light-emitting pixel can be controlled by turning the thin-film transistor on and off. Because the seed portions 1223 in each column of thin-film transistors are electrically connected together, when the light emission of the light-emitting device 300 is regulated, the light emission of the pixels in the same column can be regulated simultaneously, thereby simplifying the control method of the circuit in the display panel 10.

[0117] The packaging component 400 includes a multi-layer stacked packaging layer, which is used to protect the light-emitting pixels in the light-emitting device 300 and the thin film transistors in the array substrate 100 to prevent moisture or oxygen in the air from entering the display panel 10 and corroding the relevant functional film layers, thereby causing the display panel 10 to fail.

[0118] It should be noted that the display panel 10 in the embodiment of the present application has a very wide range of applications, including various display and lighting display devices such as televisions, computers, mobile phones, foldable and rollable display screens, as well as wearable devices such as smart bracelets and smart watches, all of which are within the scope of the application field of the display panel 10 in the embodiment of the present application.

[0119] The above is a detailed introduction to the manufacturing method of an array substrate, an array substrate and a display panel provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for manufacturing an array substrate, characterized in that: The method comprises: providing a substrate; forming a conductive layer and a photoresist layer in sequence on the base substrate; performing patterning on the photoresist layer and the conductive layer, wherein the conductive layer after patterning comprises an electrically connected conductive area and an electroplating area; removing the photoresist layer; Providing an electrolytic cell comprising an anode, a cathode, and an electrolyte electrically connected between the anode and the cathode; placing the conductive layer corresponding to the electroplating area in the electrolyte of the electrolytic cell; electrically connecting the conductive layer corresponding to the conductive area to the cathode of the electrolytic cell; applying a preset current between the anode and cathode of the electrolytic cell to form an electroplating layer on the conductive layer at a position corresponding to the electroplating area; The electroplating area is disconnected from the conductive area.

2. The method for manufacturing an array substrate according to claim 1, wherein: The patterning of the photoresist layer and the conductive layer comprises: performing patterning on the photoresist layer to partially expose the conductive layer; The conductive layer is patterned to remove the exposed portion of the conductive layer to form a conductive electrode, a connecting portion, a routing portion and a seed portion, wherein the conductive electrode and the connecting portion constitute a conductive area, and the routing portion and the seed portion constitute an electroplating area; the routing portion is electrically connected to the seed portion, and the connecting portion is connected between the conductive electrode and the routing portion, so that the electroplating area is electrically connected to the conductive area.

3. The method for manufacturing an array substrate according to claim 2, wherein: The conductive layer corresponding to the electroplating area is placed in the electrolyte of the electrolytic cell; the conductive layer corresponding to the conductive area is electrically connected to the cathode of the electrolytic cell; Applying a preset current between the anode and cathode of the electrolytic cell to form an electroplating layer on the conductive layer at a position corresponding to the electroplating area, comprising: placing the routing portion and the seed portion in an electrolyte of an electrolytic cell; electrically connecting the conductive electrode to the cathode of the electrolytic cell; A preset current is applied between the anode and cathode of the electrolytic cell to form an electroplating layer on the wiring portion and the seed portion.

4. The method for manufacturing an array substrate according to claim 2, wherein: The step of disconnecting the electroplating area from the conductive area comprises: The connecting portion is removed or cut off to disconnect the conductive electrode from the wiring portion, thereby disconnecting the electroplating area from the conductive area.

5. The method for manufacturing an array substrate according to claim 2, wherein: The method further comprises: The routing portion and the electroplating layer on the routing portion are patterned to form a conductive routing, so that the conductive routing is electrically connected to the seed portion.

6. The method for manufacturing an array substrate according to any one of claims 1 to 5, wherein: The thickness of the photoresist layer is greater than or equal to 1 micron and less than or equal to 1.5 microns.

7. An array substrate, characterized in that: The array substrate is manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 6, and the array substrate comprises: substrate; A conductive layer is provided on the substrate, the conductive layer comprising a conductive area and an electroplating area distributed in a pattern, the conductive area and the electroplating area are spaced apart and disconnected; The electroplating layer is arranged on the conductive layer corresponding to the electroplating area.

8. The array substrate according to claim 7, wherein: The conductive area includes a conductive electrode, the electroplating area includes a wiring portion and a seed portion, the wiring portion is electrically connected to the seed portion; and the electroplating layer is provided on the wiring portion and the seed portion.

9. The array substrate according to claim 8, wherein: The electroplating area includes a plurality of the routing portions and a plurality of the seed portions, and each of the routing portions is electrically connected to a plurality of the seed portions.

10. The array substrate according to claim 9, wherein: The conductive electrode is in a strip shape, and a plurality of the wiring portions are arranged in parallel along an extension direction of the conductive electrode.

11. The array substrate according to claim 7, wherein: The thickness of the conductive layer is greater than or equal to 0.5 micrometers and less than or equal to 0.6 micrometers; the thickness of the electroplating layer is greater than or equal to 6 micrometers.

12. The array substrate according to claim 7, wherein: The material of the conductive layer is the same as that of the electroplating layer.

13. A display panel, characterized in that: The display panel includes: The array substrate according to any one of claims 7 to 12; A light emitting device is provided on the array substrate; The packaging component is arranged on the light-emitting device.

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