Compound logic gate circuits and computing devices

Abstract

The present disclosure relates to a composite logic gate circuit and a computing device. The composite logic gate circuit includes: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS tube and a first NMOS tube; the first logic gate circuit is configured to receive a first input signal and a second input signal, and output a first output signal, the inverter circuit includes a second PMOS tube and a second NMOS tube, the source of the second PMOS tube is coupled to a power input terminal, the drain is coupled to the drain of the second NMOS tube, and the gate is configured to receive the first output signal, the source of the second NMOS tube is coupled to a ground terminal, the gate is configured to receive the first output signal, the source of the first PMOS tube is coupled to the drain of the second PMOS tube, the drain is coupled to the drain of the first NMOS tube, and the gate is configured to receive a third input signal, the source of the first NMOS tube is configured to receive the first output signal, and the gate is configured to receive the third input signal, and the first logic gate circuit is a NAND gate circuit or a NOR gate circuit.

Description

Technical Field

[0001] The present disclosure relates to a complex logic gate circuit, and more particularly to a transistor-level low-power AND-XOR (AND exclusive OR) gate circuit and a complex logic gate circuit such as an OR-XOR (or exclusive OR) gate circuit, an AND-XNOR (AND exclusive OR) gate circuit or an OR-XNOR (or exclusive OR) gate circuit, and a computing device including such a complex logic gate circuit. Background Art

[0002] With the continuous reduction of integrated circuit process size and the rapid development of design technology, integrated circuits are developing towards a larger scale and more complex trend. Power consumption has become one of the severe challenges facing the development of integrated circuits. At present, almost all digital circuit design methods use Boolean logic based on the "AND", "OR", and "NOT" operation set, which can be called traditional Boolean (TB) logic. It can be considered that part of the challenges faced by today's integrated circuit design are due to the limitations of traditional Boolean logic itself. In fact, digital circuits can be implemented using traditional Boolean logic based on "AND", "OR", and "NOT" gate circuits, or using Reed-Muller (RM) logic based on AND-XOR, OR-XOR gate circuits.

[0003] Compared with TB logic, RM logic has the following advantages: (1) It is much simpler to implement arithmetic operations, parity check functions and other logical functions using RM logic than TB logic. For example, for a parity checker with n variables, it takes 2 n 1. The AND-XOR gate circuit is a commonly used RM composite logic gate circuit that can be used to implement arithmetic operations / parity checks and other functions. It has cost and power consumption advantages over simple logic gate circuits based on AND, OR, and NOT gate circuits.

[0004] However, one of the reasons why RM logic has not been widely used in the industry like TB logic is the lack of a low-power cell library suitable for RM logic synthesis. In recent years, although there have been studies on AND-XOR gate circuits, all of them are structures obtained by cascading AND gate circuits and XOR / XNOR gate circuits, which have problems such as large area and high power consumption.

[0005] Therefore, it is expected to propose a novel AND-XOR gate circuit and a similar complex logic gate circuit based on transistor-level design that can reduce cost and power consumption. Summary of the invention

[0006] According to one aspect of the present disclosure, a composite logic gate circuit is provided, and the composite logic gate circuit may include: a simple logic gate circuit, a first PMOS transistor and a first NMOS transistor; wherein the simple logic gate circuit may include a first logic gate circuit and an inverter circuit, wherein the first logic gate circuit may be configured to receive a first input signal and a second input signal, and output a first output signal, wherein the inverter circuit may include a second PMOS transistor and a second NMOS transistor, wherein the source of the second PMOS transistor is coupled to a power input terminal, the drain is coupled to the drain of the second NMOS transistor, the gate is configured to receive the first output signal, and the source of the second NMOS transistor is coupled to the power input terminal. connected to the ground terminal, the drain is coupled to the drain of the second PMOS tube, and the gate is configured to receive the first output signal, wherein the source of the first PMOS tube is coupled to the drains of the second PMOS tube and the second NMOS tube, the drain is coupled to the drain of the first NMOS tube, and the gate is configured to receive a third input signal, wherein the source of the first NMOS tube is configured to receive the first output signal, the drain is coupled to the drain of the first PMOS tube, and the gate is configured to receive the third input signal, and wherein the simple logic gate circuit can be an AND gate circuit or an OR gate circuit, and the first logic gate circuit can correspondingly be a NAND gate circuit or a NOR gate circuit.

[0007] According to another aspect of the present disclosure, a computing device is provided, wherein the computing device includes the composite logic gate circuit as described above.

[0008] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0010] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0011] Figure 1 The structure diagram of a conventional AND-XOR gate circuit obtained by cascading a CMOS AND gate circuit and a CMOS XOR gate circuit based on a transistor-level design is schematically shown;

[0012] Figure 2The schematic diagram shows the structure of the XOR gate circuit implemented by the transfer transistor logic;

[0013] Figure 3 A schematic diagram of the structure of a composite logic gate circuit based on transistor-level design according to an embodiment of the present invention is shown;

[0014] Figure 4 A schematic diagram of the structure of a composite logic gate circuit based on transistor-level design according to another embodiment of the present invention is shown;

[0015] Figure 5 A schematic diagram of the structure of another complex logic gate circuit based on transistor-level design according to another embodiment of the present invention is shown;

[0016] Fig. 6A and Figure 6B The structural diagrams of the CMOSNAND gate circuit and the CMOSNOR gate circuit included in the composite logic gate circuit based on transistor-level design according to the embodiments of the present invention are schematically shown respectively.

[0017] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0018] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION

[0019] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0020] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure and its application or use. That is, the circuits and methods herein are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in the present disclosure, and are not intended to be limiting. Those skilled in the art will appreciate that they merely illustrate exemplary ways that can be used to implement the present disclosure, and are not exhaustive ways.

[0021] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0022] Figure 1 The structure diagram of a conventional AND-XOR gate circuit 100 obtained by cascading a CMOS AND gate circuit and a CMOSXOR gate circuit based on transistor-level design is schematically shown.

[0023] exist Figure 1 In the present invention, a common complementary static CMOS logic gate circuit can be used to implement the AND-XOR gate circuit 100. The function expression of the output signal of the AND-XOR gate circuit 100 at the output terminal Y1 can satisfy Y1=AB⊕C, where ⊕ represents exclusive OR.

[0024] like Figure 1 As shown in FIG. 1 , the AND-XOR gate circuit 100 may include a NAND gate circuit 110 , an INV (inverter) gate circuit 120 , and a XOR gate circuit 130 , wherein the NAND gate circuit 110 and the INV gate circuit 120 may form a CMOS AND gate circuit.

[0025] The NAND gate circuit 110 may include PMOS transistors P11 and P12 and NMOS transistors N11 and N12. The NAND gate circuit 110 may receive a first input signal A at the gates of the PMOS transistors P11 and NMOS transistors N11, receive a second input signal B at the gates of the PMOS transistors P12 and NMOS transistors N12, and output a first output signal Y11 at an output terminal Y11 to which the drains of the PMOS transistors P11, P12 and NMOS transistor N11 are coupled. .

[0026] The INV gate circuit 120 may include a PMOS transistor P13 and an NMOS transistor N13. The INV gate circuit 120 may receive the first output signal at the gates of the PMOS transistor P13 and the NMOS transistor N13. , and a signal AB is outputted at an output terminal Y21 where the drains of the PMOS transistor P13 and the NMOS transistor N13 are coupled to each other.

[0027] Thus, the NAND gate circuit 110 and the INV gate circuit 120 may form an AND gate circuit, and an AND operation value of the input signals may be output at an output terminal of the AND gate circuit.

[0028] The XOR gate circuit 130 may include a NOR gate circuit and an AOI gate circuit. The NOR gate circuit may include PMOS transistors P14 and P15 and NMOS transistors N14 and N15, and receive input signals AB at the gates of the PMOS transistors P14 and N14, and receive input signals C at the gates of the PMOS transistors P15 and N15. The AOI gate circuit may include PMOS transistors P16, P17 and P18 and NMOS transistors N16, N17 and N18, and receive input signals AB at the gates of the PMOS transistors P17 and N17, and receive input signals C at the gates of the PMOS transistors P18 and N18, and output a signal AB⊕C at the output terminal Y1.

[0029] exist Figure 1 In the AND-XOR gate circuit 100 shown in FIG. 1 , the transistor is regarded as a switch controlled by a signal at its gate terminal. The AND-XOR gate circuit 100 formed by a static complementary CMOS gate circuit has the advantages of high noise tolerance, low output impedance, high input impedance, no static power consumption, etc. However, from Figure 1 It can be seen from the figure that the AND-XOR gate circuit 100 formed by the static complementary CMOS gate circuit shares 16 transistors, and the area and power consumption are still relatively large.

[0030] The applicant realizes that the XOR gate circuit 130 in the above design is composed of a NOR gate circuit + an AOI gate circuit, and uses 10 transistors P14-P18 and N14-N18. The applicant considers that the implementation based on transfer transistor logic (PTL) has the advantages of low power consumption and a small number of transistors. Specifically, when using transfer transistor logic, the original input is used to drive the gate and source / drain terminals to reduce the number of required transistors. In other words, the input signal can not only control the gate terminal of the transistor, but also drive the source / drain terminal. Specifically, when using transfer transistor logic, the XOR gate circuit can be implemented with 4 transistors.

[0031] Figure 2 The schematic diagram shows the structure of the XOR gate circuit 200 implemented by the transmission transistor logic.

[0032] like Figure 2As shown in, the XOR gate circuit 200 may include PMOS tubes P21, P22 and NMOS tubes N21, N22, wherein the PMOS tube P21 and the NMOS tube N21 may form an inverter circuit. The gate of the PMOS tube P21 receives the input signal A, the source is coupled to the power input terminal VDD, and the drain is coupled to the drain of the NMOS tube N21. The gate of the NMOS tube N21 receives the input signal A, the drain is coupled to the drain of the PMOS tube P21, and the source is coupled to the ground terminal VSS. The source of the PMOS tube P22 is coupled to the gate of the PMOS tube P21 and receives the input signal A, the gate is coupled to the gate of the NMOS tube and receives the input signal B, and the drain is coupled to the drain of the NMOS tube N22. The gate of the NMOS tube N22 is coupled to the gate of the PMOS tube P22 and receives the input signal B, the drain is coupled to the drain of the PMOS tube P22, and the source is coupled to the drains of the NMOS tube N21 and the PMOS tube P21. The XOR gate circuit 200 constructed in this way can output a signal A⊕B which is an exclusive OR value of input signals A and B at the output terminal.

[0033] exist Figure 1 In the AND-XOR gate circuit 100 shown in FIG. 1 , the CMOS AND gate circuit may include a NAND gate circuit 110 and an INV gate circuit 120, and includes 6 transistors. Figure 2 In the XOR gate circuit 200 shown in FIG. 1 , the XOR gate circuit 200 includes 4 transistors. Therefore, if Figure 1 The CMOSAND gate circuit in Figure 2 By directly combining the XOR gate circuits in the embodiment, an AND-XOR gate circuit composed of 10 transistors can be formed. However, the applicant realizes that Figure 1 The CMOS AND gate circuit in the embodiment may include an INV gate circuit composed of a PMOS transistor P13 and an NMOS transistor N13, and Figure 2 The XOR gate circuit 200 in the embodiment may include an inverter circuit formed by a PMOS transistor P21 and an NMOS transistor N21. Figure 1 The INV gate circuit formed by the PMOS tube P13 and the NMOS tube N13 as a part of the AND gate circuit is used as Figure 2 The inverter circuit formed by the PMOS tube P21 and the NMOS tube N21 shown in FIG. 1 and the corresponding signal connection mode are changed. Then, only Figure 1 Increase in Figure 2 The transistors corresponding to the PMOS tube P22 and the NMOS tube N22 in the Figure 1 The AND gate circuit in the AND-XOR gate circuit can be realized by adding only two transistors. In other words, the AND-XOR gate circuit can be realized by using only 6 transistors.

[0034] Of course, those skilled in the art will understand that Figure 1 When the NAND gate circuit in the AND-XOR gate circuit 100 is replaced by a NOR gate circuit, according to the concept of the present invention, an OR-XOR gate circuit can also be realized by adding only two transistors compared to the OR gate circuit.

[0035] Figure 3 The structure diagram of a composite logic gate circuit 300 based on transistor-level design according to an embodiment of the present invention is schematically shown.

[0036] like Figure 3 As shown in , the composite logic gate circuit 300 may include a simple logic gate circuit, a PMOS tube P32 (corresponding to the first PMOS tube) and an NMOS tube N32 (corresponding to the first NMOS tube), wherein the simple logic gate circuit may include a first logic gate circuit 310 and an inverter circuit formed by a PMOS tube P31 (corresponding to the second PMOS tube) and an NMOS tube N31 (corresponding to the second NMOS tube).

[0037] The first logic gate circuit 310 can be configured to receive a first input signal A and a second input signal B, and output a first output signal at an output terminal Y31. The source of the PMOS transistor P31 in the inverter circuit is coupled to the power input terminal VDD, the drain is coupled to the output terminal Y32, and the gate is configured to be coupled to the output terminal Y31 to receive the first output signal. The source of the NMOS transistor N31 in the inverter circuit is coupled to the ground terminal VSS, the drain is coupled to the output terminal Y32, and the gate is configured to be coupled to the output terminal Y31 to receive the first output signal.

[0038] The source of the PMOS transistor P32 is coupled to the drain of the PMOS transistor P31 instead of Figure 2 The source of the NMOS transistor N32 is coupled to the gate of the PMOS transistor P31 instead of the gate of the PMOS transistor P21 as shown in FIG. Figure 2 As shown in FIG. 1 , the drain of the PMOS transistor P21 is coupled to the output terminal Y3, and the gate is configured to receive the third input signal C. By changing the connection mode in this way, although the Figure 1 The CMOSAND gate circuit in Figure 2 Compared with the direct combination of the XOR gate circuit in the embodiment, the number of inverters formed by two transistors is reduced, but the AND / OR-XOR circuit can still be realized.

[0039] In addition, the first logic gate circuit 310 can be a NAND gate circuit or a NOR gate circuit. When the first logic gate circuit 310 is a NAND gate circuit, the above simple logic gate circuit can be an AND gate circuit, and the composite logic gate circuit 300 can be an AND-XOR gate circuit; and when the first logic gate circuit 310 is a NOR gate circuit, the above simple logic gate circuit can be an OR gate circuit, and the composite logic gate circuit 300 can be an OR-XOR gate circuit. The first logic gate circuit 310 can generally be formed by 4 transistors. The following description takes the first logic gate circuit 310 as a NAND gate circuit as an example.

[0040] When the first logic gate circuit 310 is a NAND gate circuit, the first output signal at the output terminal Y31 is , and the output signal at the output terminal Y32 is AB, so the output signal at the output terminal Y3 can be + C= AB⊕C, and the output signal at the output terminal Y3 conforms to the following truth table.

[0041]

[0042] It can be seen that in the composite logic gate circuit 300 as an AND-XOR gate circuit or an OR-XOR gate circuit, by using the inverter in the AND gate circuit or the OR gate circuit, only two transistors can be added compared to the AND gate circuit or the OR gate circuit to realize the AND-XOR gate circuit or the NOR-XOR gate circuit, such as Figure 3 As shown in . In this way, only 8 transistors are used to realize AND-XOR gate circuit or NOR-XOR gate circuit. Figure 1 The original design shown in is reduced by 50%, thereby reducing the area and power consumption of the AND-XOR gate circuit or the NOR-XOR gate circuit.

[0043] In the above embodiments, the transmission transistor logic can realize the logic function with the least number of transistors, but there is a problem that the node signal is not fully swinging. Figure 3 In the example, when AB=0 at the output terminal Y32, since the PMOS tube P32 has a weak ability to transmit 0 and the NMOS tube N32 has a weak ability to transmit 1, when C=0, Y3=0+Vthp (weak 0); and when C=1, Y3=VDD-Vthn (weak 1). There is a threshold loss at the output node Y3, which will cause a large delay and reduce the noise margin in low-voltage applications.

[0044] Figure 4 The structure diagram of a composite logic gate circuit 400 based on transistor-level design according to another embodiment of the present invention is schematically shown.

[0045] like Figure 4 As shown in , by adding a transmission gate composed of a PMOS tube P43 (corresponding to the third PMOS tube) and an NMOS tube N43 (corresponding to the third NMOS tube), when AB=0 at the output terminal Y42, the output is directly given through the transmission gate, Y4=C, which can avoid the problem of non-full swing.

[0046] In one embodiment, the gate of the PMOS transistor P43 is coupled to the output terminal Y42, the source is coupled to the output terminal Y4, the drain is coupled to the gates of the PMOS transistor P42 and the NMOS transistor N42, and is configured to receive the input signal C. The source of the NMOS transistor N43 is coupled to the gates of the PMOS transistor P42 and the NMOS transistor N42 and is configured to receive the input signal C, the drain is coupled to the output terminal Y4, and the gate is coupled to the output terminal Y41 to receive the first output signal of the first logic gate circuit 410.

[0047] As described above, the first logic gate circuit 410 may be a NAND gate circuit or a NOR gate circuit, and is generally composed of 4 transistors. Figure 4 The implementation uses 10 transistors, which is Figure 1 The 16 transistors of the original design shown in are reduced by 37.5%.

[0048] Therefore, in conventional designs, the AND-XOR gate circuit implemented by ordinary complementary static CMOS logic gate circuits uses a large number of transistors (e.g., 16), and has a large area and power consumption. In the present invention, in the design of the AND-XOR gate circuit or the OR-XOR gate circuit, the inverter in the AND gate circuit or the OR gate circuit can be used to implement the AND-XOR circuit or the OR-XOR gate circuit by adding only two transistors. In order to solve the problem of non-full swing of the node signal, a transmission gate circuit can be added, so that the AND-XOR circuit or the OR-XOR gate circuit is implemented by, for example, 10 transistors, thereby reducing the area and power consumption of the AND-XOR gate circuit or the NOR-XOR gate circuit.

[0049] In addition, the present invention is not limited thereto, and the above method can also be used in similar composite logic gate circuits, such as an AND-XNOR gate circuit or an OR-XNOR gate circuit.

[0050] Figure 5 The structure diagram of another complex logic gate circuit 500 based on transistor level design according to another embodiment of the present invention is schematically shown.

[0051] exist Figure 5 In, with Figure 3Compared with the embodiment of the present invention, an inverter circuit consisting of a PMOS tube P53 (corresponding to the fourth PMOS tube) and an NMOS tube N53 (corresponding to the fourth NMOS tube) is added.

[0052] The source of the PMOS transistor P53 is coupled to the power input terminal VDD, the drain is coupled to the output terminal Y5, and the gate is coupled to the drains of the PMOS transistor P52 and the NMOS transistor N52. The source of the NMOS transistor N53 is coupled to the ground terminal VSS, the drain is coupled to the output terminal Y5, and the gate is coupled to the drains of the PMOS transistor P52 and the NMOS transistor N52. In the case where the first logic gate circuit 510 is a NAND gate circuit, the first output signal at the output terminal Y51 is , the output signal at the output terminal Y52 is AB, and the output signal at the output terminal Y5 is =AB⊙C. Thus, Figure 5 The composite logic gate circuit 500 in the embodiment may be an AND-XNOR gate circuit. Similarly, when the first logic gate circuit 510 is a NOR gate circuit, the output signal at the output terminal Y5 may be =(A+B)⊙C, Figure 5 The composite logic gate circuit 500 in the embodiment may be an OR-XNOR (exclusive OR) gate circuit.

[0053] Fig. 6A and Figure 6B The structural diagrams of a CMOS NAND gate circuit 600 - 1 and a CMOS NOR gate circuit 600 - 2 included in a composite logic gate circuit based on transistor-level design according to an embodiment of the present invention are schematically shown respectively.

[0054] In one embodiment, Figure 3-Figure 5 The first logic gate circuits 310-510 shown in FIG. 1 may be Fig. 6A The NAND gate circuit shown in . Fig. 6AAs shown in , the NAND gate circuit 600-1 includes a PMOS transistor P61 (corresponding to the fifth PMOS transistor), a PMOS transistor P62 (corresponding to the sixth PMOS transistor), an NMOS transistor N61 (corresponding to the fifth NMOS transistor) and an NMOS transistor N62 (corresponding to the sixth NMOS transistor). The sources of the PMOS transistors P61 and P62 are both coupled to the power input terminal VDD and the drains are both coupled to the output terminal N1. The gate of the PMOS transistor P61 is configured to receive the first input signal A and the gate of the PMOS transistor P62 is configured to receive the second input signal B. The source of the NMOS transistor N61 is coupled to the drain of the NMOS transistor N62, the drain is coupled to the output terminal N1, and the gate is configured to receive the first input signal A. The drain of the NMOS transistor N62 is coupled to the source of the NMOS transistor N61, the source is coupled to the ground terminal, and the gate is configured to receive the second input signal B. The NAND gate circuit 600-1 outputs the first output signal at the output terminal N1. .also, Fig. 6A The output terminal N1 in can correspond to Figure 3-Figure 5 The output terminals Y31-Y51 in.

[0055] like Figure 6B As shown in , the NOR gate circuit 600-2 includes a PMOS transistor P63 (corresponding to the seventh PMOS transistor), a PMOS transistor P64 (corresponding to the eighth PMOS transistor), an NMOS transistor N63 (corresponding to the seventh NMOS transistor), and an NMOS transistor N64 (corresponding to the eighth MOS transistor). The source of the PMOS transistor P63 is coupled to the power input terminal VDD, the drain is coupled to the source of the PMOS transistor P64, and the gate is configured to receive the first input signal A. The source of the PMOS transistor P64 is coupled to the drain of the PMOS transistor P63, the drain is coupled to the output terminal N2, and the gate is configured to receive the second input signal B. The sources of the NMOS transistors N63 and NMOS transistors N64 are both coupled to the ground terminal VSS and the drains are both coupled to the output terminal N2, the gate of the NMOS transistor N63 is configured to receive the first input signal A and the gate of the NMOS transistor N64 is configured to receive the second input signal B. The NOR gate circuit 600-2 can output the first output signal at the output terminal N2 .also, Figure 6B The output terminal N2 in can correspond to Figure 3-Figure 5 The output terminals Y31-Y51 in.

[0056] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0057] The advantage of the present invention is that the number of transistors in the circuit is reduced without affecting the circuit performance, thereby effectively reducing the power consumption of the circuit. The circuit of the present invention is not only used for circuits with XOR logic functions, but can also be used for circuits with XNOR logic functions.

[0058] In one embodiment, a composite logic gate circuit is provided, the composite logic gate circuit comprising: a simple logic gate circuit, a first PMOS tube and a first NMOS tube; wherein the simple logic gate circuit comprises a first logic gate circuit and an inverter circuit, wherein the first logic gate circuit is configured to receive a first input signal and a second input signal, and output a first output signal, wherein the inverter circuit comprises a second PMOS tube and a second NMOS tube, the source of the second PMOS tube is coupled to a power input terminal, the drain is coupled to a drain of the second NMOS tube, the gate is configured to receive the first output signal, and the source of the second NMOS tube is coupled to a ground terminal. The first PMOS tube has a first terminal, a drain coupled to the drain of the second PMOS tube, and a gate configured to receive the first output signal, wherein the source of the first PMOS tube is coupled to the drains of the second PMOS tube and the second NMOS tube, the drain is coupled to the drain of the first NMOS tube, and the gate is configured to receive a third input signal, wherein the source of the first NMOS tube is configured to receive the first output signal, the drain is coupled to the drain of the first PMOS tube, and the gate is configured to receive the third input signal, and wherein the simple logic gate circuit is an AND gate circuit or an OR gate circuit, and the first logic gate circuit is a NAND gate circuit or a NOR gate circuit accordingly.

[0059] In one embodiment, the composite logic gate circuit further includes a transmission gate circuit, which includes a third PMOS tube and a third NMOS tube, wherein the gate of the third PMOS tube is coupled to the drain of the second PMOS tube and the source of the first PMOS tube, the source is coupled to the drain of the first PMOS tube and the first NMOS tube, and the drain is coupled to the gate of the first PMOS tube and the first NMOS tube, the gate of the third NMOS tube is coupled to the source of the first NMOS tube and is configured to receive the first output signal, the source is coupled to the gate of the first PMOS tube and the first NMOS tube, and the drain is coupled to the drain of the first PMOS tube and the first NMOS tube.

[0060] In one embodiment, the composite logic gate circuit also includes a second inverter circuit, which includes a fourth PMOS tube and a fourth NMOS tube, wherein the source of the fourth PMOS tube is coupled to the power input terminal, the drain is coupled to the drain of the fourth NMOS tube, and the gate is coupled to the drains of the first PMOS tube and the first NMOS tube, and the source of the fourth NMOS tube is coupled to the ground terminal, the drain is coupled to the drain of the fourth PMOS tube, and the gate is coupled to the drains of the first PMOS tube and the first NMOS tube.

[0061] In one embodiment, the first logic gate circuit is a NAND gate circuit, and the NAND gate circuit includes: a fifth PMOS tube, a fifth NMOS tube, a sixth PMOS tube and a sixth NMOS tube, wherein the source of the fifth PMOS tube is coupled to the power input terminal, the drain is coupled to the drain of the sixth PMOS tube and the fifth NMOS tube, and the gate is configured to receive the first input signal, wherein the source of the sixth PMOS tube is coupled to the power input terminal, the drain is coupled to the drain of the fifth PMOS tube and the fifth NMOS tube, and the gate is configured to receive the second input signal, wherein the source of the fifth NMOS tube is coupled to the drain of the sixth NMOS tube, the drain is coupled to the drain of the fifth PMOS tube and the sixth PMOS tube, and the gate is configured to receive the first input signal, the source of the sixth NMOS tube is coupled to the ground terminal, the drain is coupled to the source of the fifth NMOS tube, and the gate is configured to receive the second input signal, wherein the node where the drains of the fifth PMOS tube, the sixth PMOS tube and the fifth NMOS tube are coupled to each other is configured to output the first output signal.

[0062] In one embodiment, the first logic gate circuit is an NOR gate circuit, and the NOR gate circuit includes: a seventh PMOS tube, a seventh NMOS tube, an eighth PMOS tube and an eighth NMOS tube, wherein the source of the seventh PMOS tube is coupled to the power input terminal, the drain is coupled to the source of the eighth PMOS tube, and the gate is configured to receive the first input signal, wherein the source of the eighth PMOS tube is coupled to the drain of the seventh PMOS tube, the drain is coupled to the drains of the seventh NMOS tube and the eighth NMOS tube, and the gate is configured to receive the second An input signal, wherein the source of the seventh NMOS tube is coupled to the ground terminal, the drain is coupled to the drain of the eighth PMOS tube and the eighth NMOS tube, and the gate is configured to receive the first input signal, wherein the source of the eighth NMOS tube is coupled to the ground terminal, the drain is coupled to the drain of the seventh NMOS tube and the eighth PMOS tube, and the gate is configured to receive the second input signal, wherein the node at which the drains of the eighth PMOS tube, the seventh NMOS tube and the eighth NMOS tube are coupled to each other is configured to output the first output signal.

[0063] In one embodiment, a computing device is provided, the computing device comprising the composite logic gate circuit as described above. The computing device is, for example, a data processing device.

[0064] The words "front", "rear", "top", "bottom", "above", "below", etc., if present, in the specification and claims are used for descriptive purposes and are not necessarily used to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances, such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0065] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not limited by any expressed or implied theory given in the above technical field, background technology, summary of the invention, or detailed description.

[0066] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0067] The above description may indicate an element or node or feature that is "coupled" or "coupled" together. As used herein, unless otherwise expressly stated, "coupling" means that one element / node / feature is directly coupled (or directly communicates) to another element / node / feature electrically, mechanically, logically or otherwise. Similarly, unless otherwise expressly stated, "coupling" means that one element / node / feature can be mechanically, electrically, logically or otherwise connected to another element / node / feature in a direct or indirect manner to allow interaction, even if the two features may not be directly coupled. In other words, "coupling" is intended to include direct and indirect connections of elements or other features, including couplings using one or more intermediate elements.

[0068] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0069] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0070] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A composite logic gate circuit, characterized in that: The composite logic gate circuit comprises: A simple logic gate circuit, a first PMOS tube and a first NMOS tube; Wherein, the simple logic gate circuit includes a first logic gate circuit and an inverter circuit. The first logic gate circuit is configured to receive a first input signal and a second input signal, and output a first output signal. The inverter circuit includes a second PMOS tube and a second NMOS tube, the source of the second PMOS tube is coupled to the power input terminal, the drain is coupled to the drain of the second NMOS tube, and the gate is configured to receive the first output signal, the source of the second NMOS tube is coupled to the ground terminal, the drain is coupled to the drain of the second PMOS tube, and the gate is configured to receive the first output signal, The source of the first PMOS tube is coupled to the drains of the second PMOS tube and the second NMOS tube, the drain is coupled to the drain of the first NMOS tube, and the gate is configured to receive a third input signal. The source of the first NMOS transistor is configured to receive the first output signal, the drain is coupled to the drain of the first PMOS transistor, and the gate is configured to receive the third input signal, and The simple logic gate circuit is an AND gate circuit or an OR gate circuit, and the first logic gate circuit is a NAND gate circuit or a NOR gate circuit accordingly.

2. The composite logic gate circuit according to claim 1, characterized in that: It also includes a transmission gate circuit, which includes a third PMOS transistor and a third NMOS transistor, wherein The gate of the third PMOS tube is coupled to the drain of the second PMOS tube and the source of the first PMOS tube, the source is coupled to the drain of the first PMOS tube and the first NMOS tube, and the drain is coupled to the gate of the first PMOS tube and the first NMOS tube, The gate of the third NMOS tube is coupled to the source of the first NMOS tube and is configured to receive the first output signal, the source is coupled to the gates of the first PMOS tube and the first NMOS tube, and the drain is coupled to the drains of the first PMOS tube and the first NMOS tube.

3. The complex logic gate circuit according to claim 1, characterized in that: The second inverter circuit includes a fourth PMOS transistor and a fourth NMOS transistor. The source of the fourth PMOS tube is coupled to the power input terminal, the drain is coupled to the drain of the fourth NMOS tube, and the gate is coupled to the drains of the first PMOS tube and the first NMOS tube. The source of the fourth NMOS tube is coupled to the ground terminal, the drain is coupled to the drain of the fourth PMOS tube, and the gate is coupled to the drains of the first PMOS tube and the first NMOS tube.

4. The complex logic gate circuit according to claim 1, characterized in that: The first logic gate circuit is a NAND gate circuit, and the NAND gate circuit includes: a fifth PMOS tube, a fifth NMOS tube, a sixth PMOS tube and a sixth NMOS tube, The source of the fifth PMOS tube is coupled to the power input terminal, the drain is coupled to the drains of the sixth PMOS tube and the fifth NMOS tube, and the gate is configured to receive the first input signal. The source of the sixth PMOS tube is coupled to the power input terminal, the drain is coupled to the drains of the fifth PMOS tube and the fifth NMOS tube, and the gate is configured to receive the second input signal. The source of the fifth NMOS tube is coupled to the drain of the sixth NMOS tube, the drain is coupled to the drains of the fifth PMOS tube and the sixth PMOS tube, and the gate is configured to receive the first input signal. The source of the sixth NMOS tube is coupled to the ground terminal, the drain is coupled to the source of the fifth NMOS tube, and the gate is configured to receive the second input signal. The node where the drains of the fifth PMOS transistor, the sixth PMOS transistor and the fifth NMOS transistor are coupled to each other is configured to output the first output signal.

5. The complex logic gate circuit according to claim 1, characterized in that: The first logic gate circuit is a NOR gate circuit, and the NOR gate circuit includes: a seventh PMOS tube, a seventh NMOS tube, an eighth PMOS tube and an eighth NMOS tube, The source of the seventh PMOS tube is coupled to the power input terminal, the drain is coupled to the source of the eighth PMOS tube, and the gate is configured to receive the first input signal. The source of the eighth PMOS tube is coupled to the drain of the seventh PMOS tube, the drain is coupled to the drains of the seventh NMOS tube and the eighth NMOS tube, and the gate is configured to receive the second input signal. The source of the seventh NMOS tube is coupled to the ground terminal, the drain is coupled to the drain of the eighth PMOS tube and the eighth NMOS tube, and the gate is configured to receive the first input signal. The source of the eighth NMOS tube is coupled to the ground terminal, the drain is coupled to the drains of the seventh NMOS tube and the eighth PMOS tube, and the gate is configured to receive the second input signal. The node where the drains of the eighth PMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor are coupled to each other is configured to output the first output signal.

6. A computing device, characterized in that The computing device comprises the complex logic gate circuit according to any one of claims 1-5.

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