Method for detecting field programmable gate array pin failure
By generating variable signals in the FPGA and detecting the signal matching degree of the input channel, the problem of inaccurate FPGA pin fault detection is solved, and fast and accurate fault location is achieved.
Patent Information
- Application Number
- CN202210349406.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-01
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2042-04-01
AI Technical Summary
Existing technologies cannot accurately determine the location of FPGA pin faults, leading to inaccurate detection.
By controlling the signal generation circuit in the FPGA to generate a variable signal and acquiring the first signal through the input channel of the pin, the fault of the pin can be determined based on the signal matching degree.
It improves the accuracy and reliability of FPGA pin fault detection and simplifies the fault location process.
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Figure CN114814558B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of circuit, and in particular, to a method for detecting a field programmable gate array (FPGA) pin fault. BACKGROUND
[0002] FPGA (field programmable gate array) is a semi-custom circuit in the field of ASIC (application specific integrated circuit), which solves the shortcomings of custom circuits and overcomes the limitation of the number of gate circuits in the original programmable device.
[0003] In the related art, when detecting the FPGA, two FPGAs are usually required to send and receive data to each other to determine whether a fault occurs, but it cannot be determined whether the fault occurs at the FPGA pin or the circuit board. Therefore, how to improve the accuracy of detecting the FPGA pin fault is crucial. SUMMARY
[0004] The present disclosure aims to at least solve one of the technical problems in the related art to some extent.
[0005] In one aspect, an embodiment of the present disclosure provides a method for detecting a field programmable gate array (FPGA) pin fault, comprising:
[0006] controlling a signal generating circuit in the FPGA to generate a variable signal, wherein the signal generating circuit is connected to an output channel of a pin in the FPGA;
[0007] obtaining a first signal through an input channel of the pin;
[0008] determining whether the pin is faulty according to a matching degree between the first signal and the variable signal.
[0009] Optionally, the signal generating circuit is connected to the output channel of each pin in the FPGA, and the obtaining of the first signal through the input channel of the pin comprises:
[0010] determining a detection signal corresponding to each group of pins according to a first signal through an input channel of each pin in each group of pins, wherein each group of pins comprises a plurality of pins;
[0011] The determining of whether the pin is faulty according to the matching degree between the first signal and the variable signal comprises:
[0012] determining whether a faulty pin is included in each group of pins according to a matching degree between the detection signal and the variable signal.
[0013] Optionally, the determining whether a faulty pin is included in each group of the pins according to the matching degree between the detection signal and the variable signal comprises:
[0014] In a case where any detection signal does not match the variable signal, a plurality of first signals corresponding to the any detection signal are acquired;
[0015] The matching degree between each first signal and the variable signal is determined;
[0016] The pin corresponding to the first signal that does not match the variable signal is determined as a faulty pin.
[0017] Optionally, the determining the detection signal corresponding to each group of the pins according to the first signal respectively passing through each pin input channel in each group of the pins comprises:
[0018] performing logical AND operation on the first signals respectively passing through each pin input channel in each group of the pins to generate the detection signal corresponding to each group of the pins; or
[0019] performing logical OR operation on the first signals respectively passing through each pin input channel in each group of the pins to generate the detection signal corresponding to each group of the pins.
[0020] Optionally, the signal generation circuit is connected with the output channel of each pin in the FPGA, and the determining whether the pin is faulty according to the matching degree between the first signal and the variable signal comprises:
[0021] determining whether each pin is faulty according to the matching degree between the first signal passing through the input channel of each pin and the variable signal.
[0022] The method for detecting the pin fault of the field programmable gate array provided by the present disclosure can first control the signal generation circuit in the FPGA to generate a variable signal, wherein the signal generation circuit is connected with the output channel of the pin in the FPGA, and then the first signal passing through the input channel of the pin can be acquired, and whether the pin is faulty can be determined according to the matching degree between the first signal and the variable signal. Thus, by detecting the signal of the output channel and the signal of the input channel of the same pin in the FPGA, whether the pin is faulty can be determined according to the matching degree between the two, and the process is relatively simple and fast, and the faulty pin can be accurately determined when the pin is faulty, thereby improving the accuracy and reliability of the FPGA pin detection.
[0023] Additional aspects and advantages of the present disclosure will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS
[0024] The above and / or additional aspects and advantages of the present disclosure will become apparent and more readily appreciated from the following description, taken in conjunction with the following drawings, in which:
[0025] Figure 1 A flowchart of a method for detecting a failure of a field programmable gate array (FPGA) pin according to an embodiment of the present disclosure;
[0026] Figure 1A A schematic diagram of a signal of a field programmable gate array (FPGA) pin according to an embodiment of the present disclosure;
[0027] Figure 2 A flowchart of a method for detecting a failure of a field programmable gate array (FPGA) pin according to another embodiment of the present disclosure. DETAILED DESCRIPTION
[0028] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, in which like or similar elements are denoted by the same or similar reference signs, and the embodiments described below are examples for explaining the present disclosure and are not intended to limit the present disclosure.
[0029] A method for detecting a failure of a field programmable gate array (FPGA) pin according to an embodiment of the present disclosure is described below with reference to the accompanying drawings.
[0030] Figure 1 A flowchart of a method for detecting a failure of a field programmable gate array (FPGA) pin according to an embodiment of the present disclosure.
[0031] As shown in Figure 1 the method for detecting a failure of a field programmable gate array (FPGA) pin can include the following steps:
[0032] In step 101, a signal generation circuit in a field programmable gate array (FPGA) is controlled to generate a variable signal, wherein the signal generation circuit is connected to an output channel of a pin in the FPGA.
[0033] The variable signal can be of various types, such as a square wave signal, a pulse signal, etc., and the present disclosure does not limit the variable signal.
[0034] In addition, the pin in the FPGA can be any I / O pin, which has both an input channel and an output channel, etc., and the present disclosure does not limit the pin.
[0035] Generally, a field-programmable gate array (FPGA) can include a signal generation circuit which can generate a signal. Thus, in the embodiments of the present disclosure, the signal generation circuit in the FPGA can be controlled to generate a variable signal and transmit it to the output channel of the pin of the FPGA, such as to control the signal generation circuit in the FPGA to generate a square wave signal, and the like. The present disclosure does not limit this.
[0036] In step 102, a first signal passing through the input channel of the pin is obtained.
[0037] It can be understood that the signal generation circuit is connected to the output channel of the pin in the FPGA, and then the variable signal generated by the signal generation circuit can be transmitted to the output channel of the pin in the FPGA. Since the pin in the FPGA is generally bidirectional, the signal passing through the output channel of the pin can return to the input channel of the pin after a certain delay, and then the signal returning to the input channel of the pin is the first signal.
[0038] In step 103, whether the pin is faulty is determined according to the matching degree between the first signal and the variable signal.
[0039] It can be understood that generally, if the FPGA pin is a normal pin, then the first signal passing through the input channel of the pin is consistent with the variable signal passing through the output channel of the pin, and the two are matched. If the FPGA pin is faulty, then the first signal passing through the input channel of the pin can change so as to be inconsistent with the variable signal passing through the output channel of the pin, and the two are not matched. Thus, whether the pin is faulty can be determined according to the matching degree between the first signal and the variable signal passing through the pin, so that when the pin is faulty, the pin fault can be accurately determined, and the accuracy and reliability of the pin fault detection are improved.
[0040] For example, if the first signal of the input channel of the FPGA pin is a "constant signal" which is not matched with the variable signal of the output channel of the FPGA pin, it can be determined that the pin is faulty. If the first signal of the FPGA pin is consistent with the variable signal, that is, the two are matched, it can be determined that the pin is normal, and the present disclosure does not limit this.
[0041] Optionally, the signal generation circuit can also be connected to the output channel of each pin in the FPGA, so that whether each pin is faulty can also be determined according to the matching degree between the first signal and the variable signal of the input channel of each pin.
[0042] For example, in the case of the variable signal being a square wave signal, it presents a form of "0" and "1" alternately. If the first signal through the input channel of the FPGA pin 1 is a "0" and "1" signal, it is consistent with the square wave signal, and it can be determined that the FPGA pin 1 is normal and has not failed. If the first signal through the input channel of the FPGA pin 2 is a "1" signal, it does not match the square wave signal, and it can be determined that the FPGA pin 2 has failed.
[0043] It should be noted that the above examples are only illustrative and cannot be used as a limitation on the manner of determining the pin failure in the embodiments of the present disclosure.
[0044] Optionally, the signal detection circuit can also be used to detect the first signal of each pin input channel to determine the matching degree between the first signal of each pin and the variable signal, and further determine whether each pin has failed.
[0045] For example, the signals corresponding to the pins in the FPGA can be as shown in Figure 1A As can be seen from Figure 1A It can be seen that the FPGA includes n I / O pins, and the signal generation circuit in the FPGA is connected to the output channel of each I / O pin to transmit the variable signal generated by the signal generation circuit to the output channel of each I / O pin. In addition, the input channel of each I / O pin is connected to the signal detection circuit to detect the first signal of each pin by using the signal detection circuit to determine whether the first signal corresponding to each pin matches the variable signal. If the first signal of any I / O pin does not match the variable signal, it can be determined that the any I / O pin has failed, and the present disclosure does not limit this.
[0046] Therefore, in the embodiments of the present disclosure, the variable signal generated in the FPGA can be output to each pin, and the first signal can be obtained by using the input channel of the pin. Then, the variable signal and the first signal can be matched to determine whether the FPGA pin has failed, thereby improving the accuracy and efficiency of determining the failed pin.
[0047] In the embodiments of the present disclosure, the signal generation circuit in the FPGA can be controlled to generate a variable signal first, wherein the signal generation circuit is connected to the output channel of the pin in the FPGA. Then, the first signal through the input channel of the pin can be obtained, and the matching degree between the first signal and the variable signal can be determined to determine whether the pin has failed. Thus, by detecting the signals of the output channel and the input channel of the same pin in the FPGA, whether the pin has failed can be determined according to the matching degree between the two signals. This process is relatively simple and fast, and the failed pin can be accurately determined when the pin fails, thereby improving the accuracy and reliability of the FPGA pin detection.
[0048] Figure 2 A flowchart of a method for detecting a failure of a field programmable gate array (FPGA) pin is shown in FIG. 1. The method can include the following steps: Figure 2
[0049] In step 201, a signal generation circuit in the FPGA is controlled to generate a variable signal, wherein the signal generation circuit is connected to an output channel of each pin in the FPGA.
[0050] In step 202, a detection signal corresponding to each group of pins is determined according to a first signal input through each pin input channel in each group of pins, wherein each group of pins includes a plurality of pins.
[0051] The pins in the FPGA can be grouped in advance, for example, according to the BANK of the FPGA, or in other ways, which are not limited in the present disclosure.
[0052] In addition, the first signals input through each pin input channel in each group of pins can be fused or superimposed to generate the detection signal corresponding to the group of pins.
[0053] Optionally, the first signals input through each pin input channel in each group of pins can be logically ANDed to generate the detection signal corresponding to the group of pins.
[0054] For example, in the case where group 1 includes three pins, if the first signal of pin 1 alternates between "0" and "1", the first signal of pin 2 is "0", and the first signal of pin 3 is "0" and "1", the three first signals are logically ANDed to generate a detection signal of "0". Alternatively, if the first signals of the three pins in group 1 are all "0" and "1", the logically ANDed detection signal is "0" and "1", and the like. The present disclosure is not limited in this regard.
[0055] Optionally, the first signals input through each pin input channel in each group of pins can be logically ORed to generate the detection signal corresponding to the group of pins.
[0056] For example, in the case where group 1 includes three pins, if the first signals of pin 1 and pin 2 both alternate between "0" and "1", and the first signal of pin 3 is "1", the three first signals are logically ORed to generate a detection signal of "1". Alternatively, if the first signals of the three pins in group 1 are all "0" and "1", the logically ORed detection signal is "0" and "1", and the like. The present disclosure is not limited in this regard.
[0057] Step 203, according to the matching degree between the detection signal and the variable signal, determine whether the fault pin is contained in each group of pins.
[0058] It can be understood that the higher the matching degree between the detection signal and the variable signal, the more likely that the group of pins does not contain a fault pin; the lower the matching degree between the detection signal and the variable signal, the more likely that the group of pins contains a fault pin.
[0059] For example, if the variable signal is a square wave signal, which can be represented as an alternating signal of "0" and "1"; if the detection signal is "1", it does not match the square wave signal, and it can be determined that the group of pins contains a fault pin. Alternatively, if the detection signal is "0", it does not match the matching degree of the square wave signal, and it can be determined that the group of pins contains a fault pin. If the detection signal is "0" and "1", it matches the square wave signal, and it can be determined that the group of pins does not contain a fault pin. The present disclosure does not limit this.
[0060] Therefore, in the embodiment of the present disclosure, the FPGA pins can be grouped first, and then the first signal of each pin input channel can be logically processed to determine the detection signal corresponding to the group of pins, that is, the detection signal sufficiently integrates the first signal of each pin, which is more complete and comprehensive. Then match the detection signal with the variable signal to determine whether the group of pins contains a fault pin. This process is relatively simple and efficient, and improves the accuracy and efficiency of determining the existence of a fault pin.
[0061] Optionally, in the case where any detection signal does not match the variable signal, the plurality of first signals corresponding to any detection signal can be obtained, and then the matching degree of each first signal with the variable signal can be determined, and the pin corresponding to the first signal that does not match the variable signal is determined as a fault pin.
[0062] It can be understood that if any detection signal matches the variable signal, it can be indicated that the group of pins corresponding to the any detection signal does not contain a fault pin, and all are normal pins.
[0063] If any detection signal does not match the variable signal, it can be indicated that the group of pins contains a fault pin. Then the first signal of each pin in the group of pins can be matched with the variable signal respectively. If the first signal of any pin in the group of pins matches the variable signal, it is considered that the two match, and the any pin is a normal pin. If the first signal of any pin in the group of pins does not match the variable signal, it is considered that the two do not match, and the any pin is a fault pin.
[0064] For example, in the case that any detection signal does not match the variable signal, if the variable signal is an alternating signal of "0" and "1", the any detection signal is a "0" signal, and there are five pins in the group corresponding to the any detection signal, pins 1, 2 and 3 are consistent with the variable signal, pin 4 is a "0" signal, and pin 5 is a "1" signal, both of which are inconsistent with the variable signal, that is, pins 4 and 5 do not match the variable signal, then pins 4 and 5 can be determined as faulty pins.
[0065] It should be noted that the above examples are only illustrative and cannot be regarded as a limitation on the grouping of pins, detection signals, first signals of each pin, and the like in the embodiments of the present disclosure.
[0066] In the embodiments of the present disclosure, a signal generation circuit in a field programmable gate array (FPGA) can be controlled to generate a variable signal, wherein the signal generation circuit is connected to the output channels of each pin in the FPGA. Then, a detection signal corresponding to each group of pins can be determined according to the first signals input through each pin in each group of pins, wherein each group of pins includes a plurality of pins. Finally, whether a faulty pin is included in each group of pins can be determined according to the matching degree between the detection signal and the variable signal. In this way, the pins in the FPGA can be grouped first, and then the detection signal corresponding to each group is matched with the variable signal to determine whether a faulty pin is included in each group. Therefore, the group position of the faulty pin can be quickly located, and the accuracy and efficiency of determining the faulty pin are improved.
Claims
1. A method for detecting pin faults in a field-programmable gate array (FPGA), characterized in that, include: The signal generation circuit in the field-programmable gate array (FPGA) is controlled to generate a variable signal, wherein the signal generation circuit is connected to the output channel of a pin in the FPGA; Acquire the first signal through the input channel of the pin; Based on the matching degree between the first signal and the variable signal, determine whether the pin is faulty; The signal generation circuit is connected to the output channels of each pin in the FPGA, and acquiring the first signal through the input channel of the pin includes: Based on the first signal input through each pin in each group of pins, the detection signal corresponding to each group of pins is determined, wherein each group of pins includes multiple pins; Determining whether the pin is faulty based on the matching degree between the first signal and the variable signal includes: Based on the matching degree between the detection signal and the variable signal, determine whether each group of pins contains a faulty pin; The step of determining the detection signal corresponding to each group of pins based on the first signal input to each pin channel in each group of pins includes: The first signal of each input channel in each group of pins is logically ANDed to generate the detection signal corresponding to each group of pins; or, The first signal of each input channel in each group of pins is logically ORed to generate the detection signal corresponding to each group of pins.
2. The method as described in claim 1, characterized in that, The step of determining whether each group of pins contains a faulty pin based on the matching degree between the detected signal and the variable signal includes: If any detection signal does not match the variable signal, a plurality of first signals corresponding to the detection signal are acquired; Determine the matching degree between each of the first signals and the variable signals; The pin corresponding to the first signal that does not match the variable signal is identified as the faulty pin.
3. The method as described in claim 1, characterized in that, The signal generation circuit is connected to the output channels of each pin in the FPGA. Determining whether a pin is faulty based on the matching degree between the first signal and the variable signal includes: Whether each pin is faulty is determined based on the matching degree between the first signal of the input channel through each pin and the variable signal.
Citation Information
Patent Citations
Programmable logic device pin state detection method, device and system
CN112463502A