Signal processing system, signal processing method and electronic device

Abstract

The present application proposes a signal processing system, a signal processing method and an electronic device, which can improve the identification accuracy of nonlinear systems. Among them, a signal processing system includes: a fractional delay generation unit, which is used to perform delay processing on the input signal of the signal processing system to generate a fractional delay signal; an integer delay unit, which is used to perform delay processing on the fractional delay signal to generate a signal processed with integer delay; and a model processing unit, which is used to process the signal processed with integer delay according to the mathematical model of the signal processing system to obtain the output signal of the signal processing system.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a signal processing system, a signal processing method and an electronic device. Background Art

[0002] In application scenarios such as automation control, base station communication, and audio signal processing, nonlinear system identification can be achieved by using discrete signal sampling. As the system bandwidth increases and the requirements for identification accuracy increase, nonlinear system identification solutions usually increase the sampling frequency to obtain better time resolution, thereby improving identification accuracy.

[0003] However, increasing the sampling frequency will increase the amount of calculation and thus increase hardware power consumption.

[0004] In view of this, how to improve recognition accuracy without increasing hardware power consumption is a technical problem that needs to be solved. Summary of the invention

[0005] The present application proposes a signal processing system, a signal processing method and an electronic device, which can improve the recognition accuracy of a nonlinear system.

[0006] According to one aspect of the present application, a signal processing system is provided, comprising:

[0007] A fractional delay generating unit, used for performing delay processing on an input signal of the signal processing system to generate a fractional delay signal;

[0008] An integer delay unit, used for performing delay processing on the fractional delay signal to generate a signal processed with integer delay;

[0009] The model processing unit is used to process the signal after integer delay processing according to the mathematical model of the signal processing system to obtain the output signal of the signal processing system.

[0010] In some embodiments, the mathematical model of the signal processing system is a generalized memory polynomial;

[0011] A fractional delay generating unit, configured to generate a first fractional delay signal and a second fractional delay signal;

[0012] The integer delay unit includes a first integer delay module and a second integer delay module, wherein the first integer delay module is used to perform delay processing on the first fractional delay signal to output a first integer delay signal, and the second integer delay module is used to perform delay processing on the second fractional delay signal to output a second integer delay signal;

[0013] The model processing unit is used to process the first integer time-delay signal and the second integer time-delay signal according to the generalized memory polynomial to obtain an output signal of the signal processing system.

[0014] In some embodiments, the mathematical model of the signal processing system is a generalized memory polynomial of fractional delay: y(n)=∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|), where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the nonlinear function basis, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, and y(n) represents the output signal;

[0015] The fractional delay generation unit is used to generate τ i The corresponding first fractional delay signal x(n-τ i ) and δ j The corresponding second fractional delay signal x(n-δ j );

[0016] The first integer delay module is used to delay the first fractional delay signal x(n-τ i ) is delayed to output a second integer delay signal x(ni-τ i ), the second integer delay module is used to delay the second fractional delay signal x(n-δ j ) is delayed to output a second integer time-delay signal x(nj-δ j );

[0017] The model processing unit includes a nonlinear function lookup table, a multiplier, and an accumulator.

[0018] Among them, the nonlinear function lookup table is used to calculate the ijp 、x(nj-δ j ) Generate α ijp φ p (|x(nj-δ j )|);

[0019] Multiplier, used to generate x(ni-τ i ) and α ijp φ p (|x(nj-δ j )|);

[0020] Accumulator, used to calculate the value of x(ni-τ i ) and α ijp φ p (|x(nj-δ j )|) to generate the output signal y(n) of the signal processing system.

[0021] In some embodiments, the signal processing system further comprises: a processor for determining α in the generalized memory polynomial of the fractional delay. ijp , τ i , δ j .

[0022] In some embodiments, the signal processing system further comprises: a signal distribution unit for distributing the first fractional delay signal x(n-τ) generated by the fractional delay generation unit to the i ) is input into the first integer delay module, and the second fractional delay signal x(n-δ j ) Input the second integer delay module.

[0023] In some embodiments, τ i , δ j The value ranges are all predetermined discrete sets, and the processor determines the generalized memory polynomial of the fractional delay according to the following method: ijp , τ i , δ j :

[0024] Initialize the matrix A to an empty matrix, initialize the set (τ, δ) to an empty set, and initialize the parameter y res is y, where y represents the target signal;

[0025] For each set of values ​​of (i, j), determine the value that makes |A(i, j, τ i , δ j ) H y res |The largest value Where A(i, j, τ i , δ j ) is the nonlinear basis of the generalized memory polynomial of fractional delay,

[0026] in, Among them, A(i, j, τ i , δ j ) H Denotes the matrix A(i, j, τ i , δ j ), It means (τ i , δ j ) a set of values;

[0027] according to Update the matrix A, represents the augmented matrix;

[0028] According to y res =yA*pinv(A)*yUpdatey res , where pinv(A) represents the pseudo-inverse matrix of matrix A;

[0029] Will Add to the set (τ, δ);

[0030] Multiply pinv(A) and y as α ijp .

[0031] In some embodiments, τ i , δ j The value range is a predetermined continuous interval, and the processor determines the generalized memory polynomial of the fractional delay according to the following method: ijp , τ i , δ j :

[0032] Initialize τ i =0,δ j is 0;

[0033] For each set of values ​​of (i, j), perform the following operations until Less than the preset threshold:

[0034] According to α ijp =pinv(A(x,τ,δ))y determine α ijp Value, where pinv(A(x, τ, δ)) represents the pseudo-inverse matrix of A(x, τ, δ),

[0035]

[0036] g k (.) represents the coefficient of the fractional delay filter;

[0037] according to Determine the disturbance Δ=(ε i , η j ), where the disturbance Δ is the i , δ j )

[0038] The value is The perturbation of (τi, δj) at time t, where

[0039] B=[C|D]

[0040]

[0041] express exist About δ j The derivative of

[0042] Determined according to the following formula:

[0043]

[0044] Update τ according to the following method i , δ j :

[0045] τ i =τ i +ε i

[0046] δ j =δ j +η j .

[0047] According to one aspect of the present application, a method for generating a nonlinear model is provided, wherein the nonlinear model is a generalized memory polynomial of fractional delay: y(n)=∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|), where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the basis of nonlinear function, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, y(n) represents the output signal, τ i , δ j The value ranges are all predetermined discrete sets; the generation method includes:

[0048] Initialize the matrix A to be an empty matrix, initialize the set (τ, δ) to be an empty set, and initialize the parameter y res is y, where y represents the target signal;

[0049] For each set of values ​​of (i, j), determine the value that makes |A(i, j, τ i , δ j ) H y res |The largest value Where A(i, j, τ i , δj ) is the nonlinear basis of the generalized memory polynomial of fractional delay,

[0050] in, Among them, A(i, j, τ i , δ j ) H Denotes the matrix A(i, j, τ i , δ j ), It means (τ i , δ j ) a set of values;

[0051] according to Update the matrix A, represents the augmented matrix;

[0052] According to y res =yA*pinv(A)*yUpdatey res , where pinv(A) represents the pseudo-inverse matrix of matrix A;

[0053] Will Add to the set (τ, δ);

[0054] Multiply pinv(A) and y as α ijp .

[0055] According to one aspect of the present application, a method for generating a nonlinear model is provided, wherein the nonlinear model is a generalized memory polynomial of fractional delay: y(n)=∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|), where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the basis of nonlinear function, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, y(n) represents the output signal, τ i , δ j The value range is a predetermined continuous interval; the generation method includes:

[0056] Initialize τ i =0,δ j is 0;

[0057] For each set of values ​​of (i, j), perform the following operations until Less than the preset threshold:

[0058] According to α ijp =pinv(A(x,τ,δ))y determine α ijp Value, where pinv(A(x, τ, δ)) represents the pseudo-inverse matrix of A(x, τ, δ),

[0059]

[0060] g k (.) represents the coefficient of the fractional delay filter;

[0061] according to Determine the disturbance Δ=(ε i , η j ), where the disturbance Δ is the i , δ j ) takes a value of Time pair (τ i , δ j ), where

[0062] B=[C|D]

[0063]

[0064]

[0065] express exist About δ j The derivative of

[0066] Determined according to the following formula:

[0067]

[0068] Update τ according to the following method i , δ j :

[0069] τ i =τ i +ε i

[0070] δ j =δ j +η j .

[0071] According to one aspect of the present application, a signal processing method is provided, comprising:

[0072] Performing time delay processing on the input signal of the signal processing system to generate a fractional time delay signal;

[0073] Delay processing is performed on the fractional delay signal to generate a signal processed with integer delay;

[0074] According to the mathematical model of the signal processing system, the signal after integer time delay processing is processed to obtain the output signal of the signal processing system.

[0075] According to one aspect of the present application, an electronic device is provided, including:

[0076] Memory;

[0077] A processor is used to execute the nonlinear model generation method or signal processing method of the embodiment of the present application.

[0078] According to one aspect of the present application, a storage medium is provided, storing a program, wherein the program includes instructions, and when the instructions are executed by an electronic device, the electronic device executes the nonlinear model generation method or signal processing method of an embodiment of the present application.

[0079] According to one aspect of the present application, a base station is provided, including:

[0080] A signal processing system according to the present application;

[0081] Power amplifier unit.

[0082] In summary, according to the signal processing system of the embodiment of the present application, it is possible to generate a fractional delay signal through a fractional delay generation unit without increasing the sampling rate, and generate an output signal based on the mathematical model of the signal processing system, which helps to improve the recognition accuracy and avoid the increase in power consumption caused by increasing the sampling rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1A and Figure 1B A schematic diagram showing application scenarios according to some embodiments of the present application is shown;

[0084] Figure 2 A schematic diagram of a signal processing system according to some embodiments of the present application is shown;

[0085] Figure 3A A schematic diagram of a signal processing system according to some embodiments of the present application is shown;

[0086] Figure 3B A schematic diagram of a signal processing system according to some embodiments of the present application is shown;

[0087] Figure 3C A schematic diagram of a signal processing system according to some embodiments of the present application is shown;

[0088] Figure 4A schematic diagram of a signal processing system according to some embodiments of the present application is shown;

[0089] Figure 5 A flow chart of a method 500 for generating a nonlinear model according to some embodiments of the present application is shown;

[0090] Figure 6 A flow chart of a method 600 for generating a nonlinear model according to some embodiments of the present application is shown;

[0091] Figure 7 shows a flow chart of a signal processing method 700 according to some embodiments of the present application;

[0092] Figure 8 A flow chart of a method 800 for generating an output signal according to some embodiments of the present application is shown;

[0093] Fig. 9 A schematic diagram of a base station according to some embodiments of the present application is shown;

[0094] Fig.10 A schematic diagram of an electronic device according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0095] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0096] Figure 1A and Figure 1B A schematic diagram showing application scenarios according to some embodiments of the present application is shown.

[0097] like Figure 1A and 1B As shown, the application scenario shows a nonlinear system 110 and a signal processing system 120. Here, the signal processing system 120 can be at the input end or output end of the nonlinear system 110. Here, the nonlinear system 110 can be, for example, a nonlinear device in scenarios such as automation control, digital audio processing, and base station communication. For example, the nonlinear system 110 is a power amplifier unit in a base station, but is not limited thereto.

[0098] like Figure 1A As shown, in a scenario where the signal processing system 120 is at the input end of the nonlinear system 110, the input signal can first be predistorted by the signal processing system 120 to obtain a predistorted signal. The predistorted signal enters the nonlinear system 110. The nonlinear system 110 can output a signal. The signal processing system 120 can compensate for the nonlinearity of the nonlinear system 110 so as to suppress the distortion of the nonlinear system 110.

[0099] like Figure 1BAs shown, in a scenario where the signal processing system 120 is at the output end of the nonlinear system 110, the signal processing system 120 can process the output signal of the nonlinear system 110, that is, use the output signal of the nonlinear system 110 as the input signal of the signal processing system 120, and perform post-processing on the output signal of the nonlinear system 110, so as to suppress the nonlinear distortion of the output signal of the nonlinear system 110. For example, the nonlinear system 110 is an audio signal processing system. The signal processing system 120 can process the output signal to cancel the echo in the audio signal.

[0100] Figure 2 A schematic diagram of a signal processing system according to some embodiments of the present application is shown. The signal processing system 120 may be implemented as an FPGA or ASIC hardware module.

[0101] like Figure 2 As shown, the signal processing system 120 may include a fractional delay generating unit 121 , an integer delay unit 122 and a model processing unit 123 .

[0102] The fractional delay generating unit 121 is used to perform delay processing on the input signal of the signal processing system to generate a fractional delay signal.

[0103] The integer delay unit 122 is used to perform delay processing on the fractional delay signal to generate a signal processed with integer delay.

[0104] The model processing unit 123 is used to process the signal after integer delay processing according to the mathematical model of the signal processing system to obtain the output signal of the signal processing system.

[0105] In summary, according to the signal processing system of the embodiment of the present application, it is possible to generate a fractional delay signal through a fractional delay generation unit without increasing the sampling rate, and generate an output signal based on the mathematical model of the signal processing system, which helps to improve the recognition accuracy and avoid the increase in power consumption caused by increasing the sampling rate.

[0106] Figure 3A A schematic diagram of a signal processing system according to some embodiments of the present application is shown.

[0107] Here, the mathematical model of the signal processing system is a generalized memory polynomial. The fractional delay generating unit 121 is used to generate a first fractional delay signal and a second fractional delay signal.

[0108] The integer delay unit 122 includes a first integer delay module 124 and a second integer delay module 125. The first integer delay module 124 is used to delay the first fractional delay signal to output a first integer delay signal, and the second integer delay module 125 is used to delay the second fractional delay signal to output a second integer delay signal.

[0109] The model processing unit 123 is used to process the first integer delay signal and the second integer delay signal according to the generalized memory polynomial to obtain the output signal of the signal processing system. In summary, according to the signal processing system of the embodiment of the present application, the first fractional delay signal and the second fractional delay signal can be generated by the fractional delay generation unit without increasing the sampling rate, and the output signal can be generated based on the mathematical model of the generalized memory polynomial of the signal processing system, which helps to improve the recognition accuracy and avoid the increase in power consumption caused by increasing the sampling rate. Figure 3B A schematic diagram of a signal processing system according to some embodiments of the present application is shown.

[0110] like Figure 3B As shown, the signal processing system 120 may include a fractional delay generating unit 121, an integer delay unit 122, and a model processing unit 123. The integer delay unit 122 may include a first integer delay module 124 and a second integer delay module 125. The model processing unit 123 includes: a nonlinear function lookup table 126, a multiplier 127, and an accumulator 128.

[0111] The mathematical model of the signal processing system 120 is a generalized memory polynomial (GMP) with fractional delay:

[0112] y(n)=∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|).

[0113] Where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the nonlinear function basis, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, and y(n) represents the output signal of the signal processing system.

[0114] The fractional delay generating unit 121 is used to generate τ iThe corresponding first fractional delay signal x(n-τ i ) and δ j The corresponding second fractional delay signal x(n-δ j ).

[0115] The first integer delay module 124 is used to delay the first fractional delay signal x(n-τ i ) is delayed to output a first integer delay signal x(ni-τ i The second integer delay module 125 is used to delay the second fractional delay signal x(n-δ j ) is delayed to output a second integer time-delay signal x(nj-δ j ).

[0116] The nonlinear function lookup table 126 is used to calculate the ijp 、x(nj-δ j ) Generate α ijp φ p (|x(nj-δ j )|).

[0117] Multiplier 127 is used to generate x(ni-τ i ) and α ijp φ p (|x(nj-δ j )|).

[0118] It should be noted that for each set of values ​​of (i, j), the signal processing system 120 is configured with a corresponding branch for outputting α ijp ,x(ni-τ i ) and φ p (|x(nj-δ j Each branch includes a first integer delay module 124, a second integer delay module 125, a nonlinear function lookup table 126, and a multiplier 127.

[0119] The accumulator 128 is used to calculate the value of x(ni-τ) according to the i ) and α ijp φ p (|x(nj-δ j )|) to generate the output signal y(n) of the signal processing system. Here, the accumulator 128 can store the α corresponding to each group of values ​​of (i, j) ijp ,x(ni-τ i ) and φ p (|x(nj-δ j )|) are accumulated to obtain the output signal y(n).

[0120] In summary, according to the signal processing system of the embodiment of the present application, it is possible to generate a fractional delay signal through a fractional delay generation unit without increasing the sampling rate, and generate an output signal based on a mathematical model of a generalized memory polynomial of the fractional delay, which helps to improve recognition accuracy and avoid increased power consumption caused by increasing the sampling rate.

[0121] Figure 3C FIG. 1 is a schematic diagram of a signal processing system 120 according to some embodiments of the present application.

[0122] like Figure 3C As shown, the signal processing system 120 may include a fractional delay generating unit 121, an integer delay unit 122, a model processing unit 123, and a signal distribution unit 129. The integer delay unit 122 may include a first integer delay module 124 and a second integer delay module 125. The model processing unit 123 includes: a nonlinear function lookup table 126, a multiplier 127, and an accumulator 128.

[0123] The signal distribution unit 129 is used to distribute the fractional delay signal x(n-τ) generated by the fractional delay generation unit 121 to i ) is input into the first integer delay module 124, and the fractional delay signal x(n-δ j ) Input the second integer delay module 125.

[0124] In some embodiments, the delay characteristics of the nonlinear system 110 are relatively stable, and the embodiments of the present application can generate parameters in the mathematical model of the signal processing system offline. For example, the embodiments of the present application can determine the parameter α in the generalized memory polynomial of the fractional delay in the electronic device. ijp , τ i , δ j Here, the electronic device may be, for example, a desktop computer, a laptop computer, or a cloud computer.

[0125] In some embodiments, during the operation of the nonlinear system 110, the parameters of the signal processing system 120 need to be adjusted. In order to determine the parameters of the signal processing system 120 during the operation of the nonlinear system 110, the embodiment of the present application can be Figure 4 The structure of the parameters is calculated.

[0126] Figure 4 FIG. 1 is a schematic diagram of a signal processing system 120 according to some embodiments of the present application.

[0127] like Figure 4As shown, the signal processing system 120 may include a fractional delay generating unit 121, an integer delay unit 122, a model processing unit 123, a signal distribution unit 129 and a processor 130. The integer delay unit 122 may include a first integer delay module 124 and a second integer delay module 125. The model processing unit 123 includes: a nonlinear function lookup table 126, a multiplier 127 and an accumulator 128.

[0128] The signal distribution unit 129 is used to distribute the fractional delay signal x(n-τ) generated by the fractional delay generation unit 121 to i ) is input into the first integer delay module 124, and the fractional delay signal x(n-δ j ) Input the second integer delay module 125.

[0129] The processor 130 is used to determine the generalized memory polynomial of the fractional delay α ijp , τ i , δ j .

[0130] For example, Figure 5 A flow chart of a method 500 for generating a nonlinear model according to some embodiments of the present application is shown. The method 500 may be executed in an electronic device or in the processor 130, for example.

[0131] The nonlinear model is a generalized memory polynomial with fractional delay: y(n) = ∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|). Where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the basis of nonlinear function, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, and y(n) represents the output signal. i , δ j The value range is a predetermined discrete set. Here, τ i , δ j The value range is, for example, {0, 1 / 4, 1 / 2, 3 / 4}.

[0132] like Figure 5 As shown, in step S501, the matrix A is initialized to an empty matrix, the set (τ, δ) is initialized to an empty set, and the parameter y is initialized to res is y, where y represents the target signal. The target signal is, for example, a sampled signal.

[0133] For each set of values ​​of (i, j), method 500 may execute steps S502 - S505 .

[0134] In step S502, determine whether |A(i, j, τ i , δ j ) H y res |The largest value Where A(i, j, τ i , δ j ) is the nonlinear basis of the generalized memory polynomial of fractional delay,

[0135] in, A(i,j,τ i , δ j ) in the matrix x(n-1-i-τ i )φ 1 (|x(n-1-j-δ j )|) … x(ni-τ i )φ P (|x(n-1-j-δ j )|)'s previous line is x(n-1-i-τ i )φ 1 (|x(n-1-j-δ j )|) … x(n-1-i-τ i )φ P (|x(n-1-j-δ j )|), the next line is x(n+1-i-τ i )φ 1 (|x(n+1-j-δ j )|) … x(n+1-i-τ i )φ P (|x(n+1-j-δ j )|).

[0136] Among them, A(i, j, τ i , δ j ) H Denotes the matrix A(i, j, τ i , δ j ), It means (τ i , δ j ) is a set of values.

[0137] In step S503, according to Update the matrix A, represents the augmented matrix.

[0138] In step S504, according to y res =yA*pinv(A)*yUpdatey res , where pinv(A) represents the pseudo-inverse matrix of matrix A.

[0139] In step S505, Add to the set (τ, δ).

[0140] Here, for each set of values ​​of (i, j), the embodiment of the present application determines in step S502 Afterwards, step S503 can be used to Add to matrix A, that is, update matrix A to increase In addition, the embodiment of the present application can update y through step S504 res The value of, and through step S505 the determined set of values Add to the set (τ, δ).

[0141] On this basis, method 500 can execute step S506, taking the product of pinv(A) and y as α ijp .

[0142] In summary, method 500 can be used for τ i , δ j Determine parameters in nonlinear models for discrete-valued scenarios.

[0143] Figure 6 A flow chart of a method 500 for generating a nonlinear model according to some embodiments of the present application is shown. The method 500 may be executed in an electronic device or in the processor 130, for example.

[0144] The nonlinear model is a generalized memory polynomial with fractional delay: y(n) = ∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|), where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the basis of nonlinear function, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, and y(n) represents the output signal. i , δ j The value range is a predetermined continuous interval, for example, [0, 1].

[0145] In step S601, initialize τ i =0,δ j is 0.

[0146] For each set of values ​​of (i, j), method 600 may repeat steps S602-S604 until Here, the predetermined threshold value is determined according to a specific application scenario, for example, 0.1.

[0147] In step S602, according to α ijp =pinv(A(x,τ,δ))y determine α ijp Value, where pinv(A(x, τ, δ)) represents the pseudo-inverse matrix of A(x, τ, δ),

[0148] Among them, each row φ of A(x, τ, δ) i In the above example, i ranges from 1 to p, and the value of n changes in each column.

[0149] For example, The previous column element of the row is The previous row of elements in the column is

[0150] g k (·) represents the coefficient of the fractional delay filter, which can be expressed as a Lagrange difference polynomial, for example.

[0151] In step S603, according to Determine the disturbance Δ=(ε i , η j ), where the disturbance Δ is the i , δ j ) takes a value of Time pair (τ i , δ j ), where

[0152] B=[C|D]

[0153]

[0154]

[0155] express exist About δ j The derivative of

[0156] Determined according to the following formula:

[0157]

[0158] In step S604, τ is updated according to the following method: i , δ j :

[0159] τ i =τ i +ε i

[0160] δ j =δ j +η j .

[0161] In summary, method 600 can be used for τ i , δ j Determine parameters in nonlinear models for continuously valued scenarios.

[0162] Figure 7 A flow chart of a signal processing method 700 according to some embodiments of the present application is shown. The signal processing method 700 may be executed in the signal processing system 120 or an electronic device, for example.

[0163] like Figure 7 As shown, in step S701, a time delay process is performed on an input signal of a signal processing system to generate a fractional time delay signal.

[0164] In step S702, delay processing is performed on the fractional delay signal to generate a signal processed with integer delay.

[0165] In step S703, the signal after integer delay processing is processed according to the mathematical model of the signal processing system to obtain an output signal of the signal processing system.

[0166] In summary, according to the signal processing method of the embodiment of the present application, it is possible to generate a fractional delay signal without increasing the sampling rate, and generate an output signal based on the mathematical model of the signal processing system, which helps to improve the recognition accuracy and avoid the increase in power consumption caused by increasing the sampling rate.

[0167] In some embodiments, the mathematical model of the signal processing system is a generalized memory polynomial. Step S701 can generate a first fractional delay signal and a second fractional delay signal. Step S702 can delay the first fractional delay signal to output a first integer delay signal, and delay the second fractional delay signal to output a second integer delay signal. Step S703 processes the first integer delay signal and the second integer delay signal according to the generalized memory polynomial to obtain the output signal of the signal processing system. In this way, the signal processing method of the embodiment of the present application can generate the first fractional delay signal and the second fractional delay signal without increasing the sampling rate, and generate the output signal based on the mathematical model of the generalized memory polynomial of the signal processing system, which helps to improve the recognition accuracy and avoid the increase in power consumption caused by increasing the sampling rate.

[0168] In some embodiments, the mathematical model of the signal processing system 120 is a generalized memory polynomial of fractional delay:

[0169] y(n)=∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|).

[0170] Where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the nonlinear function basis, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, and y(n) represents the output signal of the signal processing system.

[0171] Step S701 can generate τ i The corresponding first fractional delay signal x(n-τ i ) and δ j The corresponding second fractional delay signal x(n-δ j ).

[0172] Step S702 may be to process the first fractional delay signal x(n-τ i ) is delayed to output a first integer delay signal x(ni-τ i ), and the second fractional delayed signal x(n-δ j ) is delayed to output a second integer time-delay signal x(nj-δ j ).

[0173] Step S703 may be implemented as method 800 .

[0174] like Figure 8 As shown, in step S801, according to α ijp 、x(nj-δ j ) Generate α ijp φ p (|x(nj-δ j )|).

[0175] In step S802, generate x(ni-τ i ) and α ijp φ p (|x(nj-δ j )|).

[0176] In step S803, according to x(ni-τ i ) and α ijp φ p (|x(nj-δ j )|) to generate the output signal y(n) of the signal processing system.

[0177] In summary, according to the method 800 of the embodiment of the present application, it is possible to generate a first fractional delay signal and a second fractional delay signal without increasing the sampling rate, and generate an output signal based on a mathematical model of a generalized memory polynomial of the fractional delay, which helps to improve the recognition accuracy and avoid the increase in power consumption caused by increasing the sampling rate.

[0178] Fig. 9 A schematic diagram of a base station according to some embodiments of the present application is shown.

[0179] like Fig. 9 As shown, the base station includes a signal processing system 120 and a power amplifier unit 140 .

[0180] The signal processing system 120 is at the input end of the power amplifier unit 140. The signal processing system 120 can perform pre-distortion processing to obtain a pre-distorted signal. The pre-distorted signal enters the power amplifier unit 140. The power amplifier unit 140 can output an amplified signal. The signal processing system 120 can compensate for the nonlinearity of the power amplifier unit 140 to suppress the distortion of the power amplifier unit 140.

[0181] Fig.10 Schematic diagram of an electronic device according to some embodiments of the present application is shown. Fig.10 As shown, the electronic device includes one or more processors (CPU) 1002, a communication module 1004, a memory 1006, a user interface 1010, and a communication bus 1008 for interconnecting these components.

[0182] The processor 1002 may receive and send data through the communication module 1004 to implement network communication and / or local communication.

[0183] The user interface 1010 includes one or more output devices 1012, which include one or more speakers and one or more screens. The user interface 1010 also includes one or more input devices 1014. The user interface 1010 may be, for example, a button, but is not limited thereto.

[0184] Memory 1006 may be a high-speed random access memory, such as DRAM, SRAM, DDR RAM, or other random access solid-state storage devices; or a non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

[0185] The memory 1006 stores an instruction set executable by the processor 1002, including:

[0186] operating system 1016, including programs for handling various basic system services and for performing hardware-related tasks;

[0187] Application 1018 includes various programs for implementing the above solutions. Such programs can implement the processing flow in the above examples, for example, a nonlinear model generation method or a signal processing method.

[0188] In addition, each embodiment of the present application can be implemented by a data processing program executed by a data processing device such as a computer. Obviously, the data processing program constitutes the present invention. In addition, the data processing program usually stored in a storage medium is executed by directly reading the program out of the storage medium or by installing or copying the program to a storage device (such as a hard disk and / or memory) of the data processing device. Therefore, such a storage medium also constitutes the present invention. The storage medium can use any type of recording method, such as paper storage media (such as paper tape, etc.), magnetic storage media (such as floppy disks, hard disks, flash memory, etc.), optical storage media (such as CD-ROM, etc.), magneto-optical storage media (such as MO, etc.), etc.

[0189] Therefore, the present application also discloses a non-volatile storage medium, in which a program is stored. The program includes instructions, and when the instructions are executed by a processor, the electronic device executes the nonlinear model generation method or signal processing method according to the present application.

[0190] In addition, the method steps described in this application can be implemented by hardware in addition to being implemented by a data processing program, for example, by logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers, etc. Therefore, such hardware that can implement the signal processing method of the embodiments of this application can also constitute this application.

[0191] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the application shall be included in the scope of protection of the present application.

Claims

1. A signal processing system, It is characterized in that include: A fractional delay generating unit, used for performing delay processing on an input signal of the signal processing system to generate a fractional delay signal; An integer delay unit, used for performing delay processing on the fractional delay signal to generate a signal processed with integer delay; A model processing unit, used for processing the signal after integer delay processing according to the mathematical model of the signal processing system to obtain an output signal of the signal processing system; in, The mathematical model of the signal processing system is a generalized memory polynomial; A fractional delay generating unit, configured to generate a first fractional delay signal and a second fractional delay signal; The integer delay unit includes a first integer delay module and a second integer delay module, wherein the first integer delay module is used to perform delay processing on the first fractional delay signal to output a first integer delay signal, and the second integer delay module is used to perform delay processing on the second fractional delay signal to output a second integer delay signal; A model processing unit, used for processing the first integer time-delay signal and the second integer time-delay signal according to the generalized memory polynomial to obtain an output signal of the signal processing system; The generalized memory polynomial is a generalized memory polynomial with fractional delay: y(n) = ∑ ijp α ijp x(ni-τ i )φ p (|x(nj-δ j )|), where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the nonlinear function basis, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, α ijp represents the coefficient of the input signal, and y(n) represents the output signal; The first fractional time delay signal is τ i The corresponding delayed signal x(n-τ i ); The second fractionally delayed signal is δ j The corresponding second fractional delay signal x(n-δ j ); The first integer time-delay signal is the integer time-delay signal x(ni-τ i ), The second integer time-delay signal is the integer time-delay signal x(nj-δ j ).

2. The signal processing system according to claim 1, It is characterized in that The fractional delay generation unit is used to generate τ i The corresponding first fractional delay signal x(n-τ i ) and δ j The corresponding second fractional delay signal x(n-δ j ); The first integer delay module is used to delay the first fractional delay signal x(n-τ i ) is delayed to output a first integer delay signal x(ni-τ i ), The second integer delay module is used to delay the second fractional delay signal x(n-δ j ) is delayed to output a second integer time-delay signal x(nj-δ j ).

3. The signal processing system according to claim 1 or 2, It is characterized in that The model processing unit includes a nonlinear function lookup table, a multiplier and an accumulator, in, Nonlinear function lookup table, used to x(nj-δ j )generate Multiplier, used to generate x(ni-τ i )and The product of Accumulator, used to calculate the value of x(ni-τ i )and The product of generates the output signal y(n) of the signal processing system.

4. The signal processing system according to claim 3, It is characterized in that Further including: A processor for determining a generalized memory polynomial of the fractional delay τ i ,δ j .

5. The signal processing system according to claim 3, It is characterized in that Further including: A signal distribution unit is used to distribute the first fractional delay signal x(n-τ) generated by the fractional delay generation unit to the i ) is input into the first integer delay module, and the second fractional delay signal x(n-δ j ) Input the second integer delay module.

6. The signal processing system according to claim 4, It is characterized in that τ i ,δ j The value ranges are all predetermined discrete sets, and the processor determines the generalized memory polynomial of the fractional delay according to the following method: τ i ,δ j : Initialize the matrix A to an empty matrix, initialize the set (τ,δ) to an empty set, and initialize the parameter y res is y, where y represents the target signal; For each set of values ​​of (i, j), determine The largest value Where A(i,j,τ i ,δ j ) is the nonlinear basis of the generalized memory polynomial of fractional delay, in, Among them, A(i,j,τ i ,δ j ) H Denotes the matrix A(i,j,τ i ,δ j ), It means (τ i ,δ j ) a set of values; according to Update the matrix A, represents the augmented matrix; According to y res =yA*pinv(A)*yUpdatey res , where pinv(A) represents the pseudo-inverse matrix of matrix A; Will Add to the set (τ,δ); Multiply pinv(A) and y as 7. The signal processing system according to claim 4, It is characterized in that τ i , δ j The value ranges are all predetermined continuous intervals, and the processor determines the generalized memory polynomial of the fractional delay according to the following method: τ i , δ j : Initialize τ i =0,δ j is 0; For each set of values ​​of (i, j), perform the following operations until Less than the preset threshold: according to Sure Value, where pinv(A(x,τ,δ)) represents the pseudo-inverse matrix of A(x,τ,δ), g k (.) represents the coefficient of the fractional delay filter; according to Determine the disturbance Δ=(ε i ,η j ), where the disturbance Δ is the i ,δ j ) takes a value of Time pair (τ i ,δ j ), where B=[C|D] express exist About δ j The derivative of Determined according to the following formula: Update τ according to the following method i , δ j : t i =t i +e i d j =d j +n j 。 8. A method for generating a nonlinear model. It is characterized in that The nonlinear model is a generalized memory polynomial with fractional delay: Where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the basis of nonlinear function, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, represents the coefficient of the input signal, y(n) represents the output signal, τ i , δ j The value ranges are all predetermined discrete sets; the generation method includes: Initialize the matrix A to an empty matrix, initialize the set (τ,δ) to an empty set, and initialize the parameter y res is y, where y represents the target signal; For each set of values ​​of (i, j), determine The largest value Where A(i,j,τ i ,δ j ) is the nonlinear basis of the generalized memory polynomial of fractional delay, in, Among them, A(i,j,τ i ,δ j ) H Denotes the matrix A(i,j,τ i ,δ j ), It means (τ i ,δ j ) a set of values; according to Update the matrix A, represents the augmented matrix; According to y res =yA*pinv(A)*yUpdatey res , where pinv(A) represents the pseudo-inverse matrix of matrix A; Will Add to the set (τ,δ); Multiply pinv(A) and y as 9. A method for generating a nonlinear model. It is characterized in that The nonlinear model is a generalized memory polynomial with fractional delay: Where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the basis of nonlinear function, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, represents the coefficient of the input signal, y(n) represents the output signal, τ i , δ j The value range is a predetermined continuous interval; the generation method includes: Initialize τ i =0,δ j is 0; For each set of values ​​of (i, j), perform the following operations until Less than the preset threshold: according to Sure Value, where pinv(A(x,τ,δ)) represents the pseudo-inverse matrix of A(x,τ,δ), g k (.) represents the coefficient of the fractional delay filter; according to Determine the disturbance Δ=(ε i ,η j ), where the disturbance Δ is the i ,δ j ) takes a value of Time pair (τ i ,δ j ), where B=[C|D] express exist About δ j The derivative of Determined according to the following formula: Update τ according to the following method i , δ j : t i =t i +e i d j =d j +n j 。 10. A signal processing method, It is characterized in that include: Performing time delay processing on an input signal of a signal processing system to generate a fractional time delay signal; Delay processing is performed on the fractional delay signal to generate a signal processed with integer delay; According to the mathematical model of the signal processing system, the signal after the integer time delay processing is processed to obtain the output signal of the signal processing system; in, The mathematical model of the signal processing system is a generalized memory polynomial, and the generalized memory polynomial is a generalized memory polynomial of fractional delay: Where n is the sampling point number of the input signal, x(n) is the input signal, i and j are integer delays, and φ p (·) is the nonlinear function basis, τ i represents the fractional delay corresponding to tap ni, δ j represents the fractional delay corresponding to tap nj, p represents the number of nonlinear bases, represents the coefficient of the input signal, and y(n) represents the output signal; The fractional delay signal includes a first fractional delay signal and a second fractional delay signal. The signal processed by integer time delay includes a first integer time delay signal and a second integer time delay signal The first fractional time delay signal is τ i The corresponding delayed signal x(n-τ i ); The second fractionally delayed signal is δ j The corresponding second fractional delay signal x(n-δ j ); The first integer time-delay signal is the integer time-delay signal x(ni-τ i ), The second integer time-delay signal is the integer time-delay signal x(nj-δ j ).

11. An electronic device, It is characterized in that include: Memory; A processor, configured to execute the method for generating a nonlinear model as claimed in claim 8 or 9, or the signal processing method as claimed in claim 10.

12. A storage medium storing a program, wherein the program includes instructions, It is characterized in that When the instructions are executed by an electronic device, the electronic device executes the nonlinear model generation method according to claim 8 or 9 or the signal processing method according to claim 10.

13. A base station, It is characterized in that include: The signal processing system according to any one of claims 1 to 7; Power amplifier unit.

Images