A storage-computation fusion multiplier and its control method

Abstract

The present invention discloses a storage-computation fusion multiplier and a control method thereof. The system performs Booth encoding on the acquired multiplier through an encoding circuit module, and then writes the encoded multiplier into a static random access memory module for storage. When calculation is required, the multiplier and multiplicand are called, and the multiplier and multiplicand are calculated through a multiplier calculation module. By combining the encoding circuit and the memory, the encoded data is stored in the memory and read out during subsequent calculations. For multiplication calculations in which one of the two operands changes slowly, only one encoding is required, which effectively solves the problem of complex Booth multiplier encoding circuits, effectively reduces the power consumption of the Booth multiplier during calculations, and improves the speed of the Booth multiplier calculations. The present invention can be widely applied in the field of integrated circuit technology.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a storage-computation fusion multiplier and a control method thereof. Background Art

[0002] Multipliers are an essential component of modern computers, playing a crucial role in digital signal processing, filters, processors, and specialized accelerators. Their performance and power consumption often determine the success of the entire system. Reducing both performance and power consumption is a key design challenge in microprocessor and accelerator designs. Microprocessors and accelerators are typically complex, and their multiplication-accumulation speed determines the overall system speed. Prior art multipliers suffer from high power consumption, insufficient precision, and excessive latency.

[0003] In summary, the problems existing in the relevant technologies need to be solved urgently. Summary of the Invention

[0004] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0005] To this end, an object of an embodiment of the present invention is to provide a storage-computation fusion multiplier and a control method thereof, which can solve the problem of complex multiplier encoding circuits, effectively reduce the power consumption of the multiplier during calculation, and improve the speed of multiplier calculation.

[0006] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0007] In one aspect, an embodiment of the present invention provides a storage-computation fusion multiplier, including:

[0008] An encoding circuit module, the encoding circuit module is used to convert the multiplier into a corresponding Booth code;

[0009] a static random access memory module, the static random access memory module being used to write the multiplier encoded by the encoding circuit module;

[0010] A multiplier calculation module, the multiplier calculation module comprising a partial product generation circuit, a Wallace tree compression tree, and a carry lookahead adder, wherein the partial product generation circuit is used to generate partial products through the Booth coding control; the Wallace tree compression tree compresses the partial products, and the carry lookahead adder is used to add the compressed partial products to obtain a final result;

[0011] The output end of the encoding circuit module is connected to the input end of the static random access memory module, the output end of the static random access memory module is connected to the first input end of the multiplier calculation module, the second input end of the multiplier calculation module is used to input the multiplicand, and the output end of the multiplier calculation module is used to output the final result.

[0012] Furthermore, the multiplier also includes a trigger module, the input end of the trigger module is connected to the output end of the static random access memory module, the output end of the trigger module is connected to the first input end of the multiplier calculation module, and the trigger module is used to synchronize the multiplicand and the encoded multiplier.

[0013] Furthermore, the static random access memory module includes a write drive circuit and a sense amplifier. The output end of the encoding circuit module is connected to the input end of the write drive circuit, the output end of the write drive circuit is connected to the input end of the sense amplifier, and the output end of the sense amplifier is connected to the trigger.

[0014] Furthermore, the static random access memory module also includes a storage unit, the output end of the encoding circuit module is connected to the input end of the storage unit, the output end of the storage unit is connected to the input end of the sense amplifier, and the storage unit is used to store the encoded multiplier.

[0015] Furthermore, the static random access memory module further includes a pre-charging circuit, which is connected to the storage unit and is used to charge the bit line.

[0016] Furthermore, the multiplier also includes a controller, a key module and a display module. The output end of the key module is connected to the input end of the controller. The controller is used to control and collect working status of the encoding circuit module, the static random access memory module and the multiplier calculation module. The output end of the controller is connected to the input end of the display module.

[0017] Furthermore, the multiplier further includes a communication module, which is connected to the controller. The communication module is used to communicate with a host computer, and the controller is used to control the multiplier to operate according to instructions issued by the host computer.

[0018] On the other hand, an embodiment of the present invention provides a control method for a storage-computation fusion multiplier, comprising the following steps:

[0019] Get the multiplier and multiplicand through the key module;

[0020] Encoding the multiplier by an encoding circuit module;

[0021] The multiplicand and the encoded multiplier are calculated by a multiplier calculation module.

[0022] Furthermore, the control method further includes:

[0023] The encoded multiplier is stored in a static random access memory module.

[0024] Furthermore, the step of encoding the multiplier by the encoding circuit module specifically includes:

[0025] Store all multipliers in a queue;

[0026] sequentially obtaining multipliers from the queue and encoding the current multiplier through the encoding circuit module;

[0027] This continues until all multipliers have been encoded.

[0028] The present invention discloses a storage-computation fusion multiplier and a control method thereof, which have the following beneficial effects:

[0029] This embodiment uses an encoding circuit module to perform Booth encoding on the acquired multiplier, then writes the encoded multiplier into a static random access memory module for storage. When calculation is required, the multiplier and multiplicand are called and the multiplier and multiplicand are calculated by the multiplier calculation module. This embodiment integrates the memory and the calculation unit, effectively reducing the movement of data between the memory and the operator, reducing the time overhead of memory access, thereby significantly improving the calculation speed and reducing the power consumption of the operation. This embodiment only reads when the multiplier changes, reducing the number of reads from the memory and reducing the power consumption required to read data. Furthermore, by combining the encoding circuit and the memory, the encoded data is stored in the memory and read out during subsequent calculations. For multiplication calculations in which one of the two operands changes slowly, only one encoding is required, effectively solving the problem of complex Booth multiplier encoding circuits, effectively reducing the power consumption of the Booth multiplier during calculations, and improving the speed of the Booth multiplier calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following introduction is made to the drawings of the embodiments of the present invention or the related technical solutions in the prior art. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0031] Figure 1This is a module block diagram of a storage-computation fusion multiplier provided in an embodiment of the present application;

[0032] Figure 2 A flow chart of a control method for a memory-computation fusion multiplier provided in an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of a precoding flow chart of a control method for a memory-computation fusion multiplier provided in an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of a multiplication calculation flow of a control method for a storage-computation fusion multiplier provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are provided for ease of description only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted based on the understanding of those skilled in the art.

[0036] In the description of the present invention, "a plurality" means more than two. If a first or second is described, it is only used to distinguish technical features and should not be understood as indicating or implying relative importance, implicitly indicating the number of the indicated technical features, or implicitly indicating the order of the indicated technical features. In addition, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. The terms used in this specification are only for describing specific embodiments and are not intended to limit the present invention.

[0037] Before further explaining the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0038] 1) Static Random-Access Memory (SRAM) is a type of random access memory. The term "static" refers to the fact that the data stored in this type of memory remains permanently stored as long as the power is on. In contrast, the data stored in dynamic random access memory (DRAM) requires periodic updating. However, when the power supply is cut off, the data stored in SRAM will disappear (called volatile memory). This is different from ROM or flash memory, which can still store data after power is removed.

[0039] 2) A multiplier is an electronic device that multiplies two unrelated analog signals. It can multiply two binary numbers and is composed of a more basic adder. Multipliers can be implemented using a range of computer arithmetic techniques. Multipliers are not only the primary building block for analog operations such as multiplication, division, exponentiation, and square root extraction, but are also widely used in electronic communication systems for modulation, demodulation, frequency mixing, phase detection, and automatic gain control. They can also be used for filtering, waveform shaping, and frequency control, making them a versatile functional circuit.

[0040] Multipliers are an essential component of modern computers, playing a crucial role in digital signal processing, filters, processors, and specialized accelerators. Their performance and power consumption often determine the success of the entire system. Reducing both performance and power consumption is a key design challenge in microprocessor and accelerator design. Microprocessors and accelerators are typically complex, and their multiplication-accumulation speed determines the speed of the entire system.

[0041] For this purpose, refer to Figure 1 The present application proposes a storage-computation fusion multiplier and a control method thereof. The system includes an encoding circuit module, the encoding circuit module is used to convert the multiplier into a corresponding Booth code; a static random access memory module, the static random access memory module is used to write the multiplier encoded by the encoding circuit module; a multiplier calculation module, the multiplier calculation module includes a partial product generation circuit, a Wallace tree compression tree, and a carry lookahead adder, wherein the partial product generation circuit is used to generate partial products through the Booth code control; the Wallace tree compression tree compresses the partial products, and the carry lookahead adder is used to add the compressed partial products to obtain a final result;

[0042] The output end of the encoding circuit module is connected to the input end of the static random access memory module, the output end of the static random access memory module is connected to the first input end of the multiplier calculation module, the second input end of the multiplier calculation module is used to input the multiplicand, and the output end of the multiplier calculation module is used to output the final result.

[0043] The present application uses an encoding circuit module to perform Booth encoding on the obtained multiplier, and then writes the encoded multiplier into a static random access memory module for storage. When calculation is required, the multiplier and multiplicand are called, and the multiplier and multiplicand are calculated by the multiplier calculation module. This embodiment effectively reduces the movement of data between the memory and the operator by integrating the memory and the calculation unit, reduces the time overhead of memory access, thereby greatly improving the operation speed and reducing the operation power consumption. This embodiment only reads when the multiplier changes, reducing the number of times it reads from the memory and reducing the power consumption required to read data. In addition, by combining the encoding circuit and the memory, the encoded data is stored in the memory and read out during the subsequent calculation. For multiplication calculations in which one of the two operands changes slowly, only one encoding is required, which effectively solves the problem of complex Booth multiplier encoding circuits, effectively reduces the power consumption of the Booth multiplier during calculation, and improves the speed of the Booth multiplier calculation.

[0044] As a further optional implementation, the multiplier also includes a trigger module, the input end of the trigger module is connected to the output end of the static random access memory module, the output end of the trigger module is connected to the first input end of the multiplier calculation module, and the trigger module is used to synchronize the multiplicand and the encoded multiplier.

[0045] Specifically, actual digital systems often contain a large number of memory cells, and they are often required to operate synchronously at the same time. To achieve this goal, a clock pulse (CLK) is introduced into each memory cell circuit as a control signal. Only when the CLK arrives will the circuit be "triggered" and operate, and the output state changes according to the input signal. This memory cell circuit that can only operate when triggered by a clock signal is called a flip-flop, to distinguish it from a latch that is not controlled by a clock signal.

[0046] In this embodiment, a trigger module can be provided between the static random access memory module and the multiplier calculation module to synchronize the encoded multiplier and multiplicand. When calculation is required, the encoded multiplier is read from the static random access memory one cycle in advance and input into the trigger. The next multiplier is read only when the multiplier needs to change. When the multiplier remains unchanged, no data read operation is required. Synchronizing the encoded multiplier and multiplicand via the trigger reduces power consumption caused by invalid flip-flops.

[0047] Further as an optional implementation, the static random access memory module includes a write drive circuit and a sensitive amplifier, the output end of the encoding circuit module is connected to the input end of the write drive circuit, the output end of the write drive circuit is connected to the input end of the sensitive amplifier, and the output end of the sensitive amplifier is connected to the trigger.

[0048] As a further optional embodiment, the static random access memory module also includes a storage unit, the output end of the encoding circuit module is connected to the input end of the storage unit, the output end of the storage unit is connected to the input end of the sensitive amplifier, and the storage unit is used to store the encoded multiplier.

[0049] Specifically, the write driver circuit is used to write the Booth-encoded multiplier, the sensitive amplifier is used to read out data, and the storage unit is used to access the Booth-encoded multiplier; after the encoding circuit module converts the multiplier into the corresponding Booth code, the Booth-encoded multiplier is written into the static random access memory module through the write driver circuit and stored in the storage unit. When the Booth-encoded multiplier needs to be called, the data is output through the sensitive amplifier.

[0050] As a further optional implementation, the static random access memory module further includes a pre-charging circuit, the pre-charging circuit is connected to the storage unit, and the pre-charging circuit is used to charge the bit line.

[0051] Specifically, the precharge circuit is used to charge the bit line before reading and writing data. In a MOS transistor, the drain is connected to the bit line, and the gate is connected to the word line. The T transistor is turned on when the word line is high, and turned off when the word line is low. When accessing the SRAM, the word line is raised to a high level, turning on the two control switch transistors M and M in each basic cell, connecting the basic cell to the bit line. The bit line is used to read or write the stored state of the basic cell. Although two inverted bit lines are not required, such inverted bit lines help improve noise tolerance.

[0052] Further as an optional implementation, the multiplier also includes a controller, a key module and a display module, the output end of the key module is connected to the input end of the controller, the controller is used to control and collect working status of the encoding circuit module, the static random access memory module and the multiplier calculation module, and the output end of the controller is connected to the input end of the display module.

[0053] Specifically, the multiplier of the embodiment of the present invention has a multiplier and multiplicand input function and a result feedback function, wherein the control input is realized through a key module, and the result feedback display is realized through an indicator light, sound, and display module.

[0054] The display module can be a liquid crystal display installed at the front end of the multiplier, and can be linked with the controller to display the calculation results of the multiplier calculation module.

[0055] As a further optional implementation, the multiplier also includes a communication module, which is connected to the controller. The communication module is used to communicate with a host computer, and the controller is used to control the multiplier to work according to instructions issued by the host computer.

[0056] The main body of a storage-computation fusion multiplier implementation environment mainly includes a host computer and a communication module. The host computer communicates with the communication module. The host computer sends corresponding instructions to the communication module, which then sends the instructions to the controller, thereby realizing remote control of the multiplier.

[0057] Specifically, the host computer in this embodiment may include but is not limited to any one or more of a smart watch, a smart phone, a computer, a personal digital assistant (PDA), an intelligent voice interaction device, a smart home appliance or a vehicle-mounted terminal. The communication module may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network) and big data and artificial intelligence platforms. A communication connection can be established between the host computer and the communication module through a wireless network or a wired network. The wireless network or wired network uses standard communication technology and / or protocols. The network can be set to the Internet or any other network, such as but not limited to a local area network (LAN), a metropolitan area network (MAN), a wide area network (WAN), any combination of mobile, wired or wireless networks, private networks or virtual private networks.

[0058] Reference Figure 2 The embodiment of the present invention provides a control method for a storage-computation fusion multiplier, which is executed by the above-mentioned storage-computation fusion multiplier and includes the following steps:

[0059] S101, obtaining a multiplier and a multiplicand through a key module;

[0060] S102, encoding the multiplier through an encoding circuit module;

[0061] S103 , calculating the multiplicand and the encoded multiplier by a multiplier calculation module.

[0062] The obtained multiplier is Booth-encoded through the encoding circuit module, and then the encoded multiplier is written into the static random access memory module for storage. When calculation is required, the multiplier and multiplicand are called and calculated through the multiplier calculation module.

[0063] Specifically, the above steps can be divided into two parts: precoding and multiplier calculation. Figure 3 As shown, first the multiplier is Booth coded, then the Booth code is stored in the static random access memory, and then it is determined whether all multipliers have been coded. If so, the pre-coding ends. If not, the next multiplier is obtained for coding. The multiplier calculation is as follows: Figure 4 As shown, the encoded multiplier is first read out from the static random access memory module, and then the multiplicand and the multiplier read out from the static random access memory module are input into the calculation module for calculation, and the results are output at the same time. Then, it is judged whether all calculations are completed. If so, the calculation ends. If not, the judgment is continued to determine whether the multiplier has changed. If so, the above steps are repeated to continue reading the multiplier for calculation. If not, the multiplicand and the multiplier read out from the static random access memory module are input into the calculation module for calculation.

[0064] By integrating the memory and the computing unit, this embodiment effectively reduces the movement of data between the memory and the operator, lowering the time overhead of memory access, thereby significantly improving the computing speed and reducing computing power consumption. This embodiment only reads when the multiplier changes, reducing the number of times the memory is read and reducing the power consumption required to read data. Furthermore, by combining the encoding circuit and the memory, the encoded data is stored in the memory and read out during subsequent calculations. For multiplication calculations in which one of the two operands changes slowly, only one encoding operation is required. This effectively solves the problem of complex encoding circuits in Booth multipliers, effectively reduces the power consumption of Booth multipliers during calculations, and improves the speed of Booth multipliers.

[0065] As an optional implementation, the control method further includes:

[0066] The encoded multiplier is stored in a static random access memory module.

[0067] Specifically, this embodiment integrates the memory and the computing unit, thereby effectively reducing the movement of data between the memory and the computing unit, reducing the time overhead of memory access, thereby greatly improving the computing speed and reducing computing power consumption.

[0068] As a further optional implementation manner, the step of encoding the multiplier by the encoding circuit module specifically includes:

[0069] Store all multipliers in a queue;

[0070] sequentially obtaining multipliers from the queue and encoding the current multiplier through the encoding circuit module;

[0071] This continues until all multipliers have been encoded.

[0072] Specifically, the encoded multiplier is first read out from the static random access memory module, and then the multiplicand and the multiplier read from the static random access memory module are input into the calculation module for calculation, and the results are output at the same time. Then, it is judged whether all calculations are completed. If so, the calculation ends. If not, the judgment is continued to determine whether the multiplier has changed. If so, the above steps are repeated to continue reading the multiplier for calculation. If not, the multiplicand and the multiplier read from the static random access memory module are input into the calculation module for calculation.

[0073] It is understood that, compared with the prior art, the embodiments of the present invention also have the following advantages:

[0074] The present invention integrates a static random access memory and a Booth multiplier, thereby reducing power consumption during data movement, and at the same time reducing the time required for data reading, thereby reducing the demand for system storage space and computing power. By integrating the encoding circuit and the static random access memory, the process of the multiplier encoding circuit is accelerated, and the power consumption and delay of the multiplier are reduced. Alternatively, pre-encoding is performed through software encoding, and the software-encoded data is stored in the static random access memory, thereby effectively reducing the circuit resources required for the application and improving the efficiency of memory-intensive and computing-intensive applications such as neural networks and filters. At the same time, since no analog calculation is introduced into the overall circuit structure, there is no loss of calculation accuracy.

[0075] It should be appreciated that embodiments of the present invention can be implemented or practiced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The above methods can be implemented in a computer program using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner—according to the methods and figures described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. In addition, the program can be run on a programmed application-specific integrated circuit for this purpose.

[0076] Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The processes described herein (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or a combination thereof. The computer programs described above include a plurality of instructions that may be executed by one or more processors.

[0077] Furthermore, the above methods can be implemented in any type of computing platform that is operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, etc. Various aspects of the present invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, an optical read and / or write storage medium, RAM, ROM, etc., so that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. In addition, the machine-readable code, or portions thereof, can be transmitted over a wired or wireless network. When such media includes instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor, the invention described herein includes these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques described herein, the present invention also includes the computer itself.

[0078] The computer program can be applied to input data to perform the functions described herein, thereby converting the input data to generate output data that is stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the converted data represents a physical and tangible object, including a specific visual depiction of the physical and tangible object produced on the display.

[0079] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the aforementioned embodiments. As long as the technical effects of the present invention are achieved by the same means, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention. Within the scope of protection of the present invention, various modifications and variations of the technical solutions and / or implementation methods are possible.

Claims

1. A storage-computation fusion multiplier, characterized in that: include: An encoding circuit module, the encoding circuit module is used to convert the multiplier into a corresponding Booth code; a static random access memory module, the static random access memory module being used to write the multiplier encoded by the encoding circuit module; A multiplier calculation module, the multiplier calculation module comprising a partial product generation circuit, a Wallace tree compression tree, and a carry lookahead adder, wherein the partial product generation circuit is used to generate partial products through the Booth coding control; the Wallace tree compression tree compresses the partial products, and the carry lookahead adder is used to add the compressed partial products to obtain a final result; The output end of the encoding circuit module is connected to the input end of the static random access memory module, the output end of the static random access memory module is connected to the first input end of the multiplier calculation module, the second input end of the multiplier calculation module is used to input the multiplicand, and the output end of the multiplier calculation module is used to output the final result; The multiplier also includes a trigger module, the input end of the trigger module is connected to the output end of the static random access memory module, the output end of the trigger module is connected to the first input end of the multiplier calculation module, and the trigger module is used to perform synchronization on the multiplicand and the encoded multiplier; the static random access memory module includes a write drive circuit and a sense amplifier, the output end of the encoding circuit module is connected to the input end of the write drive circuit, the output end of the write drive circuit is connected to the input end of the sense amplifier, and the output end of the sense amplifier is connected to the trigger.

2. The storage-computation fusion multiplier according to claim 1, characterized in that: The static random access memory module further includes a storage unit, the output end of the encoding circuit module is connected to the input end of the storage unit, the output end of the storage unit is connected to the input end of the sense amplifier, and the storage unit is used to store the encoded multiplier.

3. The storage-computation fusion multiplier according to claim 2, characterized in that: The static random access memory module further includes a pre-charging circuit, which is connected to the storage unit and is used to charge the bit line.

4. The memory-computation fusion multiplier according to claim 1, characterized in that: The multiplier also includes a controller, a key module and a display module. The output end of the key module is connected to the input end of the controller. The controller is used to control and collect working status of the encoding circuit module, the static random access memory module and the multiplier calculation module. The output end of the controller is connected to the input end of the display module.

5. The memory-computation fusion multiplier according to claim 4, characterized in that: The multiplier further includes a communication module, which is connected to the controller. The communication module is used to communicate with a host computer. The controller is used to control the multiplier to work according to instructions issued by the host computer.

6. A control method for a memory-computation fusion multiplier, executed by a memory-computation fusion multiplier according to any one of claims 1 to 5, characterized in that: The following steps are involved: Get the multiplier and multiplicand through the key module; Encoding the multiplier by an encoding circuit module; The multiplicand and the encoded multiplier are calculated by a multiplier calculation module.

7. The control method of a memory-computation fusion multiplier according to claim 6, characterized in that: The step of encoding the multiplier by the encoding circuit module specifically includes: Store all multipliers in a queue; sequentially obtaining multipliers from the queue and encoding the current multiplier through the encoding circuit module; This continues until all multipliers have been encoded.

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