Burr absorption apparatus and method

Abstract

Embodiments of the present disclosure relate to glitch absorption apparatus and methods. An apparatus comprising a primary processor and a secondary processor configured to receive a first signal, a second signal, and a plurality of input signals and perform the same operations as each other based on the first signal, the second signal, and the plurality of input signals; a comparison circuit configured to receive an output signal of the primary processor and an output signal of the secondary processor and detect a lockstep mismatch between the first processor and the second processor based on the output signals, a fault capture circuit configured to receive the first signal and the second signal and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal and absorb a glitch fed into the first glitch absorption device.

Description

Technical Field

[0001] The present disclosure generally relates to glitch absorption devices and methods in a dual-core lockstep system. Background Art

[0002] As the automotive industry continues to expand and vehicle sizes grow, demand for system-on-chip (SoC) semiconductor devices designed for safety-critical applications continues to grow. Reliability is a key issue in meeting safety requirements for a range of vehicle applications, including advanced passenger assistance systems, electric power steering systems, adaptive cruise control systems, and actuation control systems.

[0003] In safety-critical applications, system failures can occur in computer systems. If the system failures are not detected and corrected quickly, they can lead to hangs and crashes in the computer system. Dual-core lockstep computer systems are used to detect system failures and prevent computer system crashes.

[0004] A dual-core lockstep computer system includes a primary hardware block (e.g., a main processor) and a secondary hardware block (e.g., a secondary processor) configured to operate in lockstep. Both the primary processor and the secondary processor are configured to receive the same input data and execute instructions of the same program code at any given time. After the execution of each instruction, the result from the primary processor is compared with the result from the secondary processor. If any mismatch is found in these results of the two processors, this indicates that there is a fault in the computer system. Therefore, the computer system enters a predefined safe mode.

[0005] In a dual-core lockstep system, a reset function is used to bring the logic to a predefined state. The reset function can be synchronous or asynchronous with respect to the clock signal. Because asynchronous resets do not have clock-related delays, they can be used to implement faster data paths. However, asynchronous resets have some disadvantages. For example, with asynchronous resets, unintended glitches can be generated during the reset assertion process. Unintended glitches can propagate into the logic circuits of the dual-core lockstep system, causing false faults. Such false faults can lead to reliability issues in the dual-core lockstep system. It is desirable to have a simple and reliable glitch absorption device to keep the dual-core lockstep system running reliably. Summary of the Invention

[0006] According to an embodiment, an apparatus includes: a main processor and a secondary processor configured to receive a first signal, a second signal, and a plurality of input signals, and to perform the same operation as each other based on the first signal, the second signal, and the plurality of input signals; a comparison circuit configured to receive output signals of the main processor and the secondary processor, and to detect a lockstep mismatch between the main processor and the secondary processor based on the output signals; a fault capture circuit configured to receive the first signal and the second signal, and to capture a fault signal generated by the comparison circuit; and a first glitch absorbing device configured to receive the first signal and the second signal, and to absorb glitches fed into the first glitch absorbing device.

[0007] According to another embodiment, a method includes placing a first glitch absorbing device at an end of a fault signal path in a local fault collector circuit before the fault signal is sent to a global collector circuit, wherein the local system and the global system have different clock signals and reset signals, and absorbing glitches fed into the first glitch absorbing device by the first glitch absorbing device.

[0008] According to yet another embodiment, a system includes: a glitch absorbing device configured to absorb glitches on a fault signal, the glitch absorbing device being placed at an end of a fault signal path in a local fault collector circuit before the fault signal is sent to a global collector circuit; a main processor and a secondary processor configured to receive a clock signal, a reset signal, and a plurality of input signals, and to perform the same operation as one another based on the clock signal, the reset signal, and the plurality of clock signals; and a comparison circuit configured to receive output signals of the main processor and the secondary processor, and to detect whether the output signal of the main processor matches the output signal of the secondary processor based on the output signals.

[0009] The foregoing has broadly outlined the features and technical advantages of the present disclosure so that the detailed description of the present disclosure below may be better understood. Additional features and advantages of the present disclosure are described in more detail below, which form the subject matter of the claims of the present disclosure. It will also be understood by those skilled in the art that the concepts and specific embodiments disclosed herein may be readily utilized as a basis for modifying or relating to other structures or processes for carrying out the same purpose of the present disclosure. It should be understood by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present disclosure and its advantages, reference is made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A block diagram of a dual-core lockstep system with a glitch absorption device according to various embodiments of the present disclosure is shown.

[0012] Figure 2 Various embodiments according to the present disclosure are shown Figure 1 Timing diagram of the dual-core lockstep system in ; and

[0013] Figure 3 Various embodiments according to the present disclosure are shown Figure 1 FIG. 4 is a flow chart of a method for absorbing glitches in a dual-core lockstep system.

[0014] Unless otherwise indicated, corresponding numerals and symbols in the different figures refer to corresponding parts.The accompanying drawings are drawn to clearly illustrate the relevant concepts of the various embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0015] The making and using of the embodiments of the present disclosure are discussed in detail below. However, it should be understood that the concepts disclosed herein can be encompassed in a wide range of contexts within the specific context of the specification, and that the specific embodiments discussed herein are merely illustrative and not intended to limit the appended claims. Furthermore, it should be understood that various changes, additions, and modifications made herein do not depart from the scope of the present disclosure and are defined by the appended claims.

[0016] The present disclosure will be described with respect to a preferred embodiment in a specific context (i.e., a glitch absorption device in a dual-core system). However, the present disclosure can also be applied to a plurality of safety-critical applications. Various embodiments will be explained in detail herein with reference to the accompanying drawings.

[0017] Figure 1 FIG1 shows a block diagram of a dual-core lockstep system with a glitch absorption device according to various embodiments of the present disclosure. The semiconductor chip 100 may include multiple dual-core lockstep systems and a global fault collection system 120. For simplicity, only one dual-core lockstep system (e.g., dual-core lockstep system 110) is shown in FIG1. Figure 1 . Each dual-core lock-step system can generate a fault signal in response to a fault (e.g., a lock-step mismatch). Each dual-core lock-step system may include a local fault collector circuit. The local fault collector circuit detects a fault (e.g., a lock-step mismatch) in the dual-core lock-step system and sends a fault signal to a global fault collection system. The global fault collection system 120 is applied to receive fault signals generated by multiple dual-core lock-step systems. Throughout the description, the dual-core lock-step system 110 may alternatively be referred to as a local system. The global circuit collection system 120 may also alternatively be referred to as a global system.

[0018] The dual-core lockstep system 110 includes a first processor 102, a second processor 104, a comparison circuit 112, a fault capture circuit 114, and a glitch absorption device 116. The dual-core lockstep system 110 is configured to receive a first clock signal (Clock I), a first reset signal (Reset I), and multiple input signals. Based on the received signals, the dual-core lockstep system 110 generates multiple functional output signals.

[0019] The first clock signal is generated by a clock generator (not shown). The first clock signal is used to regulate a plurality of intellectual property (IP) components (eg, communication IP, timer IP, and memory IP). It should be noted that Figure 1 Only one clock signal is shown for the dual-core lockstep system 110. This is merely an example, the dual-core lockstep system 110 may include multiple clock signals, and the clock signals shown herein are merely used to clearly illustrate the inventive aspects of various embodiments.

[0020] The first reset signal is used to reset the different parts of the dual core lockstep signal 110 before the start of functional operation. Figure 1 Only one reset signal is shown for the dual-core lockstep system 110. This is just an example, and the dual-core lockstep system 110 may include multiple reset signals depending on design needs.

[0021] The input signal may be a data signal. Alternatively, the input signal may be a test signal. The test signal is used when the dual-core lockstep system 110 is configured to operate in test mode. The data signal is used when the dual-core lockstep system 110 is configured to operate in functional mode. The data signals are generated by various IPs and fed into the first processor 102 and the second processor 104, respectively. The first processor 102 processes the data signal and feeds the processed data signal to the plurality of IPs connected to the outputs of the first processor 102.

[0022] like Figure 1 As shown, multiple input signals flow through a common signal path. At node A, multiple input signals flow into two different signal paths coupled to the first processor 102 and the second processor 104, respectively. A first clock signal flows through the common signal path. At node B, the first clock signal flows into two different signal paths coupled to the first processor 102 and the second processor 104, respectively. Similarly, a first reset signal flows through the common signal path. At node C, the first reset signal flows into two different signal paths coupled to the first processor 102 and the second processor 104, respectively.

[0023] In some embodiments, the first processor 102 and the second processor 104 are two identical processors that are reset in the same state and fed with the same input signals. If the two processors operate correctly, the same output is generated by the two processors. During operation, a fault may occur and reach the outputs of these two processors. Such a fault can be detected by comparing the outputs of the two processors. After detecting such a fault, the dual-core lockstep system 110 can take appropriate actions to handle the fault to prevent the system from being damaged. In some embodiments, the first processor 102 is configured to perform system operations. The second processor 104 is configured to confirm the correctness of the operation of the first processor 102. Throughout the description, the first processor 102 may alternatively be referred to as the main processor 102. The second processor 104 may be referred to as the auxiliary processor 104.

[0024] Comparison circuit 112 has a first input coupled to primary processor 102, a second input coupled to the output of secondary processor 104, and an output (LS) coupled to fault capture circuit 114. In some embodiments, comparison circuit 112 is implemented as an exclusive-OR gate. Comparison circuit 112 is configured to compare the output signal of primary processor 102 with the output signal of secondary processor 104 and detect whether the output signal of primary processor 102 matches the output signal of secondary processor 104. If any mismatch is found between the results of the two processors, a fault is detected in dual-core lockstep system 110. Therefore, dual-core lockstep system 110 enters a defined safe mode.

[0025] In operation, the XOR gate generates an output signal having a logic low state when the input signal of the main processor 102 matches the output signal of the secondary processor 104. On the other hand, when the output signal of the main processor 102 does not match the output signal of the secondary processor 104, the XOR gate generates an output signal having a logic high state.

[0026] The fault capture circuit 114 has an input coupled to the output of the comparison circuit 112 and an output (GF) coupled to the input of the glitch absorption device 116. In some embodiments, the fault capture circuit 114 includes a D-type flip-flop. The D-type flip-flop is used to generate a fault signal based on the output signal of the comparison circuit 112. Figure 1 As shown, the fault capture circuit 114 is configured to receive the output signal of the comparison circuit 112, the first clock signal, and the delayed first reset signal (reset FF). The fault capture circuit 114 is configured to generate a fault signal when the XOR gate generates an output signal with a logic high state. The delayed first reset signal is similar to the first reset signal, except that there is a delay ( Figure 2 shown in ).

[0027] In some embodiments, the comparison circuit 112 and the fault capture circuit 114 form a local fault collector circuit. Figure 1 As shown, the local fault collector circuit detects a fault and sends a fault signal to the global fault collector circuit 118 through the glitch absorption device 116. In other words, the fault collection glitch absorption device 116 is placed at the end of the fault signal path in the local fault collector circuit before the fault signal is sent to the global collector circuit.

[0028] The glitch absorption device 116 has an input coupled to the circuit of the fault capture circuit 114 and an output (CF) coupled to the input of the fault collector circuit 118. In some embodiments, the glitch absorption device 116 includes a D-type flip-flop. The D-type flip-flop is used to absorb glitches on the input signal generated by the fault capture circuit 114. Figure 1 As shown, the glitch absorption device 116 is configured to receive the output signal of the fault capture circuit 114, the first clock signal and the delayed first reset signal. The glitch absorption device 116 is configured to absorb glitches on the fault signal. The detailed operation principle of the glitch absorption device 116 will be referred to below. Figure 2 describe.

[0029] It should be recognized that although Figure 1 One glitch absorption device is shown, but any number of glitch absorption devices can be used to further improve glitch absorption capabilities. In particular, when the reset assertion has been cleared as a multi-cycle path for clocking, the path may have a delay of more than one clock cycle. In this case, multiple glitch absorption devices (e.g., two glitch absorption devices) can be connected in series to effectively absorb glitches caused by long reset assertion propagation delays (e.g., reset assertion propagation delays greater than one clock cycle).

[0030] In some embodiments, the fault collector circuit 118 includes a D-type flip-flop. The D-type flip-flop is used to receive the fault signal generated by the dual-core lockstep system 110. Figure 1 As shown in FIG, the fault collector circuit 118 is configured to receive the output signal of the glitch absorption device 116, the second clock signal (Clock II), and the second reset signal (Reset II). It should be noted that the clock and reset signals of the fault collector circuit 118 are different from the clock and reset signals of the dual-core lockstep system 110.

[0031] Figure 2 Various embodiments according to the present disclosure are shown Figure 1 The timing diagram of the dual-core lockstep system is shown in FIG. Figure 2The horizontal axis represents the time interval. There are nine vertical axes. The first vertical axis Y1 represents the first clock signal (Clock I). The second vertical axis Y2 represents the first reset signal (Reset I). The third vertical axis Y3 represents the output signal (LS) of the comparison circuit 112. The fourth vertical axis Y4 represents the output signal (GF) of the fault capture circuit 114. The fifth vertical axis Y5 represents the output signal (CF) of the glitch absorption device 116. The sixth vertical axis Y6 represents the reset signal (Reset FF) applied to the fault capture circuit 114 and the glitch absorption device 116. The seventh vertical axis Y7 represents the second clock signal (Clock II). The eighth vertical axis Y8 represents the fault output signal generated by the fault collector circuit 118. The ninth vertical axis Y9 represents the second reset signal (Reset II).

[0032] At time t0, the comparison circuit 112 generates a signal with a logic high state. This is a valid fault signal. Figure 2 As shown, the valid fault signal extends over one clock cycle. One clock cycle later, at time t1, the fault capture circuit 114 captures the logic high state and generates a fault signal in response to the logic high state of the output circuit of the comparison circuit 112. Another clock cycle later, at time t2, the glitch absorption device 116 generates a fault signal similar to that generated by the fault capture circuit 114, except for the delay between the fault signal generated by the glitch absorption device 116 and the fault capture circuit 114. Figure 1 , the glitch absorption device 116 sends the fault signal to the fault collector circuit 118. At the next clock cycle of the global system (time t3), the fault collector circuit 118 generates a fault signal (logic high state).

[0033] In operation, the reset assertion may generate a propagation delay. This propagation delay may cause the comparison circuit 113 to malfunction. In particular, glitches may appear on the output signal of the comparison circuit 112. Figure 2 As shown, at time t4, a first glitch appears on the output signal of comparison circuit 112. At time t5, a second glitch appears on the output signal of comparison circuit 112. The first glitch is short. Fault capture circuit 114 does not capture this glitch. The second glitch maintains a logic high state on the leading edge of the next clock cycle (time t6). At time t6, fault capture circuit 114 generates a fault signal in response to the logic high state of the second glitch.

[0034] like Figure 2 As shown, the second glitch does not extend over one clock cycle. The second glitch is absorbed by the glitch absorption device 116. Figure 2As shown, since the second glitch has been absorbed, glitch absorption device 116 does not generate a fault signal. At time t7, fault collector circuit 118 does not generate a fault signal. In other words, glitch absorption device 116 has absorbed the glitch. Because of glitch absorption device 116, the glitch has no impact on the operation of the dual-core lockstep system.

[0035] It should be recognized that although Figure 2 Two glitches on the output signal of the comparison circuit 112 are shown, but any number of glitches may be generated on the output signal of the comparison circuit 112. The glitch absorption device 116 is capable of absorbing any number of glitches.

[0036] It should be further noted that Figure 2 The glitch shown in FIG is caused by the reset assertion propagation delay. As long as the reset assertion propagation delay is less than one clock cycle, the glitch can be safely filtered or absorbed by the glitch absorption device 116. In some embodiments, the duration of the reset assertion propagation delay is greater than one clock cycle. An additional glitch absorption device can be connected in series with the glitch absorption device 116 to prevent the glitch from propagating to the next stage.

[0037] Figure 3 The method for absorbing the Figure 1 A flow chart of the method for detecting glitches in a dual-core lockstep system is shown in FIG. Figure 3 The flowchart shown in FIG is merely an example, which should not unduly limit the scope of the appended claims. A person skilled in the art will recognize many variations, substitutions, and modifications, for example, Figure 3 The various steps shown in the drawings may be added, removed, substituted, rearranged, and repeated.

[0038] The dual-core lockstep system includes a main processor (e.g., processor 1 in FIG1 ) and a secondary processor (e.g., Figure 1 Both the main processor and the auxiliary processor are configured to receive the same input signals, including a clock signal, a reset signal and a plurality of data signals.

[0039] Multiple data signals flow through a common signal path. Figure 1 At node A in FIG, multiple data signals are routed to two different paths, and the two different signal paths are connected to the main processor and the auxiliary processor respectively.

[0040] It should be noted that for controlling the timing of multiple data signals fed into the main processor, multiple primary delay buffers may be placed in the signal path between the first node and the main processor. For controlling the timing of multiple data signals fed into the second processor, multiple secondary delay buffers may be placed in the signal path between the first node and the auxiliary processor.

[0041] The clock signal flows through a common signal path. At a second node (e.g. Figure 1 Node B in FIG. 1 1), the clock signal is routed to two different signal paths connected to the primary processor and the secondary processor, respectively.

[0042] It should be noted that for controlling the timing of the clock signal feeding the primary processor, a number of primary delay buffers can be placed in the signal path between the second node and the primary processor. For controlling the timing of the clock signal feeding the secondary processor, a number of secondary delay buffers can be placed in the signal path between the second node and the secondary processor.

[0043] The reset signal path flows through a common reset signal path. At a third node (e.g. Figure 1 Node C in FIG. 1 1), the reset signal is routed to two different signal paths connected to the primary processor and the secondary processor, respectively.

[0044] It should be noted that for controlling the timing of the reset signal feeding the primary processor, a number of primary delay buffers can be placed in the signal path between the third node and the primary processor. For controlling the timing of the reset signal feeding the secondary processor, a number of secondary delay buffers can be placed in the signal path between the third node and the secondary processor.

[0045] Both the primary processor and the secondary processor process the received signals. The output of the primary processor is compared to the output of the secondary processor at a comparison circuit (e.g. Figure 1 the comparison circuit shown in FIG. 1 1). The output of the comparison circuit determines whether the output signal of the primary processor matches the output signal of the secondary processor. If the outputs of the processors do not match each other, it indicates a fault in the dual-core lockstep system. The dual-core lockstep system enters a predefined safe mode to avoid the propagation of the fault.

[0046] In operation, glitches can occur on the output signal of the comparison circuit. Conventional dual-core configurations prevent the occurrence of glitches by adding a complex circuit to the dual-core lockstep system. In various embodiments of the present disclosure, the following steps are used to absorb glitches that occur in the dual-core lockstep system.

[0047] At step 402, a first glitch absorption device (e.g. Figure 1 the glitch absorption device 1 16 shown in FIG. 1 1) is placed at the end of the fault signal path in the local fault collector circuit before the fault signal is sent to the global collector circuit. The local system is a dual-core lockstep system. The global system includes a fault collector circuit configured to receive fault signals from a plurality of dual-core lockstep systems. The local system and the global system have different clock and reset signals.

[0048] In step 404, the glitch fed into the first glitch absorbing device is absorbed by the first glitch absorbing device. The first glitch absorbing device is a D-type flip-flop. Figure 2 As shown in , the D-type flip-flop is able to absorb glitches on the fault signal.

[0049] Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0050] Furthermore, the scope of the present disclosure is not intended to be limited to the processes, machines, manufactures, compositions of matter, parts, and steps described in the specification. Those skilled in the art will readily appreciate from existing or to-be-developed disclosures of the present disclosure, processes, machines, manufactures, compositions of matter, parts, and steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments disclosed herein and that may be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufactures, compositions of matter, parts, methods, or steps.

Claims

1. A burr absorbing device, comprising: a main processor and a secondary processor configured to receive a first signal, a second signal, and a plurality of input signals, and to perform the same operation as each other based on the first signal, the second signal, and the plurality of input signals; a comparison circuit configured to receive an output signal of the primary processor and an output signal of the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals; a fault capture circuit configured to receive the first signal and the delayed second signal and capture a fault signal generated by the comparison circuit; as well as a first glitch absorbing device configured to receive the first signal and the delayed second signal and absorb glitches fed into the first glitch absorbing device, wherein the first glitch absorbing device comprises a first D-type flip-flop having an input coupled to the output of the fault capture circuit and an output coupled to the input of a fault collector circuit.

2. The device according to claim 1, wherein The first signal is a first clock signal; and The second signal is a first reset signal.

3. The apparatus according to claim 2, further comprising: A fault collector circuit is configured to receive a second clock signal and a second reset signal, the fault collector circuit being coupled to an output of the first glitch absorbing device.

4. The device according to claim 3, wherein: The fault collector circuit includes a second D-type flip-flop.

5. The apparatus according to claim 1, wherein: The comparison circuit includes an XOR gate.

6. The device according to claim 5, wherein: The XOR gate has: a first input coupled to the output of the primary processor; a second input coupled to the output of the secondary processor; and an output coupled to an input of the fault capture circuit.

7. The apparatus according to claim 1, wherein: The fault capture circuit includes a third D-type flip-flop having an input coupled to the output of the comparison circuit and an output coupled to the input of the first glitch absorbing device.

8. The apparatus according to claim 1, wherein: The fault capture circuit and the first glitch absorption device are arranged directly adjacent to each other in a layout of a dual-core lockstep system including the primary processor and the secondary processor.

9. The apparatus according to claim 1, further comprising: The second burr absorbing device is connected in series with the first burr absorbing device.

10. A method for burr absorption, comprising: placing a first glitch absorption device at an end of a fault signal path of the dual-core lockstep system before the fault signal is sent to a global fault collection system, wherein the dual-core lockstep system and the global fault collection system have different clock signals and reset signals; as well as absorbing, by the first burr absorbing device, burrs fed into the first burr absorbing device; wherein the first glitch absorption device comprises a first D-type flip-flop having an output coupled to an input of a fault collector of the global fault collection system; The dual-core lockstep system comprises: a comparison circuit configured to generate a fault signal; a fault capture circuit configured to receive a first clock signal and a delayed first reset signal and capture the fault signal generated by the comparison circuit; and The first glitch absorbing device is configured to receive the first clock signal and the delayed first reset signal, and absorb the glitch fed into the first glitch absorbing device.

11. The method according to claim 10, further comprising: A second burr absorbing device is placed in series with the first burr absorbing device.

12. The method according to claim 10, wherein the dual-core lockstep system further comprises: a main processor and a sub-processor configured to receive the first clock signal, the first reset signal, and a plurality of input signals, and to perform the same operation as each other based on the first clock signal, the first reset signal, and the plurality of input signals; and The comparison circuit is further configured to receive an output signal of the main processor and an output signal of the auxiliary processor.

13. The method according to claim 12, further comprising: comparing the output signal of the main processor with the output signal of the auxiliary processor by the comparison circuit; as well as Based on a comparison result of the step of comparing the output signal of the main processor with the output signal of the auxiliary processor, it is detected whether the output signal of the main processor matches the output signal of the auxiliary processor.

14. The method according to claim 12, wherein: The fault capture circuit includes a second D-type flip-flop.

15. The method of claim 12, wherein: The fault capture circuit includes a third D-type flip-flop having an input coupled to the output of the comparison circuit and an output coupled to the input of the first glitch absorbing device.

16. A burr absorption system comprising: a glitch absorbing device configured to absorb glitches on the fault signal, the glitch absorbing device being placed at an end of a fault signal path in the local fault collector circuit before the fault signal is sent to the global fault collector circuit; a main processor and a sub-processor configured to receive a clock signal, a reset signal, and a plurality of input signals, and to perform the same operation as each other based on the clock signal, the reset signal, and the plurality of input signals; a comparison circuit configured to receive an output signal of the main processor and an output signal of the auxiliary processor, and detect whether the output signal of the main processor matches the output signal of the auxiliary processor based on the output signals; as well as a fault capture circuit configured to receive the clock signal and the delayed reset signal and capture a fault signal generated by the comparison circuit; as well as The glitch absorbing device includes a first D-type flip-flop having an input coupled to an output of the fault capture circuit and an output coupled to an input of the fault collector circuit.

17. The system of claim 16, wherein: The local fault collector circuit and the global fault collector circuit have different clock signals and reset signals.

18. The system of claim 16, further comprising: The fault capture circuit is coupled between the comparison circuit and the glitch absorption device.

19. The system of claim 18, wherein: the global fault collector circuit comprising a fault collector circuit coupled to an output of the glitch absorption device, and wherein the fault collector circuit comprises a second D-type flip-flop; and The fault capture circuit includes a third D-type flip-flop having an input coupled to the output of the comparison circuit and an output coupled to the input of the glitch absorption device.

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