Data pre-fetching method and device for reducing direct memory access processing delay
The data prefetching method addresses DMA processing delays by concurrent memory access and connection path establishment, enhancing data transmission efficiency in high-performance computer systems.
Patent Information
- Application Number
- CN202210550076.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-20
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2042-05-20
AI Technical Summary
The delay in direct memory access (DMA) processing in high-performance computer systems, particularly through the PCIE interface, hinders efficient data transmission between nodes, leading to suboptimal communication efficiency.
A data prefetching method that initiates memory data access concurrently with establishing the data connection path, setting a prefetch threshold to manage the number of data blocks, and discarding prefetched data if the connection fails, ensuring efficient data transmission.
Reduces latency and improves communication efficiency by hiding memory access delays within the connection path establishment process, optimizing data acquisition and reducing transmission delays between nodes.
Smart Images
Figure CN114817088B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of high performance computing in-chip data pre-fetching technology, and specifically relates to a data pre-fetching method and device for reducing direct memory access (DMA) processing delay, which is used to reduce the delay of data processing transactions by sending a memory data read request to a PCIE interface in advance. Background Art
[0002] As the computing speed of high-performance computer systems (HPC) continues to increase from petascale to exascale, the amount of data that microprocessor chips and interconnected network chips need to process is increasing exponentially. Therefore, how to process more data in a shorter time is a huge challenge faced in the current research process of high-performance computer systems.
[0003] In high-performance computer systems, a massive amount of data needs to be transmitted between thousands of computing nodes. For data transmission between any two nodes, the typical Remote Direct Memory Access (RDMA) processing flow includes: first, a data connection path is established between the source node and the destination node to prepare for network transmission; second, the network interface chip on the source node submits a memory data access request to the source node through the PCIE interface; then, the source node sends the corresponding memory data to the network interface chip through the PCIE interface; finally, the network interface chip processes the data and sends it to the interconnected network of the entire system through the network port, and finally reaches the destination computing node through the established data connection path. However, since the delay of accessing memory data through the PCIE interface accounts for a large proportion of the total delay of the entire data transmission process, if the above process is executed completely serially, it will not be able to achieve a high data transmission efficiency. Summary of the invention
[0004] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a data prefetching method and device for reducing the processing delay of direct memory access are provided. The present invention aims to optimize the data acquisition process of direct memory access, reduce the data transmission delay between any two nodes, and improve the efficiency of the processing process, thereby improving the communication efficiency of the entire system.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0006] A data prefetching method for reducing direct memory access processing latency, comprising:
[0007] 1) After receiving the descriptor of the RDMA transaction, when starting the process of establishing the data connection path between the source node and the destination node according to the descriptor, the process of prefetching the data block is started at the same time to prefetch the memory data required by the current RDMA transaction;
[0008] 2) Execute the message processing sub-process: If the data connection path is successfully established, all memory data of the current RDMA transaction including the pre-fetched memory data are sent to the destination node.
[0009] Optionally, when the process of starting the data block pre-fetch request in step 1), the number of data blocks that need to be pre-fetched does not exceed a preset pre-fetch threshold N.
[0010] Optionally, the size of the pre-fetch threshold N is the number of data blocks that can be cached in the response data buffer of the network interface chip of the source node.
[0011] Optionally, the process of starting the data block pre-fetch request in step 1) includes:
[0012] 1.1A) Send a data block pre-fetch request to the PCIE bus;
[0013] 1.2A) Determine whether the current RDMA transaction still has data blocks that need to be pre-fetched. If so, jump to the next step; otherwise, this process ends;
[0014] 1.3A) Determine whether the number of data block pre-fetch requests issued is equal to the pre-fetch threshold N. If so, the process ends. Otherwise, jump to step 1.1A) to continue sending the next data block pre-fetch request.
[0015] Optionally, when the data connection path is successfully established in step 1), it further includes determining whether the current RDMA transaction still has data blocks for which a data block prefetch request has not been issued, and if there are still data blocks for which a data block prefetch request has not been issued, a process of executing a data block request for the data blocks for which a data block prefetch request has not been issued:
[0016] 1.1B) Send a data block request to the PCIE bus;
[0017] 1.2B) Determine whether the current RDMA transaction still has data blocks to be requested. If so, jump to step 1.1B); otherwise, this process ends.
[0018] Optionally, when executing the message processing sub-process in step 2), it also includes the steps of discarding the pre-fetched data returned by the start data block pre-fetch request, canceling the current RDMA transaction, and ending and exiting when the data connection path fails to be established.
[0019] Optionally, when executing the message processing sub-process in step 2), sending all memory data of the current RDMA transaction including the pre-fetched memory data to the destination node includes:
[0020] 2.1) Determine whether a sufficient amount of memory data of the current RDMA transaction has been received. If a sufficient amount of data of the current RDMA transaction has been received, jump to the next step; otherwise, jump to and re-execute step 2.1) and continue waiting;
[0021] 2.2) Encapsulate the memory data of the current RDMA transaction into a message and send it to the destination node through the established data connection path;
[0022] 2.3) Determine whether the message of the current RDMA transaction has been sent. If not, jump to step 2.1); otherwise, end the message processing sub-process and exit.
[0023] In addition, the present invention also provides a data prefetching device for reducing direct memory access processing delay, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is connected to a network interface chip, and the microprocessor is programmed or configured to execute the steps of the aforementioned data prefetching method for reducing direct memory access processing delay.
[0024] In addition, the present invention also provides a high-performance computer system, comprising a plurality of computer nodes interconnected via a network, the computer nodes comprising interconnected microprocessors and memories, the microprocessors being connected to a network interface chip, and the microprocessors being programmed or configured to execute the steps of the aforementioned data prefetching method for reducing direct memory access processing delay.
[0025] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is used to be executed by a microprocessor to implement the steps of the aforementioned data prefetching method for reducing direct memory access processing delay.
[0026] Compared with the prior art, the present invention mainly has the following advantages: 1. Low latency. By hiding the memory data access process in the process of establishing the data connection path, the RDMA transaction processing delay of the two nodes is reduced; 2. The prefetch mechanism does not incur additional costs. The prefetch mechanism simply executes the memory data request operation in advance without adding additional costs. Even if the data connection path fails to be established, the prefetched returned data only needs to be discarded. In short, the present invention can reduce the data transmission delay between any two nodes and improve the efficiency of the processing flow by optimizing the data acquisition process of direct memory access, thereby improving the communication efficiency of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention. DETAILED DESCRIPTION
[0028] See also Figure 1 , the data prefetching method for reducing direct memory access processing delay in this embodiment includes:
[0029] 1) After receiving the descriptor of the RDMA transaction (used to start the RDMA transaction transmission process), when starting the process of establishing the data connection path between the source node and the destination node according to the descriptor, the process of data block prefetching request is started at the same time to prefetch the memory data required by the current RDMA transaction;
[0030] 2) Execute the message processing sub-process: If the data connection path is successfully established, all memory data of the current RDMA transaction including the pre-fetched memory data are sent to the destination node.
[0031] The network interface chip obtains the descriptor of the current RDMA transaction from the software. The descriptor contains the identifier, operation type, address, length and other information used by the current transaction to obtain and send data. After obtaining the descriptor information, the data connection path establishment process with the destination node is started. The data connection path establishment process needs to be completed by communicating with the destination node. This process will last for a period of time, and the data connection path may fail to be established due to errors or unavailable resources. The data to be processed by the current transaction needs to be obtained from the memory through the PCIE interface and sent to the destination node through the network port after the data connection path is successfully established. The current descriptor sends a memory data read request to the PCIE interface. Usually, the memory data request of a descriptor may be split into multiple requests to adapt to the processing logic of the PCIE interface, thereby improving data processing efficiency. After each data request is responded to, the corresponding memory data is sequentially returned to the network interface chip through the PCIE interface and waits to be sent through the network port. Since data can only be sent after the data connection path is successfully established, the most direct way is to wait for the data connection path to be successfully established before starting to send data requests to the PCIE, but this method has a large delay. The purpose of the present invention is to optimize the data transmission process, reduce the data transmission delay between any two nodes, improve the efficiency of the processing flow, and thus improve the data transmission performance of the entire system. This embodiment proposes a data pre-fetching method, which advances the process of the network interface chip obtaining memory data through PCIE to the same time as the data connection path establishment process, rather than starting the memory data access process after the data connection path establishment process is completed. The purpose is to hide the memory data access process in the data connection path establishment process, thereby reducing the data transmission delay between the two nodes.
[0032] This embodiment directly sends a data request to PCIE after obtaining the descriptor information, without waiting for the data connection path establishment process to be completed. Since the amount of memory data that needs to be read by the RDMA transaction represented by a descriptor is usually large, the memory data request of an RDMA transaction is generally split into multiple requests to adapt to the data processing granularity of the PCIE interface. In this embodiment, when the process of starting the data block prefetch request in step 1), the number of data blocks that need to be prefetched does not exceed the preset prefetch threshold N. Note that the number of PCIE data requests for an RDMA transaction is n times in total, and a prefetch threshold N is set. If n>N, only N PCIE data prefetch requests are submitted before the data connection path is established, and the remaining nN data requests are not prefetched; if n≤N, all n PCIE data requests are submitted for prefetching.
[0033] In this embodiment, the pre-fetch threshold N is the number of data blocks that can be cached in the response data buffer of the network interface chip of the source node. After the data corresponding to N requests are returned from the memory, the response data buffer of the network interface chip can just fill up.
[0034] In this embodiment, the process of starting the data block pre-fetch request in step 1) includes:
[0035] 1.1A) Send a data block pre-fetch request to the PCIE bus;
[0036] 1.2A) Determine whether the current RDMA transaction still has data blocks that need to be pre-fetched. If so, jump to the next step; otherwise, this process ends;
[0037] 1.3A) Determine whether the number of data block pre-fetch requests issued is equal to the pre-fetch threshold N. If so, the process ends. Otherwise, jump to step 1.1A) to continue sending the next data block pre-fetch request.
[0038] In this embodiment, when the data connection path is successfully established in step 1), it also includes determining whether the current RDMA transaction still has data blocks for which a data block prefetch request has not been issued. If there are still data blocks for which a data block prefetch request has not been issued, a process of executing a data block request for the data blocks for which a data block prefetch request has not been issued:
[0039] 1.1B) Send a data block request to the PCIE bus;
[0040] 1.2B) Determine whether the current RDMA transaction still has data blocks to be requested. If so, jump to step 1.1B); otherwise, this process ends.
[0041] In this embodiment, when executing the message processing sub-process in step 2), it also includes the steps of discarding the pre-fetched data returned by the start data block pre-fetch request, canceling the current RDMA transaction, and ending and exiting when the data connection path fails to be established.
[0042] In this embodiment, when executing the message processing sub-process in step 2), sending all memory data of the current RDMA transaction including the pre-fetched memory data to the destination node includes:
[0043] 2.1) Determine whether a sufficient amount of memory data of the current RDMA transaction has been received. If a sufficient amount of data of the current RDMA transaction has been received, jump to the next step; otherwise, jump to and re-execute step 2.1) and continue waiting;
[0044] 2.2) Encapsulate the memory data of the current RDMA transaction into a message and send it to the destination node through the established data connection path;
[0045] 2.3) Determine whether the message of the current RDMA transaction has been sent. If not, jump to step 2.1); otherwise, end the message processing sub-process and exit.
[0046] If a signal indicating that the data connection path is established is received during the process of submitting the prefetch descriptor, subsequent processing of the received data will begin: if the data connection path is established successfully, the received memory data will be encapsulated into multiple network messages according to the message format definition, and then sent out through the network port, and finally arrive at the corresponding memory space of the destination node; if the data connection path fails to be established, the received memory data will be discarded and the processing of the RDMA transaction will be terminated.
[0047] In addition, this embodiment also provides a data prefetching device for reducing direct memory access processing delay, including a microprocessor and a memory connected to each other, the microprocessor is connected to a network interface chip, and the microprocessor is programmed or configured to execute the steps of the aforementioned data prefetching method for reducing direct memory access processing delay.
[0048] In addition, this embodiment also provides a high-performance computer system, including multiple computer nodes interconnected through a network, the computer nodes include interconnected microprocessors and memories, the microprocessors are connected to a network interface chip, and the microprocessors are programmed or configured to execute the steps of the aforementioned data prefetching method for reducing direct memory access processing delay.
[0049] In addition, this embodiment further provides a computer-readable storage medium, in which a computer program is stored. The computer program is used to be executed by a microprocessor to implement the steps of the aforementioned data prefetching method for reducing direct memory access processing delay.
[0050] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data prefetching device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data prefetching device generate instructions for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data pre-fetching device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data pre-fetching device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0051] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.
Claims
1. A data prefetching method for reducing direct memory access processing delay, characterized in that: include: 1) After receiving the descriptor of the RDMA transaction, when starting the process of establishing the data connection path between the source node and the destination node according to the descriptor, the process of prefetching the data block is started at the same time to prefetch the memory data required by the current RDMA transaction; 2) Execute the message processing sub-process: If the data connection path is successfully established, all memory data of the current RDMA transaction including the pre-fetched memory data are sent to the destination node; The process of initiating a data block prefetch request in step 1) includes: 1.1A) Send a data block prefetch request to the PCIE bus; 1.2A) Determine whether the current RDMA transaction still has data blocks that need to be pre-fetched. If so, jump to the next step; otherwise, this process ends; 1.3A) Determine that the number of data block prefetch requests issued is equal to the prefetch threshold N Is it true? If so, the process ends. Otherwise, jump to step 1.1A) to continue sending the next data block prefetch request; When the data connection path is successfully established in step 1), it also includes determining whether the current RDMA transaction still has data blocks for which a data block prefetch request has not been issued. If there are still data blocks for which a data block prefetch request has not been issued, a process of executing a data block request for the data blocks for which a data block prefetch request has not been issued: 1.1B) Send a data block request to the PCIE bus; 1.2B) Determine whether the current RDMA transaction still has data blocks to be requested. If so, jump to step 1.1B); otherwise, this process ends.
2. The data prefetching method for reducing direct memory access processing delay according to claim 1, characterized in that: When the data block prefetch request process is initiated in step 1), the number of data blocks to be prefetched does not exceed the preset prefetch threshold. N .
3. The data prefetching method for reducing direct memory access processing delay according to claim 2, characterized in that: The prefetch threshold N The size is the number of data blocks that can be cached by the response data buffer of the network interface chip of the source node.
4. The data prefetching method for reducing direct memory access processing delay according to claim 1, characterized in that: When executing the message processing sub-process in step 2), it also includes the steps of discarding the pre-fetched data returned by the start data block pre-fetch request, canceling the current RDMA transaction, and ending and exiting when the data connection path fails to be established.
5. The data pre-fetching method for reducing direct memory access processing delay according to claim 4, characterized in that: When executing the message processing sub-process in step 2), all memory data of the current RDMA transaction including the pre-fetched memory data is sent to the destination node including: 2.1) Determine whether a sufficient amount of memory data of the current RDMA transaction has been received. If a sufficient amount of memory data of the current RDMA transaction has been received, jump to the next step; otherwise, jump to and re-execute step 2.1) and continue waiting; 2.2) Encapsulate the memory data of the current RDMA transaction into a message and send it to the destination node through the established data connection path; 2.3) Determine whether the message of the current RDMA transaction has been sent. If not, jump to step 2.1); otherwise, end the message processing sub-process and exit.
6. A data pre-fetching device for reducing direct memory access processing delay, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is connected to a network interface chip, characterized in that: The microprocessor is programmed or configured to execute the steps of the data prefetching method for reducing direct memory access processing delay as recited in any one of claims 1 to 5.
7. A high-performance computer system, comprising a plurality of computer nodes interconnected via a network, wherein the computer nodes comprise interconnected microprocessors and memories, wherein the microprocessors are connected to a network interface chip, characterized in that: The microprocessor is programmed or configured to execute the steps of the data prefetching method for reducing direct memory access processing delay as recited in any one of claims 1 to 5.
8. A computer-readable storage medium having a computer program stored therein, characterized in that: The computer program is used to be executed by a microprocessor to implement the steps of the data prefetching method for reducing direct memory access processing delay as described in any one of claims 1 to 5.