A method for characterizing the characteristics of a SiP process reliability evaluation test carrier

Abstract

A method for characterizing a test carrier for evaluating the reliability of a SiP process, which analyzes the key processes of SiP products through PFMECA and analyzes the key structures according to risk factors, thereby determining the process domain that the test carrier needs to include, and then determining the value of the test carrier's characteristic characterization parameters based on a failure physics method or a qualitative analysis method. By manufacturing a test carrier for verifying the SiP production process, instead of the SiP samples used for assessment and verification, the cost of producing SiP samples that are far greater than the demand can be reduced, thereby reducing the cost of SiP products.

Description

Technical Field

[0001] The invention relates to a method for characterizing characteristics of a SiP process reliability evaluation test carrier, and belongs to the technical field of SiP product reliability evaluation. Background Art

[0002] SiP products use a variety of advanced packaging processes, including thin / thick film substrate technology, multi-chip packaging technology, tube and shell design and production technology, etc. In order to solve the problems of traditional integrated circuit assurance standards and inspection schemes not making standardized requirements for new factors brought by advanced packaging processes, the introduction of new failure modes and unclear failure mechanisms, and the difficulty in directly detecting internal defects in high-density packaging, it is necessary to conduct in-depth research on the reliability evaluation technology of SiP products.

[0003] To achieve improved functionality and performance, SiP products require integrating silicon-based integrated circuit chips of varying sizes, such as FPGAs, CPUs, DSPs, large-scale storage modules, and ASICs, along with discrete device chips and passive components, into a single package. A single SiP product can accomplish functions that previously could only be achieved by a single machine, resulting in relatively low customer demand. According to the current quality assurance plan, the majority of each batch of SiP products is used for assessment testing, resulting in far more samples being used for assessment testing than ordered by customers, dramatically increasing the cost of SiP products. To reduce the sample cost of SiP product assessment testing, a test vehicle that covers the process capabilities of SiP manufacturers can be designed to address this issue. However, a search revealed no patent documents related to the content of this patent application. Summary of the Invention

[0004] The technical problem solved by the present invention is: in view of the problem that the current existing technology lacks a method and technology that can reduce the sample cost of SiP product assessment tests, a characteristic characterization method of a SiP process reliability assessment test carrier is proposed.

[0005] The present invention solves the above technical problems by the following technical solutions:

[0006] A method for characterizing a SiP process reliability evaluation test carrier, comprising:

[0007] Analyze the SiP product manufacturing process;

[0008] Identify key processes based on process failure modes, effects and criticality analysis;

[0009] Based on the risk factors of key processes, determine the key structures, including key structures that can be quantitatively analyzed and key structures that cannot be quantitatively analyzed;

[0010] Design characteristic parameters of key structures that can be quantitatively analyzed through failure physics methods;

[0011] The characteristic characterization parameters of key structures that cannot be quantitatively analyzed are designed through qualitative analysis methods to complete the characteristic characterization.

[0012] The specific analysis process is as follows:

[0013] Determine the process flow for SiP product manufacturing and analyze the equipment, materials, process control parameters, technical indicators and inspection methods involved in the process flow.

[0014] The method for determining key processes is:

[0015] Based on the possible failure modes, causes, and impacts on SiP products in each process flow during the SiP product manufacturing process, the severity level of each failure mode, the probability level of each failure mode, and the difficulty level of detection of each failure mode are determined. The risk priority value of each failure mode is calculated by multiplication, and the key process of the SiP product is determined according to the size of the risk priority value.

[0016] The key processes include substrate manufacturing process, tube and shell manufacturing process, chip packaging process, passive components, wire manufacturing process and capping process. The key processes of SiP process products are determined through impact and hazard analysis.

[0017] Conduct risk factor analysis on key processes of SiP products and determine the key structure of the SiP evaluation test carrier, specifically:

[0018] The risk factors of substrate manufacturing process, chip packaging process, shell and tube manufacturing and capping process, and shell and tube manufacturing process are determined respectively, and the key structure is obtained by adjusting the manufacturing process design according to each risk factor.

[0019] Using the finite element simulation software COMSOL Multiphysics, a geometric model of the key structure was established, the failure mechanism of the key structure was analyzed, and corresponding environmental stress was applied to the geometric model. The stress conditions of the key structure were determined through simulation calculations. Based on the parameters of different key processes, different simulation results were obtained and the numerical values ​​of the quantitatively analyzable characteristic characterization parameters of the SiP evaluation test carrier were determined.

[0020] Based on the failure mode and failure mechanism, qualitative analysis is performed to determine the characteristic parameter values ​​of the SiP evaluation test carrier that cannot be quantitatively analyzed.

[0021] Key structures that can be quantitatively analyzed include substrate through-holes, substrate tile stacks, and bonding wires;

[0022] Critical structures that cannot be quantitatively analyzed include welding / bonding structures, tube shells and caps.

[0023] A characterization system for a SiP process reliability evaluation test carrier includes an analysis module, a key structure determination module, and a characterization parameter design module, wherein:

[0024] The analysis module analyzes the SiP product manufacturing process and determines the key processes based on process failure modes, impacts, and criticality analysis;

[0025] The critical structure determination module determines the critical structure based on the risk factors of the critical process;

[0026] The characteristic characterization parameter design module designs characteristic characterization parameters of key structures that can be quantitatively analyzed through failure physics methods, and designs characteristic characterization parameters of key structures that cannot be quantitatively analyzed through qualitative analysis methods.

[0027] In the analysis module, by determining the process flow of SiP product manufacturing, clarifying the process content and operating process procedures, analyzing the equipment, materials, process control parameters, technical indicators and inspection methods involved in the process flow, and targeting the failure modes, causes and impacts on SiP products that may occur in each process step during the SiP product manufacturing process, the severity level of each failure mode, the probability level of each failure mode, and the difficulty level of detection of each failure mode are determined, and the risk priority value of each failure mode is calculated by multiplication, and the key process of the SiP product is determined according to the size of the risk priority value.

[0028] In the key structure determination module, risk factor analysis is performed on the key processes of SiP products, and the risk factors of the substrate manufacturing process, the risk factors of the chip packaging process, the risk factors of the tube and shell manufacturing and capping process, and the risk factors of the tube and shell manufacturing process are determined respectively. The key structure is obtained by adjusting the manufacturing process design according to each risk factor.

[0029] Based on the failure mode and failure mechanism, qualitative analysis is performed to determine the characteristic parameter values ​​of the SiP evaluation test carrier that cannot be quantitatively analyzed.

[0030] The advantages of the present invention compared with the prior art are:

[0031] The present invention provides a method for characterizing the characteristics of a test carrier for evaluating the reliability of a SiP process. The method analyzes the key processes of the SiP product through PFMECA and analyzes the key structures based on risk factors, thereby determining the process domain that the test carrier needs to include. The characteristic characterization parameter values ​​of the test carrier are then determined based on the failure physics method or the qualitative analysis method. The method can manufacture a test carrier for verifying the SiP production process, replacing the SiP samples used for assessment and verification, so as to reduce the cost of producing SiP samples that far exceed the demand, thereby reducing the cost of SiP products. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flowchart of the implementation steps provided for the invention;

[0033] Figure 2 Schematic diagram of the packaging structure of the SiP product provided for the invention;

[0034] Figure 3 Schematic diagram of the geometric model of the substrate through hole provided for the invention;

[0035] Figure 4 Schematic diagram of the temperature cycle load applied to the through-hole of the substrate provided by the invention;

[0036] Figure 5 Schematic diagram of the 1 / 4 geometric model of the HTCC substrate provided for the invention;

[0037] Figure 6 A schematic diagram of the temperature change curve of cooling after high-temperature co-firing provided by the invention;

[0038] Figure 7 Schematic diagram of the mesh division results of the HTCC substrate model provided by the invention;

[0039] Figure 8 Schematic diagram of the warping of the HTCC substrate provided for the invention;

[0040] Figure 9 A schematic diagram of the first principal stress cloud diagram of the HTCC substrate provided by the invention;

[0041] Figure 10 Schematic diagram of a simplified geometric model of the bonding wire provided for the invention;

[0042] Figure 11 A schematic diagram of the power spectrum density of random vibrations applied to the bonding wire provided by the invention; DETAILED DESCRIPTION

[0043] A method for characterizing the characteristics of a SiP process reliability evaluation test carrier is provided. The method is capable of designing a SiP evaluation test carrier that can cover the process capabilities of a manufacturer. By manufacturing a test carrier for verifying the SiP production process, it replaces the SiP samples used for assessment and verification, thereby reducing the cost of producing SiP samples that far exceed the demand, thereby reducing the cost of SiP products.

[0044] The specific steps of the characterization method are as follows:

[0045] Step 1: SiP product manufacturing process analysis

[0046] Analyze the process flow of SiP product manufacturing, clarify the process content and operating procedures, and analyze the equipment, materials, process control parameters, technical indicators and inspection methods involved in the process;

[0047] Step 2: Determine key processes based on PFMECA

[0048] Assuming that the product design meets the requirements, the possible failure modes and causes of each process step in the SiP product production process and all their impacts on the SiP product are determined. The severity level (S), probability level (O) and detection difficulty level (D) of each process are determined. The risk priority number (RPN) value of the failure mode is calculated by multiplying the three. The key process of the SiP product is determined according to the size of the risk priority value.

[0049] The main process of SiP products includes substrate manufacturing, tube and shell manufacturing, chip packaging, passive device and wire manufacturing, and capping. Through PFMECA analysis, it is determined that the key processes of SiP products are thin / thick film substrate process, multi-chip packaging process, and tube and shell manufacturing process.

[0050] Step 3: Determine key structures based on key process risk factor analysis

[0051] Conduct risk factor analysis on SiP products' thick film substrate process, multi-chip packaging process, and tube and shell manufacturing process;

[0052] The risk factors of thick film substrate process include two parts: the first part is that when punching, filling through holes and printing conductive tapes on raw ceramic sheets, process defects such as punching deviation, poor through hole filling, broken conductive tape printing and interconnection often occur. Therefore, through holes and conductive tapes must be included in the design of the test carrier; the second part is that when the ceramic sheets prepared with through hole filling and conductive tapes are precisely stacked, isostatically laminated, cut into raw ceramics and low-temperature calcined into shape, as the number of ceramic sheet stacking layers increases, the risks of conductive tape deviation and misalignment caused by stacking, cracking of green sheets caused by lamination, and stress damage to substrates caused by cutting and calcining also gradually increase. Therefore, the number of ceramic sheet stacking layers must be considered in the design of the test carrier substrate;

[0053] The multi-chip packaging process is usually a mixed circuit assembly, including specific process flows such as dicing, mounting, bonding, capping and molding. The risk factors of the multi-chip packaging process include three parts: the first part is that the component welding process often leads to circuit failures such as short circuits and open circuits due to process stability issues. Therefore, the test carrier design needs to include at least one component welding process, and the welding materials used should include all welding materials used for SiP devices. The second part is the bonding strength, overflow size and environmental stability of chips of different sizes that may occur during the chip mounting process. Therefore, the test carrier design should include at least two chip bonding processes of different sizes, and the choice of patch glue should include all types used in existing SiPs. The third part is the device reliability problem caused by defects in the bonding process. The material and diameter of the bonding wire, the bonding distance, and the bonding point strength will affect the service life and application reliability of the device. Therefore, the test carrier design should include existing common bonding wire types, wire diameters and different bonding methods;

[0054] Shell and tube manufacturing and capping processes typically include double-sided or multi-cavity shell and tube design and airtight capping. Risk factors include the size and thickness of the cavity during shell and tube design, which may affect device reliability. Furthermore, during the hermetic packaging process, there are issues with voids and faults caused by weld frame contamination. Therefore, the test vehicle design must cover different shell and tube cavity designs and different capping processes.

[0055] Step 4: Design characteristic parameters of key structures based on failure physics methods

[0056] Based on the failure physics analysis of the failure mechanism of the key structure, a geometric model of the key structure is established in the finite element simulation software COMSOL Multiphysics. The environmental stress corresponding to the failure mechanism is applied to the geometric model, and the stress condition of the key structure is obtained through simulation calculation. The characteristic characterization parameter values ​​of the SiP evaluation test carrier are determined based on the simulation results of different design or process parameters.

[0057] For through-holes (THHs) on substrates, metal is plated on the walls of the holes to form an electrical connection between the internal and external circuits. When the temperature changes, due to the mismatch in the coefficient of thermal expansion (CTE) between the plating material and the substrate material in the thickness direction, cyclic stress will be generated in the through-hole plating, leading to thermal fatigue failure of the through-hole plating. Furthermore, the main factor affecting the life of the through-holes on the substrate is the ratio of the through-hole depth to the through-hole diameter. Therefore, a geometric model of the through-holes can be established in COMSOL Multiphysics, and temperature cycling loads can be set according to GJB548B. Through simulation, the Z-axial stress simulation results for different through-hole radii can be obtained. The through-hole radius that causes the maximum Z-axial stress within the SiP manufacturer's process capabilities is selected as the characteristic characterization parameter for the through-holes of the SiP test carrier.

[0058] For high-temperature co-fired HTCC ceramic substrates, the metallization slurry needs to be evenly printed on the ceramic green sheet by screen printing, and after drying, it is sintered in a reducing atmosphere at 1500-1600℃ to form a dense metal film layer, which effectively connects the ceramic and the metal. After high-temperature co-firing, the HTCC substrate will warp and have high residual stress, and the number of ceramic stacking layers on the substrate will affect the degree of substrate warping and the magnitude of residual stress. Therefore, a geometric model of the HTCC ceramic substrate can be established in COMSOL Multiphysics, and a sintering temperature curve with a uniform cooling rate of 10℃ / min from 1500℃ to 20℃ can be set. The maximum first principal stress (residual stress) σ1 and the maximum warpage deformation w (absolute value) of different ceramic stacking layers on the HTCC substrate can be obtained through simulation. According to the change law, a reasonable number of stacking layers is designed as the characteristic characterization parameter of the SiP test carrier ceramic substrate;

[0059] During transportation and use, bonding wires are subject to various stress environments, especially random vibration stress. The internal stress generated by random vibrations can cause the wires to break and fail. Therefore, a geometric model of the bonding wire can be established in COMSOL Multiphysics. Based on the actual working conditions of the bonding wire, random vibration excitation is applied to the contact surface between the first and second bonding points of the bonding wire and the pad. The first principal stress of the bonding wire at different bonding wire spans is obtained through simulation. Based on the variation pattern, a reasonable bonding wire span is designed as a characteristic parameter for the bonding wire of the SiP test carrier.

[0060] Step 5: Design characteristic characterization parameters of key structures that are difficult to quantitatively analyze based on qualitative analysis methods. For key structures that cannot be quantitatively analyzed using failure physics methods, qualitative analysis can be performed based on their failure modes and failure mechanisms to determine the characteristic characterization parameter values ​​of the SiP evaluation test vehicle.

[0061] For chip bonding structures, some bubbles will inevitably appear at the bonding interface during the conductive adhesive bonding process. Under the action of moist heat load and temperature shock, these bubbles will cause stress concentration, greatly reducing the thermal fatigue life of electronic devices and accelerating the destruction and failure of electronic devices. In the conductive adhesive bonding process, the larger the chip size, the greater the probability of pores appearing at the conductive adhesive bonding interface, and its reliability will be lower. Therefore, according to the process capabilities of the SiP manufacturer, a reasonable chip size is set as a characteristic characterization parameter of the SiP test carrier chip bonding structure;

[0062] For the shell and tube structure, since the shell and tube itself and the capping process have fewer steps and the failure mode is less critical, the design of the shell and tube cap of the SiP test carrier should be within the manufacturer's process capabilities and be sufficient to support the chips and capacitors inside the cavity, reflecting the reliability of the processing technology.

[0063] A characterization system is proposed, which includes an analysis module, a key structure determination module, and a characterization parameter design module, wherein:

[0064] The analysis module analyzes the SiP product manufacturing process and determines the key processes based on process failure modes, impacts, and criticality analysis;

[0065] The critical structure determination module determines the critical structure based on the risk factors of the critical process;

[0066] The characteristic characterization parameter design module designs characteristic characterization parameters of key structures that can be quantitatively analyzed using failure physics methods, and designs characteristic characterization parameters of key structures that cannot be quantitatively analyzed using qualitative analysis methods;

[0067] In the analysis module, by determining the process flow of SiP product manufacturing, clarifying the process content and operating process procedures, analyzing the equipment, materials, process control parameters, technical indicators and inspection methods involved in the process flow, and focusing on the possible failure modes, causes and impacts on SiP products in each process step during the SiP product manufacturing process, the severity level of each failure mode, the probability level of each failure mode, and the difficulty level of each failure mode being detected are determined. The risk priority value of each failure mode is calculated by multiplication, and the key process of the SiP product is determined according to the size of the risk priority value;

[0068] In the key structure determination module, risk factor analysis is conducted on the key processes of SiP products, and the risk factors of thick film substrate manufacturing process, chip packaging process, tube and shell manufacturing and capping process, and tube and shell manufacturing process are determined respectively. Based on each risk factor, the manufacturing process design is adjusted to obtain the key structure;

[0069] Using the finite element simulation software COMSOL Multiphysics, we established geometric models of key structures, analyzed their failure mechanisms, and applied corresponding environmental stresses to the geometric models. Simulations were then used to determine the stress conditions of the key structures. Based on the parameters of different key processes, we obtained different simulation results and determined the numerical values ​​of the quantitatively analyzable characteristic parameters of the SiP evaluation test vehicle.

[0070] At the same time, qualitative analysis is performed based on the failure mode and failure mechanism to determine the characteristic characterization parameter values ​​of the SiP evaluation test carrier that cannot be quantitatively analyzed.

[0071] The following is further described based on specific embodiments:

[0072] In the current embodiment, the characterization method steps of the SiP evaluation test carrier are as follows: Figure 1 As shown, the details are as follows:

[0073] Step 1: SiP product manufacturing process analysis

[0074] A typical SiP product from a manufacturer was selected as a case study for manufacturing process analysis. The packaging structure of the SiP product is as follows: Figure 2 As shown, ① is the HTCC (high temperature co-fired ceramic) integrated tube shell, ② is the high temperature conductive adhesive, ③ is the chip installed in the cavity, ④ is the alloy cover, ⑤ is the gold wire, ⑥ is the low temperature conductive adhesive, ⑦ is the flat seam cover, ⑧ is the bottom filling adhesive, and ⑨ is the capacitor. The process flow of this typical SiP product is as follows:

[0075] (1) Use HTCC (high temperature co-fired ceramic technology) to manufacture the packaged integrated tube shell. The main process flow of manufacturing HTCC integrated tube shell is as follows: first, punch the raw ceramic sheet, then use the conductive paste to fill the through hole, then use the thick film process to print the passive components and wires, then make the core cavity, then stack multiple raw ceramic sheets in sequence, then isostatically press them, then cut off the excess parts, and finally sinter at high temperature. In addition, the received wafers must be thinned and diced to obtain the chip to be assembled;

[0076] (2) Before assembly, the shell and tube are pre-baked, and then the upper cavity is encapsulated, including conductive adhesive bonding and gold wire bonding between the chip and the shell and finally the upper cavity is capped by fusion welding;

[0077] (3) Encapsulation of the lower cavity, including conductive adhesive bonding and gold wire bonding between the chip, capacitor and tube shell, and finally capping of the lower cavity by parallel seam welding;

[0078] Step 2: Determine key processes based on PFMECA

[0079] PFMECA was conducted on SiP products, and the critical processes of SiP products were identified based on the risk priority values. The top 20% of RPN values ​​were selected as the RPN critical value, that is, the process with RPN ≥ 80 was selected. The specific results are shown in Table 1:

[0080] Table 1 Processes where RPN values ​​exceed critical values

[0081]

[0082]

[0083]

[0084]

[0085] Through PFMECA analysis, it can be determined that the key processes of SiP products are thin / thick film substrate process, multi-chip packaging process and tube and shell manufacturing process;

[0086] Step 3: Determine key structures based on key process risk factor analysis

[0087] A risk factor analysis was conducted on the thick-film substrate process, multi-chip packaging process, and tube and shell manufacturing process of typical SiP products. Based on the analysis results, the key structures that should be considered in the test evaluation carrier are determined to be: substrate through-holes and guide strips, substrate tile stacking, component welding structure, chip bonding structure, bonding wires, tube and shell, and different capping processes;

[0088] Step 4: Design characteristic parameters of key structures based on failure physics methods

[0089] The characteristic characterization parameter design based on the failure physics method is carried out for the through hole of the substrate, the tile stack of the substrate, and the bonding wire respectively:

[0090] (1) Through hole in substrate

[0091] Electroplating metal on the walls of substrate through-holes creates an electrical connection between internal and external circuits. When the temperature changes, the mismatch in the coefficient of thermal expansion (CTE) between the plating material and the substrate material in the thickness direction causes cyclic stress in the through-hole plating, leading to thermal fatigue failure of the through-hole plating. Furthermore, the main factor affecting the life of substrate through-holes is the ratio of through-hole depth to through-hole diameter.

[0092] The diameter of the through hole on the substrate of a manufacturer's SiP product is 75μm, the maximum depth is 3.25mm, and the filling slurry is tungsten slurry. The finite element simulation software COMSOL Multiphysics is used to establish a two-dimensional axisymmetric model of the substrate through hole. The established model is as follows Figure 3 As shown in the figure, the left rectangle represents the through-hole in the substrate, and the right rectangle represents the HTCC ceramic substrate. Due to the symmetry of the through-hole in the substrate, the upper half of the through-hole can be selected along the center of the substrate thickness for modeling and analysis to reduce the amount of calculation and computation time. At the same time, displacement constraints are applied at the symmetry plane to avoid under-constrained models that may result in incorrect results.

[0093] According to the temperature cycle test conditions in GJB548B, the finite element simulation boundary conditions of the substrate through hole are set, and the temperature cycle load is as follows: Figure 4The lowest temperature is -65℃, the highest temperature is 150℃, the high and low temperature conversion time is 1min, the high and low temperature holding time is 10min, and the temperature cycle time is 22min.

[0094] Taking different through-hole radii r0, which are 0.02, 0.0225, 0.025, 0.0275, 0.03, 0.0325, 0.035, 0.0375 and 0.04, respectively, all in mm, parametric scanning is performed to obtain the Z-axial stress of the through-hole at high and low temperatures as shown in Table 2:

[0095] Table 2 Maximum Z-axial stress at high and low temperatures for through holes with different radii

[0096]

[0097]

[0098] As can be seen from the table above, the smaller the via radius, the greater the cyclic stress generated inside the via under temperature cycling, and the lower the via reliability under the same conditions. When designing a SiP evaluation test vehicle, it is necessary to consider the impact of the via radius on substrate reliability. The substrate via diameter of the SiP product is 75μm, which is also the smallest via diameter among substrate manufacturers. Therefore, the substrate via diameter of the SiP evaluation test vehicle should be designed to be 75μm.

[0099] (2) Number of substrate tile stacking layers

[0100] The manufacturing process of high-temperature co-fired HTCC ceramic substrates involves evenly screen-printing a metallization slurry onto a ceramic green sheet. After drying, the substrate is sintered in a reducing atmosphere at 1500-1600°C to form a dense metal film layer, effectively connecting the ceramic and the metal. After high-temperature co-firing, the substrate cools from a high temperature of over 1500°C to room temperature around 20°C. The HTCC substrate will warp and exhibit high residual stress. The number of ceramic layers stacked on the substrate will affect the degree of substrate warpage and the amount of residual stress.

[0101] The substrate used in a certain manufacturer's SiP product is a high-temperature co-fired HTCC ceramic, with 90% alumina. The number of ceramic layers is 13, and the substrate size is 32×32×3.25mm. The thickness of each conductor layer and dielectric layer is 0.1mm and 0.15mm respectively. The 1 / 4 substrate model established using the finite element simulation software COMSOL Multiphysics is as follows: Figure 5 The conductor layer and dielectric layer in the substrate are made of tungsten and alumina ceramics respectively, and the material parameters are shown in Table 3:

[0102] Table 3 Material properties of substrate conductor layer and dielectric layer

[0103]

[0104] The HTCC substrate was cooled at a constant rate of 10°C / min from 1500°C to room temperature of 20°C. The temperature change diagram is shown in the figure below. Figure 6 Assume that the high temperature co-firing process is in good condition and the connection between the conductor layer and the dielectric layer of the substrate is defect-free.

[0105] Since ceramics are brittle materials, the main focus is on the first principal stress, which is expressed as:

[0106] σ1=σ max

[0107] Where σ1 is the first principal stress, σ max It is the maximum normal stress on three pairs of mutually perpendicular principal planes on the principal stress element, which can be directly obtained from the finite element analysis results of COMSOL Multiphysics;

[0108] The 1 / 4 model of the HTCC substrate with 13 layers of tiles is divided into meshes as follows Figure 7 As shown in the figure, the bottom surface is meshed with free quadrilaterals to obtain 324 units, and then the entire model is meshed with swept meshes to obtain a mesh model with 16,848 units. The finite element analysis results show that the stress cloud distribution and warpage deformation of ceramic substrates with different numbers of layers are basically the same after cooling from 1500°C to 20°C, with only the stress value and deformation being different. Taking the 1 / 4 model of the HTCC substrate with 13 layers of ceramic stacking as an example, its warpage deformation is shown in the figure below. Figure 8 The results show that the warping deformation of the ceramic substrate becomes more and more obvious as the distance from the center point increases during the cooling process, and the warping deformation reaches the maximum at the edge. The stress cloud diagram is shown in Figure 9 As shown, the maximum value of the first principal stress is located at the junction of the conductor layer and the dielectric layer at the top edge.

[0109] Taking the number of HTCC ceramic substrate stacking layers as a variable, a parametric sweep was performed to simulate and calculate the maximum first principal stress (residual stress) σ1 and the maximum warpage deformation w (absolute value) of HTCC substrates with 13 to 22 layers. The results are shown in Table 4.

[0110] Table 4 Maximum first principal stress and maximum warpage of substrates with different numbers of tile layers

[0111]

[0112] From the results of the parametric scan, it can be seen that as the number of tile stacking layers increases, the residual stress of the HTCC substrate gradually increases, but the increase is not large, while the warping of the substrate first decreases and then increases. According to the variation law of the warping deformation between 17 and 22 layers, the warping deformation of the HTCC substrate will increase faster and faster as the number of stacking layers continues to increase. When designing the SiP evaluation test carrier, the warping deformation of the HTCC substrate can be used as a characteristic representation. On the basis of the SiP product, a 20% redundancy is designed so that the warping deformation of the HTCC substrate of the SiP evaluation test carrier is increased to at least 0.0635mm. After simulation calculation, when the number of tile stacking layers is 28, the warping deformation of the HTCC substrate is 0.06389mm, which can meet the requirements;

[0113] (3) Bonding wire

[0114] Bond wires are subject to various stresses during transportation and use, particularly random vibration. The internal stress generated by random vibration can lead to wire fracture and failure. Without considering factors such as bond strength, carbonization, and corrosion, the primary failure modes for bond wires are brittle fracture and fatigue fracture, typically occurring at the neck of the solder joint. Brittle fracture occurs when stress exceeds the strength limit of the bond wire material; fatigue fracture occurs when energy from factors such as temperature and vibration accumulates over a period of time, exceeding a certain limit and causing the bond wire to yield and fatigue. Of these two stresses, the stress that causes fatigue fracture is much lower than that that causes brittle fracture. When designing a carrier for SiP evaluation, comprehensive consideration of the bond wire diameter, material, and bonding method is required, with simulations primarily focused on the bond wire span.

[0115] In a typical SiP product from a certain manufacturer, the chips are interconnected using wire bonding. The diameters of the bonding wires are 20μm and 30μm, and the bonding method used is gold ball bonding. The maximum spans are 1.51mm and 1.55mm, respectively. To improve modeling efficiency, the complex external shape of the bonding wire is ignored and replaced with a simple geometric shape. The gold ball bonding wire bonding model is established as follows: Figure 10 Assume that the first and second solder joints of the gold ball bond are aligned with the pad, the arch height is set to 0.15 mm, and the span L is the distance between the first and second solder joints. Table 5 lists the material parameters of the gold bonding wire.

[0116] Table 5 Bonding wire material parameters

[0117]

[0118] According to the actual working conditions of the bonding wire, random vibration excitation is applied to the contact surface between the first and second bonding points of the bonding wire and the pad. By comparing the vibration and response of the same magnitude in each direction, it is found that the vibration perpendicular to the plane where the bonding wire is located (xz plane) produces the largest response, so the vibration excitation direction is set to the y direction perpendicular to the xz plane. According to GJB 548B "Test Methods and Procedures for Microelectronic Devices", the following is designed: Figure 11 The vibration simulation excitation spectrum shown in the figure shows that the random vibration power spectral density (PSD) is 10N² / Hz at 50Hz, increases to 40N² / Hz at 100Hz, remains at 40N² / Hz from 100 to 1000Hz, and decreases to 10N² / Hz at 2000Hz.

[0119] Since random vibration PSD is the statistical value of vibration in the frequency domain, the vibration stress on the bonding wire should also be a statistical value. The stress statistical value can be calculated using the root mean square function to characterize the response of the bonding wire under random vibration.

[0120] For the finite element model of the bonding wire, only the span L of the bonding wire is changed and the same PSD is applied to obtain the root mean square value σ of the first principal stress of the bonding wire with different spans. 1rms As shown in Table 6:

[0121] Table 6 RMS value of the first principal stress of bonding wires with different spans

[0122]

[0123] Simulation results show that as the bond wire span increases, the first principal stress of the bond wire vibration stress also increases. In SiP products, the bond wire span is 1.51mm, and the vibration stress is 0.0562MPa. Based on this, a 20% redundancy is designed for the SiP evaluation test vehicle. The vibration stress of the bond wire in the test vehicle should be 0.06744MPa. Based on the calculation results, the bond wire span in the SiP evaluation test vehicle can be designed to be 1.52mm.

[0124] Step 5: Design characteristic characterization parameters of key structures that are difficult to quantitatively analyze based on qualitative analysis methods. Carry out characteristic characterization parameter design based on qualitative analysis methods for welding / bonding structure, shell and cap respectively:

[0125] (1) Welding / bonding structure

[0126] In a typical SiP product from a certain manufacturer, the chip and substrate are bonded using conductive adhesives. The two main types of conductive adhesives used are high-temperature conductive adhesive JM7000 and low-temperature conductive adhesive 84-1LMISR4. The SiP evaluation test carrier must fully cover the conductive adhesive material, so both types of conductive adhesives must be considered in the carrier design.

[0127] In the bonding process, the curing process of the conductive adhesive is a key factor in the bonding of the conductive adhesive. The curing temperature and time have a great influence on its bonding strength and reliability. During the curing process of the conductive adhesive, solvents and water vapor will be released. An inappropriate curing temperature will cause the water vapor to concentrate and form some voids in the conductive adhesive. Too many voids will affect the effective bonding area, resulting in a decrease in the bonding strength of the conductive adhesive and even failure. Excessively high curing temperatures will also cause the surface of the conductive adhesive to solidify first to form a thin film, which will prevent the water vapor from being discharged normally and will gather in the conductive adhesive to form voids. This will also affect the bonding quality. In the conductive adhesive bonding process, some bubbles are inevitable at the bonding interface. Under the action of moist heat loads and temperature shocks, these bubbles will cause stress concentration, greatly reducing the thermal fatigue life of electronic devices and accelerating the destruction and failure of electronic devices.

[0128] In the conductive adhesive bonding process, the larger the chip size, the greater the probability of pores appearing at the conductive adhesive bonding interface, and its reliability will be relatively lower. Therefore, in the design of the SiP evaluation test carrier, the chip size bonded with conductive adhesive should be larger than the chip size of the SiP product. The maximum size of the chip bonded with the high-temperature conductive adhesive JM7000 in the product is 16.13mm×13.96mm×0.40mm, and the chip size bonded on the test evaluation carrier should be designed to be approximately 20mm×20mm. The maximum size of the chip bonded with the low-temperature conductive adhesive 84-1LMISR4 in the product is 6.7mm×6.7mm×0.40mm, and the chip size bonded on the test evaluation carrier should be designed to be approximately 12mm×12mm.

[0129] (2) Shell and cap

[0130] A typical SiP product from a certain manufacturer uses a high-temperature co-fired HTCC ceramic tube package with two cavities: the upper cavity is sealed with alloy fusion, and the lower cavity is welded with parallel seams. The SiP evaluation test vehicle needs to cover both cover plate welding methods. The cover plate material used is consistent with the product, and the cover plate's dimensional parameters require special design.

[0131] According to the PFMECA results of SiP products, the tube shell and capping processes have fewer steps and the severity of the failure mode is relatively low. In the design of the SiP evaluation test vehicle, the design of these two structures should be based on sufficient support for the chips and capacitors inside the cavity, reflecting the reliability of the processing technology.

[0132] The difficulty of the tube shell and capping process is positively correlated with their size, meaning that larger tube shells increase the difficulty. The SiP product's HTCC ceramic tube shell measures 32mm x 32mm, with an alloy solder cover plate measuring 23.37mm x 23.37mm in outer diameter and 20.83mm x 20.83mm in inner diameter. The flat seam cover plate has an outer diameter of 23.75mm x 23.75mm and a boss size of 21.00mm x 21.00mm. In the SiP evaluation test vehicle, the tube shell should be designed to be larger than 32mm, perhaps a square with a side length of 40mm. The sizes of the upper and lower cavity covers can also be increased proportionally.

[0133] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

[0134] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A method for characterizing the characteristics of a SiP process reliability evaluation test carrier, characterized in that include: Analyze the manufacturing process of SiP products; Determine key processes based on process failure modes, effects and criticality analysis; Determine the key structures based on the risk factors of key processes; Including key structures that can be quantitatively analyzed and key structures that cannot be quantitatively analyzed; Design characteristic characterization parameters of key structures that can be quantitatively analyzed through failure physics methods; Design characteristic characterization parameters of key structures that cannot be quantitatively analyzed through qualitative analysis methods to complete characteristic characterization; The key process is determined by: According to the possible failure modes, causes and impacts on SiP products in each process flow during the manufacturing process of SiP products, determine the severity level of each failure mode, the probability level of each failure mode, and the difficulty level of each failure mode being detected, and calculate the risk priority value of each failure mode by multiplication, and determine the key process of SiP products according to the size of the risk priority value; The key processes include substrate manufacturing process, tube shell manufacturing process, chip packaging process, passive components, wire manufacturing process and capping process. The key processes of SiP process products are determined through impact and hazard analysis; Analyze the risk factors of the key processes of SiP products and determine the key structure of the SiP evaluation test carrier, specifically: Determine the risk factors of substrate manufacturing process, chip packaging process, tube shell manufacturing and capping process, tube shell manufacturing process, and obtain key structures by adjusting the manufacturing process design according to each risk factor; Through the finite element simulation software COMSOL Multiphysics, the geometric model of the key structure is established, the failure mechanism of the key structure is analyzed and the corresponding environmental stress is applied to the geometric model. The stress condition of the key structure is determined through simulation calculation. According to the parameters of different key processes, different simulation results are obtained and the numerical values ​​of the characteristic characterization parameters of the SiP evaluation test carrier that can be quantitatively analyzed are determined.

2. The method for characterizing a SiP process reliability evaluation test carrier according to claim 1, characterized in that: The specific analysis process is as follows: Determine the process flow of SiP product manufacturing, and analyze the equipment, materials, process control parameters, technical indicators and inspection methods involved in the process flow.

3. The method for characterizing a SiP process reliability evaluation test carrier according to claim 1, characterized in that: Qualitative analysis is performed based on failure modes and failure mechanisms to determine the values ​​of characteristic characterization parameters of the SiP evaluation test vehicle that cannot be quantitatively analyzed.

4. The method for characterizing a SiP process reliability evaluation test carrier according to claim 3, characterized in that: Key structures that can be quantitatively analyzed include through-holes in substrates, tile stacks in substrates, and bonding wires; Critical structures that cannot be quantitatively analyzed include welding / bonding structures, tube shells and caps.

5. A characterization system using the characterization method of a SiP process reliability evaluation test carrier as claimed in claim 4, characterized in that: It includes analysis module, key structure determination module and characteristic characterization parameter design module, among which: The analysis module analyzes the SiP product manufacturing process and determines the key processes based on the process failure mode, impact and hazard analysis; The key structure determination module determines the key structure based on the risk factors of the key process; The characteristic characterization parameter design module designs the characteristic characterization parameters of key structures that can be quantitatively analyzed through failure physics methods, and designs the characteristic characterization parameters of key structures that cannot be quantitatively analyzed through qualitative analysis methods.

6. The characteristic characterization system of the characteristic characterization method of the SiP process reliability evaluation test carrier according to claim 5, characterized in that: In the analysis module, the process flow of SiP product manufacturing is determined, the process content and operating process procedures are clarified, the equipment, materials, process control parameters, technical indicators and inspection methods involved in the process flow are analyzed, and the possible failure modes, causes and impacts on SiP products in each process step during the SiP product manufacturing process are determined. The severity level of each failure mode, the probability level of each failure mode, and the difficulty level of detection of each failure mode are determined, and the risk priority value of each failure mode is calculated by multiplication, and the key process of the SiP product is determined according to the size of the risk priority value.

7. The characteristic characterization system of the characteristic characterization method of the SiP process reliability evaluation test carrier according to claim 6, characterized in that: In the key structure determination module, risk factor analysis is performed on the key processes of SiP products, and risk factors of substrate manufacturing process, chip packaging process, shell and tube manufacturing and capping process, and shell and tube manufacturing process are determined respectively. The key structure is obtained by adjusting the manufacturing process design according to each risk factor.

8. The characteristic characterization system of the characteristic characterization method of the SiP process reliability evaluation test carrier according to claim 7, characterized in that: Qualitative analysis is performed based on failure modes and failure mechanisms to determine the values ​​of characteristic characterization parameters of the SiP evaluation test vehicle that cannot be quantitatively analyzed.

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