Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate including a target layer, on which a pattern definition layer is formed; forming an opening extending in a first direction and arranged in a second direction in the pattern definition layer; forming a first sidewall layer on the sidewall of the opening, comprising a first sub-sidewall layer and a second sub-sidewall layer arranged alternately; forming a first sacrificial layer in the remaining space of the opening; forming a second sacrificial layer on top of the first sub-sidewall layer or the second sub-sidewall layer, the second sacrificial layer covering a portion of the pattern definition layer and the first sacrificial layer in the second direction; forming a second sidewall layer on the sidewall of the second sacrificial layer; using the second sidewall layer as a mask, removing the second sacrificial layer and the first sacrificial layer and the pattern definition layer on both sides of the second sidewall layer; etching the target layer using the remaining first sacrificial layer and the pattern definition layer, and the first sidewall layer as a mask to form a target pattern. The present invention further reduces the pitch between target patterns while increasing the process window.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In the development of integrated circuits, as the functional density (i.e. the number of internal connection structures of each chip) gradually increases, the geometric size (i.e. the minimum component size that can be produced using the process steps) also gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] At present, as technology nodes continue to shrink, how to break through the current limitations of lithography equipment and meet the process requirements of increasingly smaller metal line widths has become a challenge. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is conducive to further reducing the pitch between target patterns.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a target layer for forming a target pattern, a pattern definition layer formed on the target layer; forming an opening penetrating the pattern definition layer in the pattern definition layer, the opening extending along a first direction and arranged along a second direction, the second direction and the first direction being perpendicular to each other; forming a first sidewall layer on the sidewall of the opening, along the second direction, the first sidewall layer comprising a first sub-sidewall layer and a second sub-sidewall layer alternately arranged; after forming the first sidewall layer, forming a first sacrificial layer in the remaining space of the opening; A second sacrificial layer is formed on the top of the first sub-spacer layer or the second sub-spacer layer, and in the second direction, the second sacrificial layer also extends to cover a partial size of the graphic definition layer and the first sacrificial layer; a second spacer layer is formed on the side wall of the second sacrificial layer; the second sacrificial layer and the first sacrificial layer and the graphic definition layer on both sides of the second spacer layer are removed using the second spacer layer as a mask; after removing the second sacrificial layer and the first sacrificial layer and the graphic definition layer on both sides of the second spacer layer, the target layer is etched using the remaining first sacrificial layer and the graphic definition layer, and the first spacer layer as a mask to form a target graphic.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] An embodiment of the present invention provides a method for forming a semiconductor structure, forming a first sidewall layer on the sidewall of an opening, forming a first sacrificial layer in the remaining space of the opening, and then forming a second sacrificial layer on top of the first sub-sidewall layer or the second sub-sidewall layer, wherein the second sacrificial layer also extends along a second direction to cover a portion of the size of the graphic definition layer and the top of the first sacrificial layer, and then forming a second sidewall layer on the sidewall of the second sacrificial layer, using the second sidewall layer as a mask to remove the second sacrificial layer and the first sacrificial layer and the graphic definition layer on both sides of the second sidewall layer, and etching the target layer using the remaining first sacrificial layer and the graphic definition layer, and the first sidewall layer as a mask to form a target graphic. The embodiment of the present invention etches part of the first sacrificial layer and the pattern definition layer using the second sidewall layer as a mask to retain the remaining first sacrificial layer and the pattern definition layer between adjacent first sidewall layers. Accordingly, in the process of etching the target layer using the first sidewall layer as a mask, the target layer is also etched using the remaining first sacrificial layer and the pattern definition layer as a mask. Compared with the current etching of the target layer using only the first sidewall layer as a mask, the embodiment of the present invention utilizes different processes to respectively form the first sidewall layer, and the remaining first sacrificial layer and the pattern definition layer located between adjacent first sidewall layers, thereby being able to meet the requirements of continuously shrinking the line width (width) and spacing (space) of the target pattern while increasing the process window of the lithography process, which is beneficial to further reduce the pitch (pitch) between the target patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0010] Currently, due to the limitation of lithography equipment, the width of metal lines formed in semiconductor devices is too large and cannot meet the process requirements of smaller and smaller metal line widths, making it difficult to further reduce the pitch between target graphics.

[0011] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a target layer for forming a target pattern, the target layer having a pattern definition layer formed thereon; forming an opening penetrating the pattern definition layer in the pattern definition layer, the opening extending along a first direction and arranged along a second direction, the second direction and the first direction being perpendicular to each other; forming a first sidewall layer on a sidewall of the opening, the first sidewall layer comprising a first sub-sidewall layer and a second sub-sidewall layer alternately arranged along the second direction; after forming the first sidewall layer, forming a first sacrificial layer in the remaining space of the opening; A second sacrificial layer is formed on the top of the first sub-spacer layer or the second sub-spacer layer, and in the second direction, the second sacrificial layer also extends to cover a partial size of the graphic definition layer and the first sacrificial layer; a second spacer layer is formed on the side wall of the second sacrificial layer; the second sacrificial layer and the first sacrificial layer and the graphic definition layer on both sides of the second spacer layer are removed using the second spacer layer as a mask; after removing the second sacrificial layer and the first sacrificial layer and the graphic definition layer on both sides of the second spacer layer, the target layer is etched using the remaining first sacrificial layer and the graphic definition layer, and the first spacer layer as a mask to form a target graphic.

[0012] In the formation method provided by an embodiment of the present invention, a first sidewall layer is formed on the sidewall of the opening, a first sacrificial layer is formed in the remaining space of the opening, and then a second sacrificial layer is formed above the top of the first sub-sidewall layer or the second sub-sidewall layer, the second sacrificial layer also extends along the second direction to cover a partial size of the graphic definition layer and the top of the first sacrificial layer, and then a second sidewall layer is formed on the sidewall of the second sacrificial layer, and the second sidewall layer is used as a mask to remove the second sacrificial layer and the first sacrificial layer and the graphic definition layer on both sides of the second sidewall layer, and the target layer is etched using the remaining first sacrificial layer and the graphic definition layer, and the first sidewall layer as a mask to form a target graphic. The embodiment of the present invention etches part of the first sacrificial layer and the pattern definition layer using the second sidewall layer as a mask to retain the remaining first sacrificial layer and the pattern definition layer between adjacent first sidewall layers. Accordingly, in the process of etching the target layer using the first sidewall layer as a mask, the target layer is also etched using the remaining first sacrificial layer and the pattern definition layer as a mask. Compared with the current etching of the target layer using only the first sidewall layer as a mask, the embodiment of the present invention utilizes different processes to respectively form the first sidewall layer, and the remaining first sacrificial layer and the pattern definition layer located between adjacent first sidewall layers, thereby being able to meet the requirements of continuously shrinking the line width (width) and spacing (space) of the target pattern while increasing the process window of the lithography process, which is beneficial to further reduce the pitch (pitch) between the target patterns.

[0013] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0014] Figures 1 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0015] refer to Figure 1 , providing a substrate, wherein the substrate includes a target layer 100 for forming a target pattern, and a pattern definition layer 101 is formed on the target layer 100.

[0016] The substrate is used to provide a process platform for subsequent process steps.

[0017] In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as resistor structures and conductive structures may also be formed in the substrate.

[0018] The target layer 100 is used as a material layer that needs to be patterned to form a target pattern.

[0019] Among them, the target graphics can be gate structures, interconnect grooves in the back end of line (BEOL) process, fins in fin field effect transistors (FinFETs), channel stacks in all-around gate (GAA) transistors or forksheet transistors, hard mask (HM) layers and other graphics.

[0020] In this embodiment, the target layer 100 is a dielectric layer, and the target layer 100 is subsequently patterned to form a plurality of interconnection grooves in the target layer 100, and then metal interconnection lines are formed in the interconnection grooves. The target layer 100 is used to achieve electrical isolation between metal interconnection lines in the back-end process.

[0021] To this end, the material of the target layer 100 is a low-k dielectric material (a low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant less than 2.6), silicon oxide, silicon nitride or silicon oxynitride, etc.

[0022] In this embodiment, the material of the target layer 100 is an ultra-low-k dielectric material, so as to reduce the parasitic capacitance between the back-end interconnects and further reduce the back-end RC delay. Specifically, the material of the target layer 100 can be SiOCH.

[0023] It should be noted that, in this embodiment, other film layers or structures in the substrate located below the target layer 100 are not illustrated.

[0024] In this embodiment, the substrate further includes a hard mask material layer (not shown) located on the target layer 100 and an etch stop layer (not shown) located on the hard mask material layer.

[0025] The hard mask material layer is used to form a hard mask layer (not shown) after a subsequent patterning process.

[0026] Specifically, the pattern is subsequently transferred to the hard mask material layer to form a hard mask layer, and then the target layer 100 is etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of patterning.

[0027] In this embodiment, the material of the hard mask material layer is silicon nitride. In other embodiments, the material of the hard mask material layer may also be silicon oxide, silicon oxynitride, silicon carbide, titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride or tungsten nitride.

[0028] The subsequent process includes multiple graphic definition processing. The etch stop layer is used to define the etching stop position in the etching process of the subsequent graphic definition processing, which is beneficial to reduce the loss of the target layer 100 and improve the depth consistency of the etching process, thereby improving the effect of the subsequent graphic process.

[0029] In this embodiment, the material of the etch stop layer is silicon oxide. In other embodiments, the material of the etch stop layer may also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride or aluminum nitride.

[0030] In this embodiment, the pattern definition layer 101 is formed on the etch stop layer.

[0031] The pattern definition layer 101 provides a process basis for subsequent process technologies.

[0032] In this embodiment, the material of the pattern definition layer is amorphous silicon.

[0033] It should be noted that the lattice structure of amorphous silicon has an unstable characteristic. The etching rate uniformity when etching amorphous silicon is high, which is conducive to the subsequent formation of an opening penetrating the pattern definition layer 101 in the pattern definition layer 101 .

[0034] refer to Figures 2 to 3 , an opening 105 penetrating the pattern definition layer 101 is formed in the pattern definition layer 101, and the opening 105 is along a first direction (such as Figure 2 ) and extends along a second direction (as shown in the Y direction Figure 2 The second direction and the first direction are perpendicular to each other.

[0035] Wherein, the first direction (such as Figure 2 The Y direction in the figure refers to the extending direction of the opening 105 in the top view.

[0036] In this embodiment, the direction parallel to the substrate surface and perpendicular to the first direction is the second direction (eg Figure 2 X direction).

[0037] In this embodiment, the opening 105 exposes the top surface of the target layer 100 .

[0038] In this embodiment, the opening 105 formed in the pattern definition layer 101 is defined as a first opening 105 , and the first opening 105 provides a space for the subsequent formation of the first sidewall layer and the first sacrificial layer.

[0039] In this embodiment, the step of forming the first opening 105 includes: forming a first mask layer 102 having a first mask opening 202 on the top of the graphic definition layer 101, the first mask opening 202 extending along the first direction and exposing a partial width of the top of the graphic definition layer 101 in the second direction; using the first mask layer 102 as a mask, removing the exposed graphic definition layer 101 along the first mask opening 202 to form the first opening 105.

[0040] In this embodiment, an anisotropic dry etching process is used to remove the pattern definition layer 101 that is partially exposed in the second direction.

[0041] The anisotropic dry etching process has the characteristic of anisotropic etching, so its longitudinal etching rate is much greater than the lateral etching rate, and can obtain quite accurate pattern transfer, thereby improving the morphology quality of the side wall of the first opening 105 .

[0042] The first mask layer 102 includes a first organic material layer 1021 , a first anti-reflection coating layer 1022 on the first organic material layer 1021 , and a first photoresist layer 1023 on the first anti-reflection coating layer 1022 .

[0043] The material of the first organic material layer 1021 includes an organic material. In this embodiment, the material of the first organic material layer 1021 is spin-on carbon (SOC). In other embodiments, the material of the first organic material layer can also be other organic materials, such as: one or more of ODL (organic dielectric layer) material, DUO (Deep UV Light Absorbing Oxide) material and APF (Advanced Patterning Film) material.

[0044] The material of the first anti-reflective coating 1022 includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0045] In this embodiment, during the process of forming the first mask layer 102, the first anti-reflective coating layer 1022 and the first organic material layer 1021 are sequentially etched using the first photoresist layer 1023 as a mask.

[0046] It should be noted that, in other embodiments, during the process of etching the first anti-reflective coating and the first organic material layer, the first photoresist layer will be consumed, and the first mask layer may correspondingly only include the first organic material layer and the first anti-reflective coating located on the first organic material layer.

[0047] In this embodiment, after forming the first opening 105 , the method further includes: removing the remaining first mask layer 102 .

[0048] refer to Figure 4 A first spacer layer 103 is formed on the sidewall of the first opening 105 . Along the second direction, the first spacer layer 103 includes first sub-spacer layers 1031 and second sub-spacer layers 1032 that are alternately arranged.

[0049] The first spacer layer 103 is used as an etching mask for subsequently etching the target layer 100 .

[0050] It should be noted that by forming the first spacer layer 103 on the sidewall of the first opening 105 and reducing the size of the first opening 105 along the second direction, the requirement of continuously reducing the line width of the target pattern can be met while increasing the process window of the photolithography process.

[0051] In this embodiment, along the second direction (such as Figure 4(shown in the X direction), the size of the first spacer layer 103 is equal to the size of the second spacer layer to be formed subsequently, so that the intervals between the subsequent adjacent target patterns are equal.

[0052] It should be noted that the size of the first sidewall layer 103 should not be too large or too small. If the size of the first sidewall layer 103 is too large, it is easy to occupy too much space of the first opening 105, which may cause the size of the target pattern to be formed later to be too small, which may result in the line width requirement of the target pattern not being met, or the interval between the target patterns not being able to reach the minimum design interval, thereby affecting the performance of the metal interconnection line; if the size of the first sidewall layer 103 is too small, it is easy to cause the remaining space of the first opening 105 to be too large, which may cause the target pattern formed by etching the target layer 100 using the first sidewall layer 103 as a mask to be too large, which may result in the line width of the target pattern not being met, thereby affecting the performance of the metal interconnection line, or, in order to make the line width of the target pattern meet the process requirements, the size of the first opening 105 needs to be reduced accordingly, thereby easily reducing the process window for forming the first opening 105. To this end, in this embodiment, along the second direction, the size of the first sidewall layer 103 is 10 nanometers to 20 nanometers. For example, along the second direction, the size of the first spacer layer 103 is 13 nanometers, 15 nanometers or 17 nanometers.

[0053] It should be noted that, in this embodiment, the size of the first spacer layer 103 along the second direction is relatively small, so that a relatively small interval is achieved between subsequent adjacent target patterns.

[0054] In this embodiment, the process of forming the first spacer layer 103 includes an atomic layer deposition process.

[0055] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the first spacer layer 103 and enabling the first spacer layer 103 to cover the sidewall of the pattern definition layer 101. In other embodiments, the first spacer layer can also be formed by a chemical vapor deposition process (CVD).

[0056] The material of the first spacer layer 103 is selected as follows: the first spacer layer 103 can be retained in the subsequent process of removing the first sacrificial layer and the second sacrificial layer, and the target layer 100 can be etched using the first spacer layer 113 as a mask.

[0057] Therefore, in this embodiment, the material of the first spacer layer 103 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride or aluminum oxide. In this embodiment, the material of the first spacer layer 103 is titanium oxide. Titanium oxide material has a large etching selection compared with amorphous silicon or spin-on glass.

[0058] In this embodiment, the step of forming the first side wall layer 103 includes: forming a first side wall material layer (not shown) on the top and side walls of the graphic definition layer 101 and the bottom of the first opening 105, removing the first side wall material layer on the top of the graphic definition layer 101 and the bottom of the first opening 105, and the remaining first side wall material layer serves as the first side wall layer 103.

[0059] refer to Figure 5 After forming the first spacer layer 103 , a first sacrificial layer 106 is formed in the remaining space of the first opening 105 .

[0060] The first sacrificial layer 106 provides a process platform for subsequently forming a second spacer layer, and by transferring the pattern of the second spacer layer to the first sacrificial layer 106 , the remaining first sacrificial layer 106 is used as a mask for etching the target layer 100 .

[0061] It should be noted that the etching selectivity ratios between the first sacrificial layer 106 and the first sidewall layer 103 and the subsequently formed second sidewall layer are relatively large, which is conducive to the subsequent use of the second sidewall layer as a mask to remove part of the first sacrificial layer 106 and reduce damage to the first sidewall layer 103.

[0062] In this embodiment, the material of the first sacrificial layer 106 includes one or more of spin-on glass, ion-enhanced silicon oxide and tetraethyl orthosilicate, which enables a higher etching selectivity ratio between the target layer 100 and the first sacrificial layer 106, and facilitates the subsequent etching of the target layer 100 using the remaining first sacrificial layer 106 between the first spacer layers 103 as a mask. As an example, the material of the first sacrificial layer 106 is spin-on glass.

[0063] refer to Figures 6 to 9 A second sacrificial layer 108 is formed on top of the first sub-spacer layer 1031 or the second sub-spacer layer 1032, and in the second direction (eg Fig. 9 In the X direction, the second sacrificial layer 108 also extends to cover a portion of the size of the pattern definition layer 101 and the first sacrificial layer 106.

[0064] The adjacent second sacrificial layers 108 form a second opening 310 , and the second opening 310 provides space for the subsequent formation of a second sidewall layer.

[0065] In this embodiment, the second sacrificial layer 108 is formed above the top of the first sub-spacer layer 1031 or the second sub-spacer layer 1032, that is, the second sacrificial layer 108 is located at the top of the junction of the graphic definition layer 101 and the first sacrificial layer 106, and the second opening 310 is located above the top of the junction of the graphic definition layer 101 and the first sacrificial layer 106. Accordingly, after the second spacer layer is subsequently formed on the sidewall of the second sacrificial layer 108, the position of the second spacer layer can be located between adjacent first spacer layers 103, thereby being able to meet the requirements of continuously shrinking line width and spacing of the target graphic while increasing the process window of the lithography process.

[0066] In this embodiment, in the step of forming the second sacrificial layer 108 , along the second direction, the size of the second sacrificial layer 108 covering the top of the pattern definition layer 101 accounts for one third to one half of the size of the pattern definition layer 101 .

[0067] It should be noted that the ratio of the size of the second sacrificial layer 108 covering the top of the pattern definition layer 101 to the size of the pattern definition layer 101 should not be too large or too small. After etching part of the pattern definition layer 101 using the second sidewall layer formed on the sidewall of the second sacrificial layer 108 as a mask, the target layer 100 is etched using the remaining pattern definition layer 101 retained between the adjacent first sidewall layers 103 as a mask to form a target pattern. In other words, two target patterns are subsequently formed between the adjacent first sidewall layers 103. If the size of the second sacrificial layer 108 along the second direction meets the process requirements, if the ratio is too large or too small, it is easy to cause the line width of the formed target pattern to fail to reach the target value, thereby affecting the performance of the metal interconnection line. For this reason, in this embodiment, along the second direction, the size of the second sacrificial layer 108 covering the top of the pattern definition layer 101 accounts for one third to one half of the size of the pattern definition layer 101.

[0068] In this embodiment, along the second direction, the size of the second sacrificial layer 108 covering the top of the first sacrificial layer 106 accounts for one third to one half of the size of the first sacrificial layer 106 .

[0069] It should be noted that the ratio of the size of the second sacrificial layer 108 covering the top of the first sacrificial layer 106 to the size of the first sacrificial layer 106 should not be too large or too small. After etching part of the first sacrificial layer 106 using the second sidewall layer formed on the sidewall of the second sacrificial layer 108 as a mask, the target layer 100 is etched using the remaining first sacrificial layer 106 retained between adjacent first sidewall layers 103 as a mask to form a target pattern. In other words, two target patterns are subsequently formed between adjacent first sidewall layers 103. When the size of the second sacrificial layer 108 along the second direction meets the process requirements, if the ratio is too large or too small, it is easy to cause the line width of the formed target pattern to fail to reach the target value, thereby affecting the performance of the metal interconnection line. For this reason, in this embodiment, along the second direction, the size of the second sacrificial layer 108 covering the top of the first sacrificial layer 106 accounts for one third to one half of the size of the first sacrificial layer 106.

[0070] The material of the second sacrificial layer 108 includes one or more of amorphous silicon, spin-on glass and tetraethyl orthosilicate, so as to improve the etching selectivity between the second spacer layer and the second sacrificial layer 108. In this embodiment, the material of the second sacrificial layer 108 is amorphous silicon.

[0071] It should be noted that the lattice structure of amorphous silicon has an unstable characteristic, which makes it easy to remove the second sacrificial layer through a subsequent wet etching process and is beneficial to improving the uniformity of the etching rate.

[0072] Specifically, the step of forming the second sacrificial layer 108 includes: Figure 7 As shown, a second sacrificial material layer 180 is formed on top of the pattern definition layer 101, the first sacrificial layer 106 and the first spacer layer 103; Figure 8 As shown, a mask layer 109 having a mask opening 110 is formed on the second sacrificial material layer 180, the mask layer 109 covers the top of the first sub-spacer layer 1031 or the second sub-spacer layer 1032, and extends along the second direction to cover a portion of the pattern definition layer 101 and the first sacrificial layer 106; as shown Fig. 9 As shown, the mask layer 109 is used as a mask to etch the second sacrificial material layer 180 exposed by the mask opening 110 , and the remaining second sacrificial material layer 180 serves as the second sacrificial layer 108 .

[0073] In this embodiment, the first mask layer 102 is used in the process of forming the first opening 105. Therefore, the mask layer 109 is defined as the second mask layer 109. The second mask layer 109 includes a second organic material layer 1091, a second anti-reflective coating 1092 located on the second organic material layer 1091, and a second photoresist layer 1093 located on the second anti-reflective coating 1092.

[0074] The specific description of the mask layer 109 can be combined with reference to the corresponding description of the first mask layer 102, which will not be repeated here.

[0075] It should be noted that, in this embodiment, a situation in which the second sacrificial layer 108 is formed on the top of the second sub-spacer layer 1032 is shown.

[0076] Combined with reference Figure 6 After forming the first sacrificial layer 106 and before forming the second sacrificial layer 108 , it also includes: forming a protective layer 107 on the top of the graphic definition layer 101 and the first sacrificial layer 106 , and the protective layer 107 also covers the top of the first sidewall layer 103 .

[0077] Before subsequently removing the first sacrificial layer 106 and the graphic definition layer 101 on both sides of the second sidewall layer, the second sacrificial layer 108 will be removed first. During the process of removing the second sacrificial layer 108, in order to reduce the probability of damage to the graphic definition layer 101 caused by the related etching process, a protective layer 107 is formed on the top of the graphic definition layer 101 and the first sacrificial layer 106. The protective layer 107 protects the top of the graphic definition layer 101 and the first sacrificial layer 106.

[0078] Moreover, during the process of patterning the second sacrificial material layer 180 , the protection layer 107 can also protect the pattern definition layer 101 and the top of the first sacrificial layer 106 .

[0079] In this embodiment, the material of the protection layer 107 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0080] The silicon oxide, silicon nitride and silicon oxynitride have the characteristics of high etching resistance. In the subsequent process of removing the second sacrificial layer, the protective layer 107 can play the role of etching stop, thereby protecting the top of the graphic definition layer 101 and the first sacrificial layer 106.

[0081] It should be noted that the thickness of the protective layer 107 should not be too large or too small. Before removing the first sacrificial layer 106 and the graphic definition layer 101 on both sides of the second sidewall layer, it is necessary to remove the protective layer 107 on both sides of the second sidewall layer. If the thickness of the protective layer 107 is too large, it will take more time to etch the protective layer 107, which will increase the probability of the second sidewall layer being consumed, which will easily lead to the difficulty of transferring the graphics of the second sidewall layer to the first sacrificial layer 106 and the graphic definition layer 101; if the thickness of the protective layer 107 is too small, it will easily lead to the protective layer 107 not being able to play a protective effect in the subsequent removal of the second sacrificial layer 108, thereby increasing the probability of the top of the first sacrificial layer 106 and the graphic definition layer 101 being damaged, and over-etching is likely to occur. For this reason, in this embodiment, the thickness of the protective layer 107 is 1 nanometer to 5 nanometers. For example, the thickness of the protective layer 107 is 3 nanometers.

[0082] refer to Fig.10 , a second spacer layer 112 is formed on the sidewall of the second sacrificial layer 108 .

[0083] In this embodiment, in the subsequent process of removing the second sacrificial layer 108 and the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 , the second spacer layer 112 is used as an etching mask.

[0084] It should be noted that, the pattern of the second sidewall layer 112 is subsequently transferred to the first sacrificial layer 106 and the pattern definition layer 101, and the target layer 100 is etched using the remaining first sacrificial layer 106 and the pattern definition layer 101, and the first sidewall layer 103 as a mask to form a target pattern. By forming a second sidewall layer 112 on the side wall of the second sacrificial layer 108, the space between the first sidewall layers 103 is divided in the second direction, thereby meeting the requirement of continuously shrinking the line width of the target pattern while increasing the process window of the lithography process.

[0085] In this embodiment, along the second direction (such as Fig.10 (shown in the X direction), the size of the second spacer layer 112 is 10 nanometers to 20 nanometers.

[0086] It should be noted that the size of the second spacer layer 112 should not be too large or too small. If the size of the second spacer layer 112 is too large, it is easy to occupy too much space of the second opening 310, which may cause the size of the target pattern to be formed later to be too small, which may fail to meet the requirements of the line width of the target pattern, or cause the interval between the target patterns to fail to reach the minimum design interval, thereby affecting the performance of the metal interconnection line; if the size of the second spacer layer 112 is too small, it is easy to cause the remaining space of the second opening 310 to be too large, which may cause the target pattern to be formed by etching the target layer 100 with the remaining pattern definition layer 101 and the first sacrificial layer 106 as a mask to be too large, which may make it difficult to meet the requirements of the continuously shrinking line width of the target pattern, thereby affecting the performance of the metal interconnection line, or, in order to make the line width of the target pattern meet the process requirements, it is necessary to reduce the size of the second opening 310 accordingly, thereby easily reducing the process window for forming the second opening 310. To this end, in this embodiment, along the second direction, the size of the second spacer layer 112 is 10 nanometers to 20 nanometers. For example, along the second direction, the size of the second spacer layer 112 is 13 nanometers, 15 nanometers or 17 nanometers.

[0087] It should be noted that, in the present embodiment, the size of the second spacer layer 112 along the second direction is relatively small, so that a relatively small interval is achieved between subsequent adjacent target patterns.

[0088] In this embodiment, the process of forming the second spacer layer 112 includes an atomic layer deposition process.

[0089] The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the second spacer layer 112, so that the second spacer layer 112 can cover the sidewall of the second sacrificial layer 108. In other embodiments, the second spacer layer can also be formed by a chemical vapor deposition process (CVD).

[0090] The material of the second spacer layer 112 is selected such that the second spacer layer 112 can be retained during the subsequent removal of the second sacrificial layer 108 and the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 .

[0091] In this embodiment, the material of the second spacer layer 112 may include titanium oxide, titanium nitride, silicon oxide, silicon nitride or aluminum oxide. In this embodiment, the material of the second spacer layer 112 is titanium oxide. The etching selectivity of titanium oxide material and amorphous silicon or spin-on glass is relatively large.

[0092] In this embodiment, the step of forming the second side wall layer 112 includes: forming a second side wall material layer (not shown) on the top and side walls of the second sacrificial layer 108 and the bottom of the second opening 310, removing the second side wall material layer on the top of the second sacrificial layer 108 and the bottom of the second opening 310, and the remaining second side wall material layer serves as the second side wall layer 112.

[0093] In this embodiment, in the step of forming the second spacer layer 112 , in the second direction, the size of the first spacer layer 103 is equal to the size of the second spacer layer 112 .

[0094] It should be noted that the size of the first spacer layer 103 is equal to the size of the second spacer layer 112 , so that the intervals between subsequent adjacent target patterns are equal.

[0095] It should also be noted that by adjusting the ratio of the size of the second sacrificial layer 108 covering the top of the graphic definition layer 101 to the size of the graphic definition layer 101, and the ratio of the size of the second sacrificial layer 108 covering the top of the first sacrificial layer 106 to the size of the first sacrificial layer 106 in the second direction, it is easy to make the line width size of the target graphic along the second direction the same.

[0096] refer to Figure 11 to Figure 12 , using the second spacer layer 112 as a mask, the second sacrificial layer 108 and the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 are removed.

[0097] It should be noted that, by using the second sidewall layer 112 as a mask to etch part of the first sacrificial layer 106 and the graphic definition layer 101, the remaining first sacrificial layer 106 and the graphic definition layer 101 between adjacent first sidewall layers 103 are retained. Accordingly, in the process of etching the target layer 100 using the first sidewall layer 103 as a mask, the target layer 100 is also etched using the remaining first sacrificial layer 106 and the graphic definition layer 101 as masks. Compared with the current method of etching the target layer 100 using only the first sidewall layer 103 as a mask, this embodiment uses different processes to respectively form the first sidewall layer 103, and the remaining first sacrificial layer 106 and the graphic definition layer 101 located between adjacent first sidewall layers 103, so that the requirements of continuously reducing the line width (width) and spacing (space) of the target graphic can be met while increasing the process window of the lithography process, which is conducive to further reducing the pitch (pitch) between the target graphics.

[0098] In this embodiment, the second sacrificial layer 108 is removed first, and then the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 are removed.

[0099] By first removing the second sacrificial layer 108 and then removing the first sacrificial layer 106 and the graphic definition layer 101 on both sides of the second sidewall layer 112, during the process of removing the first sacrificial layer 106 and the graphic definition layer 101, the longitudinal removal amount of each area is the same, thereby improving etching uniformity.

[0100] In this embodiment, a wet etching process is used to remove the second sacrificial layer 108 .

[0101] The wet etching process has the characteristics of high efficiency and low cost in removing organic materials, and can reduce damage to the underlying film layer.

[0102] In this embodiment, a dry etching process is used to remove the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 .

[0103] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, so its longitudinal etching rate is much greater than the lateral etching rate, and can obtain quite accurate pattern transfer, thereby improving the morphology quality of the remaining pattern definition layer 101 and the first sacrificial layer 106.

[0104] In this embodiment, in the step of removing the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112, the etching selectivity ratio between the first sacrificial layer 106 and the second spacer layer 112 or the first spacer layer 103 is greater than 5:1.

[0105] It should be noted that the etching selectivity ratio between the first sacrificial layer 106 and the second spacer layer 112 or the first spacer layer 103 should not be too small. If the etching selectivity ratio between the first sacrificial layer 106 and the second spacer layer 112 is too small, it is easy to cause the second spacer layer 112 to be damaged, so that it is difficult to accurately transfer the pattern of the second spacer layer 112 to the first sacrificial layer 106; if the etching selectivity ratio between the first sacrificial layer 106 and the first spacer layer 103 is too small, it is easy to cause the first spacer layer 103 to be damaged, so that it is difficult to accurately transfer the pattern of the first spacer layer 103 to the target layer 100. For this reason, in the present embodiment, in the step of removing the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112, the etching selectivity ratio between the first sacrificial layer 106 and the second spacer layer 112 or the first spacer layer 103 is greater than 5:1.

[0106] In this embodiment, in the step of removing the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112, the etching selectivity ratio between the pattern definition layer 101 and the second spacer layer 112 or the first spacer layer 103 is greater than 5:1.

[0107] It should be noted that the etching selectivity ratio between the graphic definition layer 101 and the second spacer layer 112 or the first spacer layer 103 should not be too small. If the etching selectivity ratio between the graphic definition layer 101 and the second spacer layer 112 is too small, it is easy to cause the second spacer layer 112 to be damaged, so that it is difficult to accurately transfer the pattern of the second spacer layer 112 to the graphic definition layer 101; if the etching selectivity ratio between the graphic definition layer 101 and the first spacer layer 103 is too small, it is easy to cause the first spacer layer 103 to be damaged, so that it is difficult to accurately transfer the pattern of the first spacer layer 103 to the target layer 100. For this reason, in the present embodiment, in the step of removing the first sacrificial layer 106 and the graphic definition layer 101 on both sides of the second spacer layer 112, the etching selectivity ratio between the graphic definition layer 101 and the second spacer layer 112 or the first spacer layer 103 is greater than 5:1.

[0108] It should be noted that before removing the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 , the process further includes: removing the protection layer 107 on both sides of the second spacer layer 112 .

[0109] The protective layer 107 on both sides of the second spacer layer 112 is removed to expose the top of the first sacrificial layer 106 and the pattern definition layer 101 , which provides a process basis for removing the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 .

[0110] In this embodiment, in the step of removing the protection layer 107 on both sides of the second spacer layer 112 , the etching selectivity ratio of the protection layer 107 to the second spacer layer 112 is greater than 5:1.

[0111] It should be noted that the etching selectivity ratio of the protective layer 107 to the second spacer layer 112 should not be too small. If the etching selectivity ratio of the protective layer 107 to the second spacer layer 112 is too small, it is easy to cause the second spacer layer 112 to be damaged, making it difficult to accurately transfer the pattern of the second spacer layer 112 to the pattern definition layer 101 and the first sacrificial layer 106, thereby affecting the subsequent process of forming the target pattern in the target layer 100, and further affecting the performance of the semiconductor structure. For this reason, in the present embodiment, in the step of removing the protective layer 107 on both sides of the second spacer layer 112, the etching selectivity ratio of the protective layer 107 to the second spacer layer 112 is greater than 5:1.

[0112] In this embodiment, the protection layer 107 , the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second spacer layer 112 are removed by the same etching step.

[0113] It should be noted that removing the protection layer 107, the first sacrificial layer 106 and the pattern definition layer 101 in the same etching step can simplify the process steps, improve the manufacturing efficiency accordingly, and reduce the process cost.

[0114] refer to Fig.13 After removing the second sacrificial layer 108 and the first sacrificial layer 106 and the pattern definition layer 101 on both sides of the second sidewall layer 112, the target layer 100 is etched using the remaining first sacrificial layer 106 and the pattern definition layer 101, and the first sidewall layer 103 as masks to form a target pattern 130.

[0115] It can be seen from the above description that this embodiment can meet the requirement of continuously reducing the line width of the target graphic 130 while increasing the process window of the lithography process, and is conducive to further reducing the pitch between the target graphics 130, which correspondingly improves the graphic accuracy and graphic quality of the target graphic 130.

[0116] It should be noted that the target layer 100 is a dielectric layer. Therefore, after etching the target layer 100 using the remaining first sacrificial layer 106, the pattern definition layer 101, and the first spacer layer 103 as masks, the target pattern 130 is an interconnection groove.

[0117] In this embodiment, a hard mask material layer (not shown) and an etch stop layer (not shown) are further formed on the target layer 100 , and the bottom of the first opening 105 exposes the etch stop layer.

[0118] In this embodiment, the remaining first sacrificial layer 106 and pattern definition layer 101, and the first sidewall layer 103 are used as masks to sequentially etch the etch stop layer and the hard mask material layer on the top of the target layer 100. After the remaining hard mask material layer is used as a hard mask layer (not shown), the target layer 100 is etched using the hard mask layer as a mask.

[0119] refer to Fig.14 The forming method further includes: after forming the interconnection groove 130 , forming a metal interconnection line 120 in the interconnection groove 130 .

[0120] The metal interconnection line 120 is used to realize the electrical connection between the semiconductor structure and an external circuit or other interconnection structures.

[0121] It can be seen from the above records that the present embodiment can meet the requirement of continuously reducing the line width of the interconnection grooves while increasing the process window of the photolithography process, and the spacing between adjacent interconnection grooves is easy to meet the designed minimum spacing, which is correspondingly conducive to making the spacing of the metal interconnection lines 120 meet the designed minimum spacing, which is conducive to further reducing the pitch between the metal interconnection lines 120, and is also conducive to improving the graphic accuracy of the metal interconnection lines 120, and further conducive to improving the electrical connection performance of the metal interconnection lines 120.

[0122] In this embodiment, the material of the metal interconnection line 120 is copper. In other embodiments, the material of the metal interconnection line can also be a conductive material such as aluminum.

[0123] In this embodiment, the metal interconnection line 120 is formed in the interconnection groove by using copper electroplating.

[0124] Accordingly, the process of forming the metal interconnection line 120 includes a step of filling with a conductive material and a step of planarizing the conductive material to remove the conductive material above the top of the dielectric layer.

[0125] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

[0126] The chemical mechanical polishing process enables the metal interconnection line 120 formed in the interconnection groove to have a flat surface, thereby improving the electrical connection effect of the metal interconnection line 120 .

[0127] In this embodiment, during the process of forming the metal interconnection line 120, the remaining pattern definition layer 101, the first sidewall layer 103, the first sacrificial layer 106, the etch stop layer and the hard mask layer are also removed to expose the top surface of the target layer 100 in preparation for subsequent processes.

[0128] The detailed description of the metal interconnection line 120 is omitted here.

[0129] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a target layer for forming a target pattern, the target layer having a pattern definition layer formed thereon; forming openings penetrating the pattern definition layer in the pattern definition layer, the openings extending along a first direction and arranged along a second direction, the second direction and the first direction being perpendicular to each other; forming a first spacer layer on the sidewall of the opening, wherein along the second direction, the first spacer layer comprises first sub-spacer layers and second sub-spacer layers which are alternately arranged; After forming the first sidewall layer, forming a first sacrificial layer in the remaining space of the opening; Forming a second sacrificial layer on top of the first sub-spacer layer or the second sub-spacer layer, wherein the second sacrificial layer also extends to cover a portion of the pattern definition layer and the first sacrificial layer in the second direction; forming a second spacer layer on the sidewall of the second sacrificial layer; Using the second spacer layer as a mask, removing the second sacrificial layer and the first sacrificial layer and the pattern definition layer on both sides of the second spacer layer; After removing the second sacrificial layer and the first sacrificial layer and the pattern definition layer on both sides of the second sidewall layer, the target layer is etched using the remaining first sacrificial layer, the pattern definition layer and the first sidewall layer as masks to form a target pattern.

2. The method for forming a semiconductor structure according to claim 1, wherein: After removing the second sacrificial layer, the first sacrificial layer and the pattern definition layer on both sides of the second spacer layer are removed.

3. The method for forming a semiconductor structure according to claim 2, wherein: After forming the first sacrificial layer and before forming the second sacrificial layer, the method further includes: forming a protective layer on top of the pattern definition layer and the first sacrificial layer, wherein the protective layer also covers the top of the first spacer layer; Before removing the first sacrificial layer and the pattern definition layer on both sides of the second spacer layer, the method further includes: removing the protection layer on both sides of the second spacer layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The protection layer, the first sacrificial layer and the pattern definition layer on both sides of the second spacer layer are removed by the same etching step.

5. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the second sacrificial layer includes: forming a second sacrificial material layer on top of the graphic definition layer, the first sacrificial layer and the first sidewall layer; forming a mask layer with a mask opening on the second sacrificial material layer, the mask layer covers the top of the first sub-sidewall layer or the second sub-sidewall layer, and extends along the second direction to cover a partial size of the graphic definition layer and the first sacrificial layer; using the mask layer as a mask, etching the second sacrificial material layer exposed by the mask opening, and the remaining second sacrificial material layer serves as the second sacrificial layer.

6. The method for forming a semiconductor structure according to claim 1 or 2, wherein: The second sacrificial layer is removed by a wet etching process.

7. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the second sacrificial layer, along the second direction, the size of the second sacrificial layer covering the top of the pattern definition layer accounts for one third to one half of the size of the pattern definition layer; Along the second direction, a size of the second sacrificial layer covering the top of the first sacrificial layer accounts for one third to one half of a size of the first sacrificial layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the second spacer layer, in the second direction, a size of the first spacer layer is equal to a size of the second spacer layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: Along the second direction, a size of the first spacer layer is 10 nanometers to 20 nanometers.

10. The method for forming a semiconductor structure according to claim 1, wherein: Along the second direction, a size of the second spacer layer is 10 nanometers to 20 nanometers.

11. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the first spacer layer includes an atomic layer deposition process.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the second spacer layer includes an atomic layer deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The first sacrificial layer and the pattern definition layer on both sides of the second spacer layer are removed by a dry etching process.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first sacrificial layer includes one or more of spin-on glass, ion-enhanced silicon oxide and tetraethyl orthosilicate.

15. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second sacrificial layer includes one or more of amorphous silicon, spin-on glass and tetraethyl orthosilicate.

16. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the first sacrificial layer and the pattern definition layer on both sides of the second spacer layer, the etching selectivity ratio between the first sacrificial layer and the second spacer layer or the first spacer layer is greater than 5:1; The etching selectivity ratio between the pattern definition layer and the second spacer layer or the first spacer layer is greater than 5:

1.

17. The method for forming a semiconductor structure according to claim 3, wherein: The material of the protective layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

18. The method for forming a semiconductor structure according to claim 3, wherein: The thickness of the protective layer is 1 nanometer to 5 nanometers.

19. The method for forming a semiconductor structure according to claim 3, wherein: In the step of removing the protective layer on both sides of the second spacer layer, an etching selectivity ratio between the protective layer and the second spacer layer is greater than 5:

1.

20. The method for forming a semiconductor structure according to claim 1, wherein: The target layer is a dielectric layer, and the target pattern is an interconnection groove; The forming method further includes: after forming the interconnection groove, forming a metal interconnection line in the interconnection groove.

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