Method of forming alignment marks in semiconductor processes

Abstract

The application provides a method for forming an alignment mark in a semiconductor process. After forming a groove by etching a device region and an alignment region at the same time, filling the groove with an epitaxial layer and / or a polysilicon layer, and removing a hard mask of the device region, a hard mask of the alignment region is reserved as an alignment mark by a protection layer mask. The method can avoid attenuation or disappearance of an alignment signal caused by a planarization process after epitaxy. Since the protection layer mask for the alignment mark has low requirements for alignment accuracy, the method will not affect alignment error and improve process reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to a method for forming alignment marks in a semiconductor process. BACKGROUND

[0002] In a conventional semiconductor process, an alignment mark (e.g. a separate alignment mark, or an alignment mark pattern in an active area mask) is first formed on the surface of a substrate as a starting step, and then other steps are performed. However, for a CIS (CMOS Image Sensor) or other process that requires epitaxy before the formation of an active area, since the epitaxy is completed after the formation of the alignment mark, the shallow alignment mark will be affected by the planarization process after the epitaxy, resulting in a decay or disappearance of the alignment signal.

[0003] To solve the alignment problem in a semiconductor process that requires epitaxy before the formation of an active area, a shallow trench can be formed in the alignment area and filled with a dielectric layer as an alignment mark, and then a deep trench is formed in the device area and epitaxy is performed, and then an active area is formed in the epitaxial layer. Although the alignment mark will not be affected by the planarization process after the epitaxy, this solution has the disadvantage of increasing the shallow trench lithography and etching steps, and increasing the error of nested alignment. SUMMARY

[0004] The purpose of the present application is to provide a method for forming alignment marks in a semiconductor process, which can avoid the decay or disappearance of the alignment signal caused by the planarization process after epitaxy, and also does not increase the alignment error, thereby improving the process reliability.

[0005] Based on the above considerations, the present application provides a method for forming alignment marks in a semiconductor process, comprising: providing a semiconductor substrate, defining a device area and an alignment area; simultaneously etching trenches in the device area and the alignment area using a hard mask; forming a first epitaxial layer and / or a polysilicon layer in the trenches of the device area and the alignment area; removing the hard mask in the device area while retaining the hard mask in the alignment area as an alignment mark; forming a second epitaxial layer in the device area and the alignment area; and forming a semiconductor device in the device area.

[0006] Preferably, the difference between the trench width of the device area and the trench width of the alignment area is less than 2 microns.

[0007] Preferably, after the formation of the second epitaxial layer, the trenches of the device area and the trenches of the alignment area are filled.

[0008] Preferably, the material of the hard mask includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0009] Preferably, the shape of the hard mask is an elongated strip with a width of no more than 8 microns.

[0010] The method for forming an alignment mark in a semiconductor process of the present application can avoid the attenuation or disappearance of the alignment signal caused by the planarization process after epitaxy by forming a trench in the device region and the alignment region at the same time, filling the trench with an epitaxial layer and / or a polysilicon layer, and then retaining the hard mask of the alignment region as an alignment mark by a protective layer mask when the hard mask of the device region is removed. Since the alignment mark protective layer mask has low requirements for the overlay accuracy, it will not affect the alignment error, thus improving the process reliability. BRIEF DESCRIPTION OF DRAWINGS

[0011] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments thereof as read with reference to the accompanying drawings.

[0012] Figure 1 A flow chart of the method for forming an alignment mark in a semiconductor process of the present application;

[0013] Figures 2-7 A process schematic diagram of the method for forming an alignment mark in a semiconductor process according to Embodiment One of the present application;

[0014] Figures 8-13 A process schematic diagram of the method for forming an alignment mark in a semiconductor process according to Embodiment Two of the present application.

[0015] In the drawings, like reference numerals refer to like elements throughout the various drawings. DETAILED DESCRIPTION

[0016] To solve the problems in the prior art, the present application provides a method for forming an alignment mark in a semiconductor process, which can avoid the attenuation or disappearance of the alignment signal caused by the planarization process after epitaxy by forming a trench in the device region and the alignment region at the same time, filling the trench with an epitaxial layer and / or a polysilicon layer, and then retaining the hard mask of the alignment region as an alignment mark by a protective layer mask when the hard mask of the device region is removed. Since the alignment mark protective layer mask has low requirements for the overlay accuracy, it will not affect the alignment error, thus improving the process reliability.

[0017] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration, and not by way of limitation, specific embodiments in which the application can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the application, and it is to be understood that other embodiments can be utilized and that structural or logical changes can be made without departing from the scope of the present application. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

[0018] Figure 1A flow chart of a method for forming an alignment mark in a semiconductor process is shown, comprising: providing a semiconductor substrate, defining a device region and an alignment region; etching a trench in the device region and the alignment region simultaneously using a hard mask; forming a first epitaxial layer and / or a polysilicon layer in the trench of the device region and the alignment region, respectively; removing the hard mask of the device region, leaving the hard mask of the alignment region as an alignment mark; forming a second epitaxial layer in the device region and the alignment region, respectively; forming a semiconductor device in the device region.

[0019] The present application is described in detail below with reference to specific embodiments.

[0020] Embodiment One

[0021] Figures 2-7 A preferred embodiment of a method for forming an alignment mark in a semiconductor process is shown.

[0022] As shown, a semiconductor substrate 100 is provided, defining a device region 100A and an alignment region 100B (separated by a dashed line), a trench 102 is etched in the device region 100A and the alignment region 100B simultaneously using a hard mask 101. Preferably, the material of the hard mask 101 comprises at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride. Figure 2 As shown, a first epitaxial layer 103 is formed in the trench 102 of the device region 100A and the alignment region 100B, respectively, and the first epitaxial layer 103 is planarized by chemical mechanical polishing, stopping at the surface of the hard mask 101.

[0023] Figure 3 As shown, the alignment region 100B is covered by a protective layer mask 104, so that when the hard mask 101 of the device region 100A is removed, the hard mask 101 of the alignment region 100B is left, and then the protective layer mask 104 is removed. Figure 4 As shown, a second epitaxial layer 105 is formed in the device region 100A and the alignment region 100B, respectively, and the second epitaxial layer 105 is planarized by chemical mechanical polishing. In a subsequent step not shown, a semiconductor device is formed in the second epitaxial layer 105 of the device region 100A.

[0024] Figure 5 As shown, a second epitaxial layer 105 is formed in the device region 100A and the alignment region 100B, respectively, and the second epitaxial layer 105 is planarized by chemical mechanical polishing. In a subsequent step not shown, a semiconductor device is formed in the second epitaxial layer 105 of the device region 100A. Figure 6 As shown, a second epitaxial layer 105 is formed in the device region 100A and the alignment region 100B, respectively, and the second epitaxial layer 105 is planarized by chemical mechanical polishing. In a subsequent step not shown, a semiconductor device is formed in the second epitaxial layer 105 of the device region 100A.

[0025] Figure 7 As shown, a second epitaxial layer 105 is formed in the device region 100A and the alignment region 100B, respectively, and the second epitaxial layer 105 is planarized by chemical mechanical polishing. In a subsequent step not shown, a semiconductor device is formed in the second epitaxial layer 105 of the device region 100A.

[0026] ​​​Preferably, the difference between the trench 102 width of the device region 100A and the trench 102 width of the alignment region 100B is less than 2 microns, regardless of whether the trench 102 of the device region 100A and the trench 102 of the alignment region 100B are filled after the first epitaxial layer 103 is formed, as long as the trench 102 of the device region 100A and the trench 102 of the alignment region 100B are both filled after the second epitaxial layer 105 is formed.

[0027] Preferably, the hard mask 101 is shaped as an elongated strip with a width of no more than 8 microns, so that the alignment signal can be clearly identified.

[0028] In this embodiment, by using the hard mask 101 of the alignment region 100B as the alignment mark, the attenuation or disappearance of the alignment signal caused by the planarization process after epitaxy can be avoided, and since the overlay accuracy requirement of the alignment mark protection layer mask is low, the alignment error will not be affected, thus improving the process reliability.

[0029] Embodiment Two

[0030] Figures 8-13 Another preferred embodiment of the method for forming an alignment mark in a semiconductor process is shown.

[0031] As shown in Figure 8 , a semiconductor substrate 200 is provided, and a device region 200A and an alignment region 200B are defined (separated by a dashed line), and a trench 202 is formed in the device region 200A and the alignment region 200B simultaneously using a hard mask 201. Preferably, the material of the hard mask 201 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0032] As shown in Figure 9 , Figure 10 , a dielectric layer 206 and a polysilicon layer 207 are formed in the trench 202 of the device region 200A and the alignment region 200B, respectively, and the polysilicon layer 207 is planarized by chemical mechanical polishing and stopped on the surface of the hard mask 201. According to process requirements, a first epitaxial layer (not shown) can also be formed before the dielectric layer 206 is formed in the trench 202 of the device region 200A and the alignment region 200B.

[0033] As shown in Figure 11 , Figure 12 , the alignment region 200B is covered by a protection layer mask 204, so that when the hard mask 201 of the device region 200A is removed, the hard mask 201 of the alignment region 200B is retained, and then the protection layer mask 204 is removed.

[0034] As shown in Figure 13As shown, a second epitaxial layer 205 is formed in the device region 200A and the alignment region 200B respectively, and the second epitaxial layer 205 is planarized by chemical mechanical polishing. In a subsequent step not shown, semiconductor devices are formed in the second epitaxial layer 205 of the device region 200A.

[0035] Preferably, the difference between the width of the trench 202 in the device region 200A and the width of the trench 202 in the alignment region 200B is less than 2 microns, regardless of whether the trench 202 in the device region 200A and the trench 202 in the alignment region 200B are filled after the polysilicon layer 207 is formed, as long as the trench 202 in the device region 200A and the trench 202 in the alignment region 200B are both filled after the second epitaxial layer 205 is formed.

[0036] Preferably, the hard mask 201 is shaped as an elongated strip with a width of no more than 8 microns, so that the alignment signal can be clearly identified.

[0037] In the present embodiment, by using the hard mask 201 of the alignment region 200B as an alignment mark, the attenuation or disappearance of the alignment signal caused by the planarization process after epitaxy can be avoided, and since the alignment mark protection layer mask has low requirements for registration accuracy, the alignment error will not be affected, thus improving the process reliability.

[0038] In summary, in the method for forming an alignment mark in the semiconductor process of the present application, after the trenches are etched in the device region and the alignment region, the trenches are filled with an epitaxial layer and / or a polysilicon layer, and when the hard mask in the device region is removed, the hard mask in the alignment region is retained as an alignment mark by the protection layer mask, so that the attenuation or disappearance of the alignment signal caused by the planarization process after epitaxy can be avoided, and since the alignment mark protection layer mask has low requirements for registration accuracy, the alignment error will not be affected, thus improving the process reliability.

[0039] It is apparent for those skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and not restrictive. Moreover, it is apparent that the word "comprising" does not exclude other elements and steps, and the word "one" does not exclude plural. Multiple elements stated in the apparatus claims can also be implemented by one element. The words "first", "second", etc. are used to express names and do not indicate any particular order.

Claims

1. A method for forming alignment marks in a semiconductor process, characterized in that, include: Provides a semiconductor substrate, defines the device region and alignment region; Trenches are formed by simultaneously etching the device area and the alignment area using a hard mask; A first epitaxial layer and / or a polysilicon layer are formed in trenches in the device region and the alignment region, respectively; Remove the hard mask from the device area, and retain the hard mask from the alignment area; A second epitaxial layer is formed in the device region and the alignment region respectively, and a hard mask located below the second epitaxial layer in the alignment region is used as an alignment mark; Semiconductor devices are formed in the device region.

2. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The difference between the trench width in the device region and the trench width in the alignment region is less than 2 micrometers.

3. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, After the second epitaxial layer is formed, the trenches in the device region and the trenches in the alignment region are filled.

4. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The material of the hard mask includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

5. The method for forming alignment marks in a semiconductor process as described in claim 1, characterized in that, The hard mask is elongated and narrow, with a width not exceeding 8 micrometers.

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