Ultra-thin chip packaging substrate, chip packaging structure and chip packaging method

Abstract

The invention discloses a chip ultra-thin packaging carrier, a chip packaging structure and a chip packaging method. The carrier is a lead frame or a substrate, a base island for mounting a chip is formed in the carrier, at least one hollow area is formed in the base island, a half-etched area is formed at the edge of the hollow area, the half-etched area and the hollow area form a step shape, the half-etched area is used to fill a curing agent to mount the chip, the hollow area formed by the base island is located in the positive projection of the chip on the base island, the side of the hollow area where the chip is not mounted is used to fill a curing agent to bond the chip, the frame of the carrier is formed with a conductive pad, and the conductive pad is used to connect with the lead-out terminal of the chip. The present invention is applicable to all packaging types, can break through the existing chip thickness limit, mount ultra-thin chips through the half-etched area, further reduce the packaging thickness, and adopt the back-side glue brushing process to apply the curing agent to fill the hollow area, which can avoid the abnormality caused by the ultra-thin curing agent of the chip turning up to the front of the chip, improve the chip performance, and improve the yield rate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more specifically to an ultra-thin chip packaging carrier, a chip packaging structure and a chip packaging method. Background Art

[0002] With the rapid development of the semiconductor industry, the requirements for chip performance are getting higher and higher, power consumption is also increasing, the heat generated by the chip will increase, and the conductivity requirements are getting higher and higher. Therefore, the chip is required to be made thinner, and a high-conductivity adhesive with better thermal and electrical conductivity must be used. This is more conducive to heat dissipation and meeting the product's conductivity requirements, thereby improving product performance.

[0003] The current technical capabilities and solutions can only achieve a chip thickness of only about 75um, and can only be used for QFN (Quad Flat No-leads Package), LGA (Land Grid Array) and BGA (Ball Grid Array) packages, which is far from meeting the requirements of other types of packages, such as SOP (Small Out-Line Package), QFP (Quad Flat Package) and all other pin-type packages.

[0004] Because the chip is ultra-thin, the traditional lead frame or substrate using the traditional glue dispensing process can easily cause the silver glue to flip up to the chip surface and cause bridging between circuits, thus causing functional abnormalities and loss of product yield. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a chip ultra-thin packaging carrier, a chip packaging structure and a chip packaging method, which are suitable for all packaging types, can break the limit of existing chip thickness, avoid the abnormality caused by the ultra-thin chip curing agent turning up to the front of the chip, and improve the product yield.

[0006] According to one aspect of the present invention, there is provided a chip ultra-thin packaging carrier, wherein the carrier is a lead frame or a substrate, a base island for mounting a chip is formed in the carrier, at least one hollow area is formed in the base island, a semi-etched area is formed at the edge of the hollow area, the semi-etched area and the hollow area form a step shape, the semi-etched area is used to fill a curing agent to mount the chip, the hollow area formed by the base island is located within the orthographic projection of the chip on the base island, the side of the hollow area where the chip is not mounted is used to fill a curing agent to bond the chip, and a conductive pad is formed on the frame of the carrier, and the conductive pad is used to be connected to the lead-out end of the chip.

[0007] In some embodiments, the half-etched region is roughened to form a roughened surface layer.

[0008] In some embodiments, the depth of the half-etched region is greater than or equal to 20 μm.

[0009] In some embodiments, the width of the half-etched region is greater than or equal to 100 μm.

[0010] According to another aspect of the present invention, a chip packaging structure is provided, including the above-mentioned chip ultra-thin packaging carrier, the semi-etched area on the front side of the carrier is mounted with a chip through curing agent 1, curing agent 2 is applied to the back side of the carrier, curing agent 2 is filled in the hollow area, curing agent 1 and curing agent 2 100% cover the back side of the chip, and the lead end of the chip is connected to the conductive pad of the carrier through a welding wire.

[0011] In some embodiments, the carrier is covered with a molding compound or a ceramic cover to protect the chip and the bonding wires connecting the lead-out terminals of the chip and the conductive pads.

[0012] According to another aspect of the present invention, a chip packaging method is provided, using the above chip packaging structure, the method comprising the following steps:

[0013] S01: forming a hollow area on the base island of the carrier, forming a half-etched area at the edge of the hollow area, and the half-etched area and the hollow area form a step shape;

[0014] S02: Apply curing agent 1 to the half-etched area of ​​the base island;

[0015] S03: mounting the chip on the half-etched area of ​​the base island so that the hollow area formed by the base island is located within the positive projection of the chip on the base island, and the curing agent makes the chip and the base island of the carrier bonded, and the lead-out end of the chip is connected to the conductive pad of the carrier through the welding wire;

[0016] S04: Flip the carrier as a whole, and evenly apply curing agent 2 on the back of the carrier by brushing glue. Curing agent 2 is filled in the hollow area to combine curing agent 2 with the chip and the base island. The back of the chip is 100% covered with curing agent 1 and curing agent 2, and curing agent 1 and curing agent 2 will not contaminate the front of the chip.

[0017] In some embodiments, after the half-etched region is formed, the half-etched region is roughened to improve the bonding force between the curing agent 1 and the base island.

[0018] In some embodiments, after the second curing agent is combined with the chip, a plastic encapsulation material or a ceramic cover is used to cover the carrier to protect the chip and the bonding wires connecting the lead-out terminals of the chip and the conductive pads.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention provides an ultra-thin chip packaging carrier and a chip packaging structure realized by using the carrier. The lead frame or substrate (i.e., carrier) of any packaging type can mount the ultra-thin chip through the half-etched area, which can reduce the thickness of the package and break through the limit of the thickness of the existing chip. The chip thickness can be 20 μm or even thinner. After the chip is mounted and fixed, the whole is turned over and a curing agent 2 is applied on the back of the carrier by a brushing process. The curing agent 2 fills the hollow area for heat dissipation and conduction, so that the curing agent 2 is combined with the chip and the base island to complete the chip packaging method adopted by the chip packaging structure. The curing agent is filled by brushing glue on the back side, which can ensure that the curing agent coverage rate of the chip contacting reaches 100%, and the front side of the chip will not be contaminated due to the ultra-thin curing agent of the chip turning up to the front side of the chip, thereby improving the chip performance and the packaging yield rate. The carrier can be covered with a plastic packaging material or a ceramic cover to protect the chip and the welding wires connected between the lead-out end of the chip and the conductive pad, so as to avoid the adverse effects of the external environment on the chip and the welding wires. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of an embodiment of an ultra-thin chip packaging carrier of the present invention;

[0021] Figure 2 It is a structural schematic diagram of an implementation mode of a chip packaging structure of the present invention;

[0022] Figure 3 It is a structural schematic diagram of an implementation mode of a chip packaging structure of the present invention;

[0023] Figure 4 It is a schematic flow chart of an implementation method of a chip packaging method of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] like Figures 1 to 3As shown, an embodiment of the present invention provides a chip ultra-thin packaging carrier, and the carrier 110 can be a lead frame or a substrate. A base island 120 is formed in the carrier 110, and the base island 120 is used to mount the chip 210. A hollow area 122 is formed in the base island 120. On the base island 120, a half-etched area 121 is formed at the edge of the hollow area 122, and the half-etched area 121 and the hollow area 122 form a step shape, and the half-etched area 121 is used to fill the curing agent 1 220 to mount the chip 210. The hollow area 122 formed by the base island 120 is located in the positive projection of the chip 210 on the base island 120, and the side of the hollow area 122 where the chip 210 is not mounted is used to fill the curing agent 221 to bond the chip 210. A conductive pad 111 is formed on the frame of the carrier 110, and the conductive pad 111 is used to connect with the lead-out end of the chip 210.

[0027] The curing agent 1 220 and the curing agent 2 221 can both be made of high-conductivity glue, or other colloids can be used.

[0028] The half-etched area 121 and the hollow area 122 can be formed by cutting or etching so that the carrier 110 has the above structure, which is not limited here. The area of ​​the hollow area 122 accounts for a large proportion of the surface of the base island 120, and the heat dissipation effect of the chip 210 can be increased to a large extent through the hollow area 122. The main function of the hollow area 122 is to evenly apply the curing agent 221 on the back of the base island 120 by the back glue brushing process. When the curing agent 221 is filled in the hollow area 122, the curing agent 221 is combined with the chip 210 and the base island 120. By using this structure, it can be ensured that the coverage rate of the colloid contacting the back of the chip 210 reaches 100% and will not contaminate the front of the chip 210, avoiding the problem of bridging between circuits caused by the colloid turning up to the surface of the chip 210 due to the ultra-thin chip 210 using the traditional glue dispensing process, avoiding functional abnormalities, thereby improving the performance of the chip 210 and improving the packaging zero rate.

[0029] It should be noted that there may be one or more hollow areas 122 formed in the base island 120, and one or more chips 210 may be placed therein. The shape of the half-etched area 121 needs to be consistent with the outline of the chip 210, and the size of the half-etched area 121 needs to be slightly larger than the outline of the chip 210. Generally, the size of the half-etched area 121 is greater than or equal to 10 μm, 25 μm, 38 μm or 50 μm larger than the outline of the chip 210, and the specific selection is customized according to the actual machine capacity.

[0030] Optionally, the width of the half-etched area 121 is greater than or equal to 100μm, such as 100μm, 110μm, 120μm, etc., which can facilitate glue dispensing before mounting the chip 210, that is, dispensing the curing agent 220 to facilitate the bonding of the back side of the chip 210 near the edge with the half-etched area 121 of the base island 120.

[0031] Optionally, the depth of the half-etched area 121 is greater than or equal to 20μm, such as 20μm, 21μm, 22μm, etc., and the chip 210 is mounted using the half-etched area 121, so that the thickness of the chip 210 after packaging can be thinner. In addition, the downwardly recessed half-etched area 121 is also conducive to the positioning of the chip 210 during mounting.

[0032] In order to increase the bonding strength between the cured adhesive 1 and the base island 120, the half-etched area 121 is roughened to form a roughened surface layer (not shown).

[0033] Another aspect of an embodiment of the present invention provides a chip packaging structure, including the above-mentioned chip ultra-thin packaging carrier, the semi-etched area 121 on the front side of the carrier 110 is mounted with the chip 210 through the curing agent 220, the curing agent 220 is dispensed onto the semi-etched area 121, the curing agent 221 is applied to the back side of the carrier 110, the curing agent 221 is filled in the hollow area 122, the curing agent 1 220 and the curing agent 2 221 100 cover the back side of the chip 210, and the lead end of the chip 210 is connected to the conductive pad 111 of the carrier 110 through the welding wire 310.

[0034] After the chip 210 is bonded to the carrier 110 , a plastic package or a ceramic cover or other packaging technology can be used to protect the chip 210 and the bonding wires 310 connecting the lead ends of the chip 210 and the conductive pads 111 to prevent the external environment from causing adverse effects on the chip 210 or the bonding wires 310 .

[0035] Another aspect of the embodiments of the present invention provides a chip packaging method, using the above chip packaging structure, the above packaging structure is SOP (Small Out-Line Package, small outline pin package) packaging, such as Figures 2 to 4 As shown, the method comprises the following steps:

[0036] S01: forming a hollow area 122 on the base island 120 of the carrier 110, and forming a half-etched area 121 at the edge of the hollow area 122, so that the half-etched area 121 and the hollow area 122 form a step shape.

[0037] After the half-etched area 121 is formed, the half-etched area 121 is roughened to improve the bonding force between the curing agent 220 and the base island 120 in the subsequent process.

[0038] S02: dispensing a curing agent 220 in the half-etched area 121 of the base island 120 through a dispensing process.

[0039] S03: The front side of the ultra-thin chip 210 is mounted on the half-etched area 121 of the base island 120 after the glue is dispensed, so that the hollow area 122 formed by the base island 120 is located within the positive projection of the chip 210 on the base island 120. The lead-out end of the chip 210 is correspondingly connected to the conductive pad 111 of the carrier 110 through the welding wire 310. The colloid is cured, and the curing agent 220 makes the chip 210 bonded to the base island 120 of the carrier 110.

[0040] S04: The carrier 110 is turned over 180° as a whole, and the curing agent 221 is evenly applied to the back of the carrier 110 by brushing glue. The curing agent 221 fills the hollow area 122, and the back of the chip 210 is 100% covered with the curing agent 1 220 and the curing agent 2 221, and the curing agent 1 220 and the curing agent 2 221 will not contaminate the front of the chip 210. The colloid is cured to combine the curing agent 221 with the chip 210 and the base island 120.

[0041] After the curing agent 221 is combined with the chip 210, the carrier 110 is covered with a plastic packaging material or a ceramic cover. Other packaging technologies can also be used according to actual product requirements to protect the chip 210 and the welding wire 310 connecting the lead end of the chip 210 and the conductive pad 111 to prevent the external environment from causing adverse effects on the chip 210 or the welding wire 310.

[0042] The present invention provides an ultra-thin chip packaging carrier and a chip packaging structure realized by using the carrier 110. The carrier 110 and the structure are applicable to all packaging types, including pinless packaging and pinned packaging. The lead frame or substrate (i.e., carrier 110) of any packaging type can be mounted with an ultra-thin chip 210 through the half-etched area 121, which can reduce the thickness of the package and break through the thickness limit of the existing chip 210. The thickness of the chip 210 can be 20 μm or even thinner. After the chip 210 is mounted and fixed, it is flipped over as a whole and a curing agent 221 is applied to the back of the carrier 110 by a brushing process. The curing agent 221 fills the hollow area 122 for heat dissipation and conduction, so that the curing agent 221 is combined with the chip 210 and the base island 120 to complete the chip packaging method adopted by the chip packaging structure. The curing agent is filled by brushing glue on the back to ensure that the curing agent coverage rate of the chip 210 is 100%, and the front of the chip 210 will not be contaminated due to the ultra-thin curing agent of the chip 210 turning up to the front of the chip 210, thereby improving the performance of the chip 210 and the packaging yield. The carrier 110 may be covered with a plastic packaging material or a ceramic cover to protect the chip 210 and the bonding wires 310 connecting the lead-out terminals of the chip 210 and the conductive pads 111 , thereby preventing the chip 210 and the bonding wires 310 from being adversely affected by the external environment.

[0043] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other modifications and improvements can be made without departing from the creative concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A chip ultra-thin packaging carrier, characterized in that: The carrier is a lead frame or a substrate, a base island for mounting a chip is formed in the carrier, at least one hollow area is formed in the base island, a half-etched area is formed at the edge of the hollow area, the half-etched area and the hollow area form a step shape, the half-etched area is used to fill curing agent 1 to mount the chip, which can reduce the packaging thickness, the hollow area formed by the base island is located in the positive projection of the chip on the base island, the side of the hollow area where the chip is not mounted is used to fill curing agent 2 to bond the chip, so that curing agent 1 and curing agent 2 can cover the back of the chip 100% and curing agent 1 and curing agent 2 will not turn up and pollute the front of the chip, and the frame of the carrier is formed with a conductive pad, which is used to connect with the lead-out end of the chip.

2. The ultra-thin chip packaging substrate according to claim 1, characterized in that: The half-etched area is roughened to form a roughened surface layer.

3. The ultra-thin chip packaging carrier according to claim 2, characterized in that: The depth of the half-etched area is greater than or equal to 20 μm.

4. The ultra-thin chip packaging carrier according to claim 3, characterized in that: The width of the half-etched area is greater than or equal to 100 μm.

5. A chip packaging structure, characterized in that: It comprises the chip ultra-thin packaging carrier as described in any one of claims 1 to 4, the chip is mounted on the semi-etched area on the front side of the carrier through curing agent 1, curing agent 2 is applied to the back side of the carrier, the curing agent 2 is filled in the hollow area, the curing agent 1 and curing agent 2 cover the back side of the chip 100%, and the lead end of the chip is connected to the conductive pad of the carrier through a welding wire.

6. The chip packaging structure according to claim 5, characterized in that: The carrier board is covered with a plastic packaging material or a ceramic cover to protect the chip and the bonding wires connecting the lead-out terminals of the chip and the conductive pads.

7. A chip packaging method, characterized in that: Using the chip packaging structure as claimed in claim 5, the method comprises the following steps: S01: forming a hollow area on the base island of the carrier, and forming a half-etched area at the edge of the hollow area, wherein the half-etched area and the hollow area form a step shape; S02: Apply curing agent 1 to the half-etched area of ​​the base island; S03: mounting a chip on the half-etched area of ​​the base island so that the hollow area formed by the base island is located within the orthographic projection of the chip on the base island, and using a curing agent to bond the chip to the base island of the carrier, and the lead-out end of the chip is correspondingly connected to the conductive pad of the carrier through a welding wire; S04: Flip the carrier as a whole, and evenly apply curing agent 2 on the back of the carrier by brushing glue. The curing agent 2 is filled in the hollow area to combine the curing agent 2 with the chip and the base island. The back of the chip is 100% covered with curing agent 1 and curing agent 2, and curing agent 1 and curing agent 2 will not contaminate the front of the chip.

8. The chip packaging method according to claim 7, characterized in that: After the half-etched area is formed, the half-etched area is roughened to improve the bonding force between the curing agent 1 and the base island.

9. The chip packaging method according to claim 7, characterized in that: After the second curing agent is combined with the chip, a plastic packaging material or a ceramic cover is used to cover the carrier board to protect the chip and the bonding wires connecting the lead-out terminals of the chip and the conductive pads.

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