Combining the traveling wave carry adder with the routable propagation / generation signal to build the dynamic block size carry jump adder on FPGA

Abstract

The invention relates to an adder implemented in a field programmable gate array (FPGA). The adder has a first ripple-carry adder block for the least significant bits of the adder. The adder has a plurality of carry-skip adder blocks of different block sizes. Each block size is related to the bit width of the input to the block. The carry-skip adder blocks of different block sizes are used for a plurality of bits of the adder. The adder has a second ripple-carry adder block for the most significant bits of the adder.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63144875, filed February 2, 2021, entitled "DYNAMICBLOCK SIZE CARRY-SKIP ADDER CONSTRUCTION ON FPGAS BY COMBINING RIPPLE CARRYADDERS WITH ROUTABLE PROPAGATE / GENERATE SIGNALS", which is incorporated herein by reference. Background Technology

[0003] Addition is common in digital design, so modern FPGAs have dedicated circuitry for implementing this function. Unlike using a pure lookup table (LUT) to implement addition, FPGAs typically add dedicated circuitry for efficiently implementing adders. Generally, full adders (e.g., each with inputs A, B and carry inputs, and outputs carry and sum) are connected in one of two ways to implement a wider range of adders.

[0004] A simple way to implement wider adders is to directly add a dedicated route from the carry output of a full adder to the carry input of another full adder. This can be used to implement a fast ripple carry adder (RCA). The critical path through a ripple carry adder is dominated by the ripple carry path, which grows linearly with the width of the adder, which is related to the bit width of the adder inputs and the bit width of the adder outputs. This type of adder is generally quite fast when designed to add low bit widths, but can become quite slow for high bit widths due to the long delay caused by the lengthy ripple carry path.

[0005] Another option for implementing wider adders in an FPGA is to add a dedicated carry-lookahead adder (CLA) circuit with a fixed block size (K) to the group of logic blocks. The block size is related to the width of the block, or bit width, and more specifically, to the bit width of the block's inputs and / or outputs. This carry-lookahead adder circuit is used to pre-calculate whether a set of full adders of size K will ignore incoming carry inputs, propagate incoming carry inputs, or generate carry outputs, regardless of the carry input value. This CLA circuit accelerates the ripple path, and its critical path is linearly related to the number of bits / K. The choice of K is a trade-off that FPGA architects must make in advance. A larger K value will provide better performance for the wider adder but will result in a higher fixed area penalty.

[0006] Other work has shown that LUTs and adders on FPGAs can be used to implement complex parallel prefix adders, which can be faster for very high bit widths. However, due to the lack of architectural support for these structures, implementing this in a typical FPGA results in a large area overhead. SUMMARY

[0007] Embodiments described herein implement a class of fast carry-skip adders using a combination of existing RCA adder circuits modified to make the propagate and generate signals routable with soft logic. The techniques described herein allow fast carry-skip adders with variable block sizes to be created with minimal architectural modifications. In one embodiment, the architectural modifications do not dictate the block size, so the block size of the adder is determined at compile time as a tradeoff between area and speed. Larger block sizes result in higher area overhead, while smaller block sizes result in lower area overhead. For low bit-width adders, standard RCA can be implemented to avoid any soft logic area overhead.

[0008] One embodiment disclosed herein is an adder implemented in a field programmable gate array (FPGA). The adder has a first row of ripple-carry adder blocks for least significant bits of the adder. The adder has a plurality of carry-skip adder blocks having different block sizes. Each block size is related to a bit width input to the block. The plurality of carry-skip adder blocks are for a plurality of bits of the adder. The adder has a second row of ripple-carry adder blocks for most significant bits of the adder.

[0009] One embodiment disclosed herein is a computer-aided design (CAD) method implemented by a CAD system. The method includes receiving instructions to implement an adder in a field programmable gate array (FPGA), and generating the adder in a format for programming the FPGA. The adder includes a first row of ripple-carry adder blocks for least significant bits of the adder. The adder includes a plurality of carry-skip adder blocks having different block sizes for a plurality of bits of the adder. Each block size is related to a bit width input to the block. The adder includes a second row of ripple-carry adder blocks for most significant bits of the adder.

[0010] One embodiment disclosed herein is a tangible, non-transitory computer readable medium having instructions thereon. When the instructions are executed by a processor, the processor is caused to perform a method. The method includes receiving instructions to implement an adder in a field programmable gate array (FPGA), and programming the FPGA to implement the adder. The adder includes a first row of ripple carry adder blocks for least significant bits of the adder. The adder includes a plurality of carry-skip adder blocks having different block sizes. Each block size is related to a bit width of input to the block. The plurality of carry-skip adder blocks are for a plurality of bits of the adder. The adder includes a second row of ripple carry adder blocks for most significant bits of the adder.

[0011] In one embodiment, the area / speed tradeoff can be decided in the following manner:

[0012] 1) Use global options by the user to improve and possibly optimize the area or speed of the entire design;

[0013] 2) Use a parameterized adder IP core which the user can configure to be more area or speed biased;

[0014] 3) Use physical synthesis techniques to start from an area optimized adder and then modify the block size to target speed for only the adders on the critical path.

[0015] The adder embodiments disclosed herein have one or more of the following advantages compared to using hard carry lookahead adders:

[0016] • Reduced and possibly minimal area overhead compared to a simple RCA, hence smaller FPGA die size compared to implementing a carry lookahead adder circuit.

[0017] • Critical path delay varies sub-linearly as the block size can be increased with increasing length of the carry chain.

[0018] • Variable block size can be used to provide superior performance advantage over a wide range of bit widths.

[0019] • No need for clustered FPGA architecture. BRIEF DESCRIPTION OF DRAWINGS

[0020] The embodiments described herein will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which various embodiments of the application are shown. However, the drawings represent illustrative embodiments only and should not be construed as limiting the application.

[0021] Figure 1 A standard full adder implemented using 4-LUTs and additional 2:1 carry ripple multiplexers is shown.

[0022] Figure 2 An embodiment of a K=2 carry-skip adder block is shown.

[0023] Figure 3 An embodiment of a K=4 carry-skip adder block is shown.

[0024] Figure 4 An embodiment of a K=16 carry-skip adder block is shown.

[0025] Figure 5 An embodiment of a faster K=16 carry-skip adder block is shown.

[0026] Figure 6 Building a carry-skip adder using a combination of block sizes to hide general routing delays is shown.

[0027] Figure 7 Selecting variable block sizes to optimize overall adder delay is shown.

[0028] Figure 8 An embodiment of a computer-aided design (CAD) system implementing various embodiments of adders according to the present disclosure is shown. DETAILED DESCRIPTION

[0029] In the following description, numerous specific details are set forth to provide a more thorough explanation of the embodiments. However, it will be apparent to one of ordinary skill in the art that the embodiments can be practiced without the specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments.

[0030] Described herein are techniques for creating a class of fast carry-skip adder structures on FPGAs with lower area overhead than ordinary ripple carry adders (RCAs) that use a modified version of the standard hard RCA, exploiting a propagating and generating signal driven routing structure.

[0031] Figure 1 An embodiment of a 4-LUT (four-level lookup table) 104 is shown broken down to implement the propagate 110, generate 108, and sum 106 functions. In various embodiments, a lookup table is a block in an FPGA that has multiplexers arranged in multiple levels. Some embodiments of general lookup tables and some embodiments of specific 4-LUTs, as blocks within blocks, have half-adders, e.g., each with inputs A and B and outputs carry and sum. See Figure 1The lower half of the 4-LUT is used to create the propagate 110 and generate 108 signals, which both use inputs A and B. The sum 106 is implemented as a 3-LUT using the upper half of the 4-LUT 104, and has inputs 118, 120, 122A / B / Cin. An additional 2: 1 multiplexer 116 (i.e., multiplexer) is used to generate the carry out signal. If the propagate 110 signal (optionally, propagate carry) is asserted, then the multiplexer 116 selects the carry in (Cin) 112 signal for the carry out (Cout) 114. Otherwise, the multiplexer 116 selects the generate 108 signal (optionally, generate carry) for the carry out (Cout) 114.

[0032] In some embodiments, the full adder implemented using the 4-LUT 104 in Figure 1 operates in the following manner. The operands A and B, which are inputs to the adder, are loaded into the SRAM (static random access memory) 102. The first stage multiplexer of the 4-LUT 104, controlled by input A 118, selects the value of "A" from the SRAM 102 to propagate to the second stage multiplexer of the 4-LUT 104. The second stage multiplexer of the 4-LUT 104, controlled by input B 120, selects from the value propagated by the first stage multiplexer, and produces the generate 108 (or generate carry), propagate 110 (or propagate carry), and a value to propagate to the third stage multiplexer to generate the sum 106. In the third stage multiplexer of the 4-LUT 104, one of the multiplexers is controlled by the carry in (Cin) 122, and selects from the value propagated by the second stage multiplexer, thereby generating the sum 106. The propagate 110 controls the multiplexer 116 to select either the carry in 122 or the generate 108, depending on the value of the propagate 110, for the carry out 114. In this example, the multiplexers in the fourth stage of the 4-LUT 114 are not used.

[0033] Figure 2 One embodiment of a carry-skip block with a block size 202K = 2 implemented using the proposed architecture is shown. To maintain consistency with the block size 202, the bit width of each of the inputs "a" (e.g., al, a0) and "b" (e.g., bl, b0) and the outputs (e.g., suml, sum0) is 2. Referring to Figure 2 , the sum (e.g., suml, sum0) is normally generated from the full adders 216 and 218 on the left. The propagate (Prop) 210 is generated using a single 4-LUT (see, e.g., Figure 1) generated as it is a function of the inputs a0, a1, b0, b1. Block generate (Block_Generate) 208 is the carry out from the 2-bit carry ripple, the carry in routing (Cin_routing) 204 from the propagation through block 214 and two full adders 216, 218. Note that if Propagate (Prop) 210 is false, then Block generate (Block_Generate) 208 does not depend on the direct carry in (Cin_direct) 206, which is the only case in which Block generate (Block_Generate) 208 is selected by multiplexer 222 for carry out 212, which then goes out of the block as both the direct carry out (Cout_direct) and the carry out routing (Cout_routing). Thus, the carry in (Cin) is routed to prevent false generation. Block generate (Block_Generate) 208 and Propagate (Prop) 210 are then routed to another full adder block (not shown, but easily envisioned) using general routing. This other full adder block implements block ripple carry. The carry skip block pre-computes the carry propagate and carry generate signals for the group, so that the carry does not have to ripple through all the full adder blocks within the carry skip block.

[0034] Figure 3 One embodiment of a carry skip block with block size 302 implemented with the proposed architecture for K = 4 is shown. This is similar to the embodiment in Figure 2 , except that the input and output sums are four bits wide to be consistent with the block size 302, there are four one-bit wide full adders 316, 318, 320, 322, and the propagate signal from each individual full adder of the adders 316, 318, 320, 322 from the left is ANDed by AND block 324 to generate propagate 306. This method of generating propagate 306 using wide AND gate logic saves area for K > 2. The carry in routing 304, direct carry in 310, carry out 312 generated by multiplexer 326 to be the direct carry out and carry out routing, and the carry out 312 from the left adder 316, 318, 320, 322 by block 314 and full adder propagation to produce block generate 308 are also similar to the embodiment in Figure 2 .

[0035] Figure 4 One embodiment of a carry skip block with block size 402 implemented with the proposed architecture for K = 16 is shown. Note that this is similar to the embodiment in Figure 3In contrast, there is an extra stage of 4-LUTs arranged as AND gate 418 connected to AND gate 420 to AND the propagate signals from the sixteen one-bit wide full adders 416 on the left. This method of generating the propagate 408 using wide AND gate logic saves area for K = 16. The carry-in routing 404, direct carry-in 410, carry-out 412 generated by multiplexer 422 to route the direct carry-out and carry-out of block generation 406 by block 414 and full adder propagation are also similar to the embodiments in Figure 2 and Figure 3 .

[0036] Figure 5 An embodiment is shown that generates the block generation 508 signal by using a rippling carry adder 516 to implement the wide AND function. By modifying the LUTMASK (Lookup Table Mask) of the LUTs in the rippling path, the function can be changed from an adder to a bitwise AND. Figure 5 An embodiment is shown of a carry skip block with a block size 502 of K = 16, which has a faster carry skip block architecture than the embodiment shown in Figure 4 . The block generation 508 is produced by the wide AND function of the rippling carry adder 516. The block propagate 506 is produced by block 518. The direct carry-in 510, carry-out 512 generated by multiplexer 520 to route the direct carry-out and carry-out are also similar to the embodiments in Figure 2 , Figure 3 and Figure 4 .

[0037] Referring to the carry skip adder embodiment in Figures 2-5 , any number of lookup tables with half adders can be connected together to generate the group carry propagate for a block that handles any number of bits, in practice of course limited by device size. Figures 2-5How the block carry generation and block carry propagation are created is shown. Block carry generation decides whether to generate a carry output regardless of the carry input value. Also, block carry propagation decides whether to propagate a group carry input to a carry output. This is referred to as soft logic, and to implement this logic in the adder embodiment, the carry propagation is accessed through regular routing, which can not typically be the case in FPGA architectures outside of this embodiment. In some embodiments, the carry propagation signal comes from the internal circuitry of the half-adder and is exposed to external routing (i.e., routing outside of the half-adder), for example, as an output port of a lookup table or logic block. In the carry-skip adder embodiment, the carry propagation signal of each K-sized carry-skip adder block enters one bit of the carry chain that serves as a group carry chain. Also, the carry generation signal comes from the internal circuitry of the half-adder and is exposed to external routing and enters the same bit of the carry chain (see Figures 1-5 the multiplexer in generates the carry output). Because of this architecture, the critical path is from the carry input to the carry output, which can be very fast, especially for the hard logic of that one bit of the carry chain. Hard logic here refers to a dedicated, fast circuit, as opposed to a circuit made up of other programmable, configurable elements. In contrast, soft logic here refers to programmable, configurable logic that can be used to build logic circuits to implement a particular function by programming the FPGA. Exposing the carry propagation signal and the carry generation signal from inside the block allows the construction of the carry-skip adder. Specialized, specific size multiplexers are used in various embodiments, for example, for the hard logic, although in further embodiments, specialized, specific size combinational logic can be used. The use of hard logic, for example, specific multiplexers, in the critical path of the carry allows the group carry wave to pass through the hard logic, which is very fast compared to soft logic.

[0038] Figure 6 The delay of the created block generation / propagation signals is hidden by starting and ending the carry-skip adder with a regular RCA is shown. This means that the delay of one embodiment of the variable block size carry-skip adder can never be slower than a regular RCA. Figure 6 An embodiment is shown of an adder made up of a ripple carry adder 604 (shown here as having two or more one-bit wide adders) for the least significant bits of the input and output, two carry-skip adders 608, 610 of block size K = 4 for the middle bits of the input and output, and a ripple carry adder 604 (shown here as having two or more one-bit wide adders) for the most significant bits of the input and output. In Figure 6In the example shown, even though there are 5 LUTs in a block, it is a K=4 block because the first LUT is only used to route the carry-in from the general purpose logic to the dedicated carry path to the adder. That is, the topmost LUT does not implement a full adder. The critical path 602 for the adder carry-in propagates through ripple carry adder 604, carry-skip adder 608, 610, and ripple carry adder 606. However, because the carry logic in the carry-skip adders is relatively fast, the critical path 602 is faster than the critical path for the carry-in of a similar size ripple carry adder implemented in the same technology, e.g., in an FPGA. In other words, all else being equal (e.g., technology, circuit delay of given elements, bit width), the carry-in of an adder implemented with the variable block size carry-skip adder architecture shown is faster than the carry-in of a similar size ripple carry adder implemented in the same technology. Figure 6 The architecture of the variable block size carry-skip adder shown, along with the ripple carry adders for the least significant bits and the most significant bits, produces a faster carry-in on the critical path 602 than a ripple carry adder. These features are generalized in further embodiments of the adder with various widths of ripple carry adders and various widths and corresponding block sizes of the carry-skip adder blocks.

[0039] Figure 7 The optimal block size of the dynamic carry-skip adder is shown to reduce and possibly minimize the critical path delay. It is noted that in one embodiment, the block size of the carry-skip adder block 702 is selected to compute the maximum number of adder bits that can be computed in a given stage or block of the adder without creating a critical path in the propagation / generation logic of the carry-skip adder block 702 that would slow down the carry propagation in the critical path 704 of the adder carry-in.

[0040] In Figure 7 In the embodiment shown, the block size of the carry-skip adder block 702 increases from K=2 at the lower significant bit end of the carry-skip adder block 702 to K=6 at the middle bits of the adder and decreases from the middle bits of the adder to K=2 at the higher significant bit end of the carry-skip adder block 702. This feature is generalized in further embodiments of the adder with various block size values and various increments and decrements in the block size of the adder implemented.

[0041] In one embodiment, in terms of block size selection, the user can select the adder structure by starting with an area-optimized adder that the user can instantiate in their design using physical synthesis techniques (e.g., the user can specify parameters that control the adder structure), then modifying the block size to parameterize the adder module for target speed of the adder on the critical path by specifying whether the CAD tool should focus more on area or performance (which is a global option that impacts the entire design), and selecting the adder structure.

[0042] Thus, as described above, a carry-skip adder structure is efficiently implemented on an FPGA using a mix of hard resources and soft logic / routing. Within the scope of embodiments are at least the following features, as well as the ability of a CAD system to generate adder implementations with various combinations of these features.

[0043] • An adder structure that uses routing to propagate and generate signals from adder logic to create a carry-skip adder structure.

[0044] • An adder structure that has a variable carry-skip block size to hide routing delays associated with generating group propagation and generating signals.

[0045] • An adder structure that has a custom block size in the adder structure to trade off performance versus adder area.

[0046] • An adder structure that includes a rippling carry structure that generates a wide AND gate logic for fast block propagation generation.

[0047] An adder structure has two or more of the foregoing features.

[0048] Various embodiments have further features in various combinations as follows.

[0049] • A lower critical path delay for a carry for an adder compared to a critical path delay for a rippling carry adder with the same overall input bit width as the adder that can be implemented in an FPGA.

[0050] • A lower area for an adder in an FPGA compared to an area for a carry-skip adder that can be implemented in an FPGA that consists of carry-skip adder blocks with a fixed block size that is equal to the largest of different block sizes.

[0051] Figure 8One embodiment of a computer-aided design (CAD) system 802 that implements various embodiments of adders according to the present disclosure is shown. A CAD tool 804 executing on a processor 806 receives instructions for an adder 808, e.g., in an appropriate format (e.g., a file in RTL, i.e., register transfer language, Verilog, or VHDL coding, etc.) for the CAD tool 804 from a user. The CAD tool 804 generates an adder implementation 812 using, e.g., a parameterized adder module 810 output in an appropriate format for programming an FPGA. The CAD system 802 or other system can then program an FPGA, resulting in a programmed FPGA 814 with the adder implementation 812. In various embodiments, various aspects and features of the above-described embodiments are automated by the CAD tool 804 or by a user in conjunction with the CAD tool 804. In further embodiments, various aspects and features of the above-described embodiments are further applied in various combinations to other types of integrated circuits, and CAD tools and CAD systems for other types of integrated circuits, e.g., full custom, ASIC (application specific integrated circuit), PLD (programmable logic device), etc.

[0052] In various embodiments, in a hierarchical structure with blocks within blocks, the entire adder is synthesized as one block. For example, if a 32-bit adder is instructed to be implemented, the CAD tool 804 creates all block sizes for creating a ripple-carry version of the adder. In some embodiments, the CAD tool 804 explores tradeoffs, e.g., the larger the block size, the longer it takes to create groups, generate and propagate signals. Returning to the example of a 32-bit adder, the CAD tool 804 can split the design into four eight-groups or eight four-groups and analyze the critical path, then select which of the two possibilities is best for carry timing. The CAD tool 804 can determine the timing for a four-bit ripple-carry adder and compare the timing for a four-bit carry-skip adder. This comparison can be made for various stage of the adder, with different block size combinations.

[0053] It has been found that as the size and width of an adder increases, the time to compute a carry changes in a sub-linear manner. Also, comparing critical paths of ripple-carry adders, the time to compute a carry is linear with the width of the adder. Thus, it has been found that below a certain bit width, a ripple-carry adder is the fastest. Such a bit width can be used as a threshold in the CAD tool 804. For adders instructed to be implemented with a bit width below or equal to the threshold, the CAD tool 804 can implement a ripple-carry adder. Greater than that bit width, the CAD tool 804 can implement a ripple-carry adder at the beginning and end, i.e., one ripple-carry adder for the low bits, another ripple-carry adder for the high bits, and either a carry-skip adder or multiple carry-skip adder blocks with different block sizes for the middle bits.

[0054] At the start, the CAD tool 804 can start with a small block size, for example, a block size of 2. There is an additional threshold, analytically, at which it makes sense to increase the block size of the next block and still be below the delay to keep up with the wavefront through the critical path of the carry. This is the implication of hiding the general routing delay in various embodiments. The delay of the carry generation and carry propagation signals for a given carry jump adder module is compared to the delay on the critical path of the carry for the assembled adder, and then from that comparison, an acceptable block size for the carry jump adder module (and the secondary critical delay of the block carry generation and block carry propagation signals) is determined.

[0055] At some point, for example, about halfway through the adder, adding a large block can create a new critical path to generate and bit. Adding a smaller block, which takes less delay to generate the later or last bit of the adder, avoids this new critical path. The CAD tool 804 can proceed in this direction, making smaller block sizes toward the more efficient bit generation of the adder. Then, another wavefront carry adder can be used to implement the final bit of the adder, which will be faster than another carry jump adder block. Past the middle of the adder, the CAD tool 804 can create smaller block sizes and keep reducing the block size because there is less delay to hide at the end of the wavefront.

[0056] Some embodiments of the CAD tool 804 balance the delay through the wavefront and the delay in the block carry generation and block carry propagation signals in the carry chain to optimize the block size of the adder implemented with variable block sizes. Using a larger block size means there are fewer wavefront stages in the critical path of the carry, which speeds up the carry propagation, but slows down the sum generation.

[0057] One embodiment of the CAD tool 804 looks at each bit of the adder and determines how to compute the sum of the next group of bits, for example, this will be one bit at a time, two bits at a time, three bits, or four bits at a time, etc. There are two factors that determine, one is that there is enough delay to generate the group generation signal earlier than the delay that has accumulated so far in the critical path of the carry. The other factor is to take into account the generation of the sum bits in the case of a wavefront through the general routing of the links. It is acceptable to slow down some signals because they are not in the critical path, which determines how large the block size can be. There are outward constraints and input constraints. At the more efficient bit end of the adder, the sum bits can be slowed down and become critical. From an algorithmic perspective, one judgment is whether it creates a new critical path by generating a block, and if so, try a smaller block.

[0058] Some portions of the above detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. These algorithmic descriptions and representations are generally

[0059] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system memories or registers into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0060] The present application also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a bus via a wire or cable, a wireless link, or any other suitable access method.

[0061] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will appear from the description below. In addition, the present application is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the application as described herein.

[0062] Machine-readable media includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media includes read-only memory ("ROM"); random access memory ("RAM"); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); etc.

[0063] While numerous changes and modifications will no doubt come to mind to one skilled in the art, it is believed that the various embodiments have been described in sufficient detail to allow one skilled in the art to make and use the application. Accordingly, reference should be made to the drawings in pursuit of a fuller understanding of the application and the illustrative nature of the preferred embodiments. The specific embodiments were disclosed by way of example only.

Claims

1. A ripple-carry adder implemented in a field programmable gate array (FPGA), comprising: a first row of carry-in adder blocks for least significant bits of the adder; a plurality of carry-skip adder blocks having different block sizes for a plurality of bits of the adder, each block size related to a bit width input to the block; and a second row of carry-in adder blocks for most significant bits of the adder; wherein: each of the plurality of carry-skip adder blocks is coupled to receive as input a route-propagate-carry and a generate-carry signal from a full-adder logic block in a carry-skip adder structure; and the plurality of carry-skip adder blocks include a variable carry-skip block size to hide routing delays associated with generate-group-propagate and generate signals.

2. The ripple-carry adder implemented in a FPGA of claim 1, wherein: a critical path delay for a carry of the adder is lower compared to a critical path delay for a carry of a ripple-carry adder capable of being implemented in the FPGA having a same overall input bit width as the adder.

3. The ripple-carry adder implemented in a FPGA of claim 1, wherein: an area of the adder is lower in the FPGA compared to an area of a further carry-skip adder capable of being implemented in the FPGA consisting of carry-skip adder blocks having a fixed block size equal to a largest of the different block sizes of the plurality of carry-skip adder blocks of the adder.

4. The ripple-carry adder implemented in a FPGA of claim 1, wherein: the different block sizes increase from a first carry-skip adder block located at a first end of the plurality of carry-skip adder blocks to at least one carry-skip adder block intermediate the plurality of carry-skip adder blocks and decrease from the at least one carry-skip adder block intermediate the plurality of carry-skip adder blocks to a second carry-skip adder block located at a second end of the plurality of carry-skip adder blocks.

5. The ripple-carry adder implemented in a FPGA of claim 1, wherein: at least one of the plurality of carry-skip adder blocks includes wide-AND gate logic for fast block-propagate carry generation.

6. The adder implemented in an FPGA of claim 1, wherein, the adder has one or more features from a feature set including: a first feature including an adder structure that uses route-propagate and generate signals from adder logic to create a carry-skip adder structure; a second feature including custom block sizes in the adder structure to trade-off adder area performance; and a third feature including a ripple-carry structure that generates wide-AND gate logic for fast block-propagate generation functionality.

7. A computer-aided design (CAD) method, the method implemented by a CAD system, the method comprising: receiving instructions for implementing an adder in a field programmable gate array (FPGA); and generating the adder in a format for programming the FPGA, wherein the adder includes: a first row of carry-in adder blocks for least significant bits of the adder; a plurality of carry-skip adder blocks having different block sizes for a plurality of bits of the adder, each block size related to a bit width input to the block; and a second rippling carry adder block for a most significant bit of the adder; wherein: each of the plurality of carry-skip adder blocks is coupled to receive as input a route-propagated carry and a generate carry signal from a full adder logic block in a carry-skip adder structure; and the plurality of carry-skip adder blocks include variable carry-skip block sizes to hide routing delays associated with the generate group propagation and generate signals.

8. The CAD method of claim 7, wherein: a critical path delay for a carry of the adder is lower compared to a critical path delay for a carry of a rippling carry adder that can be implemented in an FPGA having a same overall input bit width as the adder.

9. The CAD method of claim 7, wherein: an area of the adder is lower in an FPGA compared to an area of a further carry-skip adder that can be implemented in an FPGA consisting of carry-skip adder blocks having a fixed block size equal to a largest of the different block sizes of the plurality of carry-skip adder blocks of the adder.

10. The CAD method of claim 7, wherein: the different block sizes increase from a first carry-skip adder block located at a first end of the plurality of carry-skip adder blocks to at least one carry-skip adder block intermediate the plurality of carry-skip adder blocks, and decrease from the at least one carry-skip adder block intermediate the plurality of carry-skip adder blocks to a second carry-skip adder block located at a second end of the plurality of carry-skip adder blocks.

11. The CAD method of claim 7, wherein: at least one of the plurality of carry-skip adder blocks includes wide AND gate logic for fast block-propagated carry generation.

12. The CAD method of claim 7, wherein, the adder has one or more features from a feature set including: a first feature including an adder structure that uses route-propagated and generate signals from adder logic to create a carry-skip adder structure; a second feature including customized block sizes in the adder structure to trade-off adder area performance; and a third feature including a rippling carry structure that generates wide AND gate logic for fast block-propagated carry generation.

13. A tangible, non-transitory computer-readable medium having instructions thereon that, when executed by a processor, cause the processor to perform a method comprising: receiving instructions for implementing an adder in a field programmable gate array (FPGA); and programming an FPGA to implement the adder, wherein the adder includes: a first rippling carry adder block for a least significant bit of the adder; a plurality of carry-skip adder blocks having different block sizes for a plurality of bits of the adder, each block size related to a bit width input to the block; and a second rippling carry adder block for a most significant bit of the adder; wherein: each of the plurality of carry-skip adder blocks is coupled to receive as input a route-propagated carry and a generate carry signal from a full adder logic block in a carry-skip adder structure; and the plurality of carry-skip adder blocks include variable carry-skip block sizes to hide routing delays associated with the generate group propagation and generate signals. Each of the plurality of carry-skip adder blocks is coupled to receive as inputs a route-propagated carry and a generate carry signal from a full adder logic block in the skip-adder structure; and The plurality of carry-skip adder blocks include a variable carry-skip block size to hide routing delays associated with the generate group propagate and generate signals.

14. The computer-readable medium of claim 13, wherein: a critical path delay for a carry of the adder is lower compared to a critical path delay for a carry of a rippling carry adder having a same overall input bit-width as the adder that is capable of being implemented in an FPGA; and an area of the adder is lower compared to an area of a further carry-skip adder consisting of carry-skip adder blocks having a fixed block size equal to a maximum of the different block sizes of the plurality of carry-skip adder blocks of the adder that is capable of being implemented in an FPGA.

15. The computer-readable medium of claim 13, wherein: the different block sizes increase from a first carry-skip adder block located at a first end of the plurality of carry-skip adder blocks to at least one carry-skip adder block intermediate the plurality of carry-skip adder blocks and decrease from the at least one carry-skip adder block intermediate the plurality of carry-skip adder blocks to a second carry-skip adder block located at a second end of the plurality of carry-skip adder blocks.

16. The computer-readable medium of claim 13, wherein: at least one of the plurality of carry-skip adder blocks includes wide-AND gate logic for fast block-propagated carry generation.

17. The computer readable medium of claim 13, wherein, the adder has one or more features from a feature set, the feature set including: a first feature including using route-propagated and generate signals from adder logic to create a carry-skip adder structure of the adder structure; a second feature including a customized block size in the adder structure to trade-off performance of adder area; and a third feature including a rippling carry structure that generates wide-AND gate logic for fast block-propagated carry generation.

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