Array substrate and display panel

Abstract

The application provides an array substrate and a display panel, and relates to the technical field of semiconductors. The array substrate comprises a substrate, a light-shielding metal layer, a semiconductor layer, a first metal layer and a second metal layer which are sequentially stacked; an insulating layer is arranged between any two adjacent layers among the light-shielding metal layer, the semiconductor layer, the first metal layer and the second metal layer; the light-shielding metal layer comprises a first signal line, and a normal projection of at least part of the first signal line on the substrate is located within a normal projection range of at least one of the first metal layer and the second metal layer on the substrate. The array substrate and the display panel provided by the application can reduce the area occupied by the signal line of the array substrate, so that the display panel with the array substrate can be improved in high resolution and high PPI.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the development of display technology, display devices such as mobile phones, tablets, and televisions have become increasingly integrated into people's daily lives, providing them with convenience. Mobile phones, in particular, have become an essential part of people's daily lives.

[0003] The display device has a display panel, which includes an array substrate and a light-emitting layer disposed on the array substrate. The array substrate includes a light-shielding metal layer, a first metal layer and a second metal layer. The first metal layer includes a plurality of laterally extending signal lines, and the second metal layer includes a plurality of laterally extending signal lines. The plurality of signal lines of the first metal layer and the plurality of signal lines of the second metal layer are arranged at intervals on the orthographic projection of the array substrate.

[0004] However, the signal lines on the array substrate occupy a relatively large area, which limits the improvement of display panels with this array substrate towards higher resolution and higher pixel density (Pixels Per Inch, or PPI). Summary of the Invention

[0005] In view of the above problems, embodiments of this application provide an array substrate and a display panel, which can reduce the area occupied by the signal lines of the array substrate, thereby enabling the display panel having the array substrate to be improved to higher resolution and higher PPI.

[0006] In a first aspect, embodiments of this application provide an array substrate, comprising a substrate, a light-shielding metal layer, a semiconductor layer, a first metal layer, and a second metal layer stacked sequentially; the light-shielding metal layer includes a first signal line, and at least a portion of the orthogonal projection of the first signal line onto the substrate is located within the orthogonal projection range of at least one of the first metal layer and the second metal layer onto the substrate.

[0007] The array substrate provided in this application includes a substrate, a light-shielding metal layer, a semiconductor layer, a first metal layer, and a second metal layer stacked sequentially. By providing an insulating layer between adjacent pairs of the light-shielding metal layer, the semiconductor layer, the first metal layer, and the second metal layer, the semiconductor layer and each metal layer of the array substrate can be kept insulated from each other, so that the array substrate can meet the requirements of complex circuit layout, thin film transistor formation, and capacitor formation.

[0008] Simultaneously, by setting a light-shielding metal layer including the first signal line, at least a portion of the first signal line's orthogonal projection on the substrate is located within the orthogonal projection range of at least one of the first and second metal layers on the substrate; that is, a portion of the first signal line is located below the first and / or second metal layers. On one hand, this reduces the area occupied by the signal lines of the array substrate, which not only helps to reduce the area of ​​a single pixel, allowing the display panel with this array substrate to be improved towards higher resolution and higher PPI, thus enhancing the performance of the display panel, but also helps to increase the light-transmitting area of ​​the array substrate, improving the usability of under-display functional devices. On the other hand, it reduces the interference of the first and second metal layers on the first signal line, thereby helping to ensure the signal transmission stability of the first signal line.

[0009] In one possible implementation of the array substrate described above, the first metal layer includes a second signal line, and at least a portion of the orthogonal projection of the first signal line onto the substrate lies within the orthogonal projection range of the second signal line onto the substrate.

[0010] This configuration has two advantages. First, it reduces the total pixel area occupied by the first and second signal lines, which not only helps reduce the area of ​​individual pixels, allowing the display panel with this array substrate to achieve higher resolution and higher PPI, thus improving the performance of the display panel, but also increases the light-transmitting area of ​​the array substrate, improving the performance of under-display functional devices. Second, it reduces mutual interference between the first and second signal lines, thereby helping to ensure the stability of signal transmission for both the first and second signal lines.

[0011] In one possible implementation of the array substrate described above, the width of the orthographic projection of the first signal line onto the substrate is not greater than the width of the orthographic projection of the second signal line onto the substrate.

[0012] This configuration allows the orthogonal projection of the first signal line onto the substrate to be completely within the orthogonal projection range of the second signal line onto the substrate. This helps to further reduce the total pixel area occupied by the first and second signal lines, and even eliminates the need for the first signal line to occupy additional pixel area outside the second signal line. Consequently, it helps to further reduce the area of ​​a single pixel, enabling the display panel with this array substrate to be improved towards higher resolution and higher PPI, thereby enhancing the performance of the display panel.

[0013] In one possible implementation of the array substrate described above, the first signal line is a first initialization signal line or a second initialization signal line; or, the first signal line includes at least two lines, wherein a portion of the first signal line is a first initialization signal line and a portion of the first signal line is a second initialization signal line.

[0014] This configuration ensures that the orthographic projection of at least one of the first initialization signal line and the second initialization signal line onto the substrate falls within the orthographic projection range of at least one of the first metal layer and the second metal layer onto the substrate. This reduces the total pixel area occupied by the first initialization signal line, the second initialization signal line, and other signal lines within the first metal layer and / or the second metal layer. Consequently, this not only improves the resolution and PPI of the display panel with the array substrate but also enhances the performance of under-display functional devices and ensures the signal transmission stability of the first signal line.

[0015] In one possible implementation of the array substrate described above, the second signal line is a scanning signal line or a light-emitting signal line; or, the second signal line includes at least two lines, wherein a portion of the second signal line is a scanning signal line and a portion of the second signal line is a light-emitting signal line.

[0016] This configuration ensures that the orthogonal projection of the first signal line onto the substrate falls within the orthogonal projection range of at least one of the scanning signal line and the light-emitting signal line onto the substrate. This reduces the total pixel area occupied by the first signal line, the scanning signal line, and the light-emitting signal line, which not only improves the resolution and PPI of the display panel with this array substrate but also enhances the performance of under-display functional devices. Furthermore, it helps to ensure the signal transmission stability of the first signal line, the scanning signal line, and the light-emitting signal line.

[0017] In one possible implementation of the array substrate described above, the second metal layer includes a third signal line, and at least a portion of the orthogonal projection of the first signal line onto the substrate lies within the orthogonal projection range of the third signal line onto the substrate.

[0018] This configuration has two advantages. First, it reduces the total pixel area occupied by the first and third signal lines, which not only helps reduce the area of ​​individual pixels, allowing the display panel with this array substrate to be improved towards higher resolution and higher PPI, thus enhancing the performance of the display panel, but also increases the light-transmitting area of ​​the array substrate, improving the performance of under-display functional devices. Second, it reduces mutual interference between the first and third signal lines, thereby helping to ensure the signal transmission stability of each signal line.

[0019] In one possible implementation of the array substrate described above, the width of the orthographic projection of the first signal line onto the substrate is not greater than the width of the orthographic projection of the third signal line onto the substrate.

[0020] This configuration allows the orthogonal projection of the first signal line onto the substrate to be completely within the orthogonal projection range of the third signal line onto the substrate. This helps to further reduce the total pixel area occupied by the first and third signal lines, and even eliminates the need for the first signal line to occupy additional pixel area beyond that of the third signal line. Consequently, it helps to further reduce the area of ​​a single pixel, enabling the display panel with this array substrate to be improved towards higher resolution and higher PPI, thereby enhancing the performance of the display panel.

[0021] In one possible implementation of the array substrate described above, the first signal line includes one of a first initialization signal line and a second initialization signal line, and the third signal line includes the other of the first initialization signal line and the second initialization signal line.

[0022] This configuration, on the one hand, places the first and second initialization signal lines on different metal layers, reducing mutual interference between them and thus ensuring the signal transmission stability of both the first and third signal lines. On the other hand, it reduces the total pixel area occupied by the first and second initialization signal lines, which not only improves the resolution and PPI of the display panel with this array substrate but also enhances the performance of under-display functional devices.

[0023] In one possible implementation of the array substrate described above, the light-shielding metal layer includes a light-shielding portion, and the orthogonal projection of the semiconductor layer on the substrate is located within the orthogonal projection range of the light-shielding portion on the substrate.

[0024] This configuration allows the light-shielding metal layer to shield the semiconductor layer, thereby preventing transmitted light from the bottom of the array substrate from adversely affecting the thin-film transistors in the array substrate during the manufacturing process.

[0025] Secondly, embodiments of this application provide a display panel, including the array substrate described above.

[0026] The display panel provided in this application includes an array substrate, which is an important component for ensuring the display panel achieves its display function. Specifically, the array substrate includes a substrate, a light-shielding metal layer, a semiconductor layer, a first metal layer, and a second metal layer stacked sequentially. By providing insulating layers between adjacent elements of the light-shielding metal layer, the semiconductor layer, the first metal layer, and the second metal layer, the semiconductor layer and each metal layer of the array substrate can be insulated from each other, thereby enabling the array substrate to accommodate complex circuit layouts, thin-film transistor formation, and capacitor formation.

[0027] Simultaneously, by setting a light-shielding metal layer including the first signal line, at least a portion of the first signal line's orthogonal projection on the substrate is located within the orthogonal projection range of at least one of the first and second metal layers on the substrate; that is, a portion of the first signal line is located below the first and / or second metal layers. On one hand, this reduces the area occupied by the signal lines of the array substrate, which not only helps to reduce the area of ​​a single pixel, allowing the display panel with this array substrate to be improved towards higher resolution and higher PPI, thus enhancing the performance of the display panel, but also helps to increase the light-transmitting area of ​​the array substrate, improving the usability of under-display functional devices. On the other hand, it reduces the interference of the first and second metal layers on the first signal line, thereby helping to ensure the signal transmission stability of the first signal line.

[0028] In one possible implementation of the above-described display panel, the display panel further includes a light-emitting layer located on the side of the array substrate facing away from the substrate of the array substrate.

[0029] With this configuration, the array substrate can control the light emission of the light-emitting layer, thereby enabling the display panel to perform its display function.

[0030] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the array substrate and display panel provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a top view of an array substrate in a related technology;

[0033] Figure 2 A top view of the array substrate provided in the embodiments of this application. Figure 1 ;

[0034] Figure 3 for Figure 2 A cross-sectional view of section AA on the middle array substrate;

[0035] Figure 4 for Figure 2Cross-sectional view of the BB section of the central array substrate;

[0036] Figure 5 A top view of the array substrate provided in the embodiments of this application. Figure 2 ;

[0037] Figure 6 for Figure 5 Cross-sectional view of the CC section of the middle array substrate Figure 1 ;

[0038] Figure 7 for Figure 5 Cross-sectional view of the CC section of the middle array substrate Figure 2 .

[0039] Explanation of reference numerals in the attached figures:

[0040] 100-substrate;

[0041] 210 - First Buffer Layer;

[0042] 220 - Second Buffer Layer;

[0043] 310 - Gate insulating layer;

[0044] 320 - Interlayer insulation layer;

[0045] 400 - Interlayer dielectric layer;

[0046] 500-Planarization layer;

[0047] 600 - Semiconductor layer; 610 - Active layer; 620 - Source region; 630 - Drain region;

[0048] 700 - Light-shielding metal layer; 710 - First signal line; 720 - Light-shielding part;

[0049] 810 - First metal layer; 811 - Second signal line; 812 - Gate;

[0050] 820 - Second metal layer; 821 - Third signal line; 822 - First electrode plate;

[0051] 830 - Third metal layer. Detailed Implementation

[0052] In related technologies, the array substrate includes a substrate, a light-shielding metal layer, a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer stacked sequentially, with an interlayer insulating layer disposed between adjacent pairs of the light-shielding metal layer, the semiconductor layer, the first metal layer, the second metal layer, and the third metal layer. Figure 1 This is a top view schematic diagram of an array substrate in related technologies, for reference. Figure 1As shown, the first metal layer includes light-emitting signal lines EM and scan signal lines Scan1 and Scan2; the second metal layer includes reference signal lines Vref-1 and Vref-2, one of which is an anode initialization signal line and the other is a capacitor gate signal line; the third metal layer includes data signal lines Data and power supply lines VDD; thin film transistors T and capacitors C are also formed in the array substrate.

[0053] In the top view of the array substrate, the light-emitting signal lines EM, Scan1, Scan2, and reference signal lines Vref-1, Vref-2 are arranged at intervals, occupying a relatively large pixel area. On the one hand, this not only makes it difficult to further reduce the area of ​​individual pixels, thus limiting the improvement of display panels with this array substrate towards higher resolution and higher pixel density, but also reduces the light-transmitting area of ​​the array substrate, thereby reducing the effectiveness of under-display functional devices. On the other hand, the reference signal lines Vref-1, Vref-2 of the second metal layer may be subject to signal interference from the signal lines of the first metal layer and other signal lines of the second metal layer, thus affecting the signal transmission stability of the reference signal lines Vref-1, Vref-2.

[0054] To address the aforementioned technical problems, embodiments of this application provide an array substrate and a display panel including the array substrate. The array substrate provided in this application includes a substrate, a light-shielding metal layer, a semiconductor layer, a first metal layer, and a second metal layer stacked sequentially. By providing insulating layers between adjacent elements in the light-shielding metal layer, semiconductor layer, first metal layer, and second metal layer, mutual insulation between the semiconductor layer and each metal layer of the array substrate can be ensured, enabling the array substrate to accommodate complex circuit layouts, thin-film transistor formation, and capacitor formation.

[0055] Simultaneously, by setting a light-shielding metal layer including the first signal line, at least a portion of the first signal line's orthogonal projection on the substrate is located within the orthogonal projection range of at least one of the first and second metal layers on the substrate; that is, a portion of the first signal line is located below the first and / or second metal layers. On one hand, this reduces the area occupied by the signal lines of the array substrate, which not only helps to reduce the area of ​​a single pixel, allowing the display panel with this array substrate to be improved towards higher resolution and higher PPI, thus enhancing the performance of the display panel, but also helps to increase the light-transmitting area of ​​the array substrate, improving the usability of under-display functional devices. On the other hand, it reduces the interference of the first and second metal layers on the first signal line, thereby helping to ensure the signal transmission stability of the first signal line.

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] Reference Figures 2 to 7 As shown, in a first aspect, embodiments of this application provide an array substrate.

[0058] The array substrate includes a substrate 100, a light-shielding metal layer 700, a semiconductor layer 600, a first metal layer 810, and a second metal layer 820, which are sequentially stacked. An insulating layer is disposed between adjacent elements of the light-shielding metal layer 700, the semiconductor layer 600, the first metal layer 810, and the second metal layer 820. Exemplarily, the insulating layer includes a first buffer layer 210, a second buffer layer 220, a gate insulating layer 310, and an interlayer insulating layer 320.

[0059] In one possible implementation, the stacked structure of the array substrate may include a substrate 100, a first buffer layer 210 disposed on one side of the substrate 100, a light-shielding metal layer 700 disposed on the side of the first buffer layer 210 facing away from the substrate, a second buffer layer 220 disposed on the side of the light-shielding metal layer 700 facing away from the substrate 100, a semiconductor layer 600 disposed on the side of the second buffer layer 220 facing away from the substrate, and a gate insulating layer 310 disposed on the side of the semiconductor layer 600 facing away from the substrate 100. A first metal layer 810 is disposed on one side away from the substrate 100. An interlayer insulating layer 320 is disposed on the side of the first metal layer 810 away from the substrate 100. A second metal layer 820 is disposed on the side of the interlayer insulating layer 320 away from the substrate 100. An interlayer dielectric layer 400 may be disposed on the side of the second metal layer 820 away from the substrate 100. A third metal layer 830 may be disposed on the side of the interlayer dielectric layer 400 away from the substrate 100. A planarization layer 500 may be disposed on the side of the third metal layer 830 away from the substrate 100.

[0060] The first metal layer 810 may include multiple scan signal lines (Scan), and the third metal layer 830 may include multiple data signal lines (Data). The scan signal lines (Scan) and data signal lines (Data) are arranged in a crisscross pattern; for example, the scan signal lines (Scan) may extend laterally, and the data signal lines (Data) may extend vertically. Based on the aforementioned insulating layer, the scan signal lines (Scan) and data signal lines (Data) are mutually insulated. The multiple scan signal lines (Scan) and multiple data signal lines (Data) define the area containing multiple pixel units of the array substrate according to the above arrangement.

[0061] The first metal layer 810 may further include a light-emitting signal line EM, the extension direction of which is the same as the extension direction of the scan signal line Scan. The third metal layer 830 may further include a power line VDD, the extension direction of which is the same as the extension direction of the data signal line Data.

[0062] Each pixel unit of the array substrate includes a capacitor C and at least two thin-film transistors T. The at least two thin-film transistors include at least one charging thin-film transistor and one driving thin-film transistor. In a pixel unit, there can be multiple charging thin-film transistors, thus forming different pixel unit circuit structures. For example, a 2T1C pixel circuit includes one charging thin-film transistor, one driving thin-film transistor, and one capacitor, while in commonly used 5T1C and 7T1C pixel circuits, the number of charging thin-film transistors is greater than one.

[0063] The thin-film transistor includes a gate, a source, a drain, and an active layer. The gate is electrically connected to a scan signal line, the source is electrically connected to a data signal line, and the drain is electrically connected to the anode of the light-emitting layer. For example, the first metal layer 810 may include a gate 812, the semiconductor layer 600 may include an active layer 610, a source region 620, and a drain region 630, and the third metal layer 830 may include a source and a drain (not shown) respectively connected to the source region 620 and the drain region 630. The capacitor includes a first plate and a second plate. For example, the second metal layer 820 may include a first plate 822, and the gate 812 may be reused as the second plate of the capacitor.

[0064] The array substrate also includes an anode initialization signal line and a capacitor gate signal line. The anode initialization signal line is electrically connected to the anode of the light-emitting layer, and the capacitor gate signal line can be electrically connected to the second plate of the capacitor to provide a signal to the second plate. The positions of the anode initialization signal line and the capacitor gate signal line in the array substrate will be described later.

[0065] The light-shielding metal layer 700 includes a first signal line 710, at least a portion of which has its orthographic projection on the substrate 100 located within the orthographic projection range of at least one of the first metal layer 810 and the second metal layer 820 on the substrate 100. For example, the orthographic projection of the first signal line 710 on the substrate 100 may be located within the orthographic projection range of the first metal layer 810 on the substrate 100; or, the orthographic projection of the first signal line 710 on the substrate 100 may be located within the orthographic projection range of the second metal layer 820 on the substrate 100; or, a portion of the orthographic projection of the first signal line 710 on the substrate 100 may be located within the orthographic projection range of the first metal layer 810 on the substrate 100, and a portion may be located within the orthographic projection range of the second metal layer 820 on the substrate 100.

[0066] On the one hand, it can reduce the pixel area occupied by the signal lines of the array substrate, which not only helps to reduce the area of ​​a single pixel, allowing the display panel with the array substrate to be improved to higher resolution and higher PPI, thus improving the performance of the display panel; but also helps to increase the light-transmitting area of ​​the array substrate, improving the performance of under-display functional devices. For example, under-display functional devices include, but are not limited to, in-display fingerprint (FOD) devices, in-display image sensors, and in-display distance sensors. This embodiment uses an in-display fingerprint device as an example. The in-display fingerprint device is disposed on the side of the display panel closest to the array substrate. When a finger touches the side of the display panel furthest from the array substrate, light passes through the display panel, including the array substrate, and is received and recognized by the in-display fingerprint device. Therefore, the larger the light-transmitting area of ​​the array substrate, the more light the in-display fingerprint device receives, the more sensitive the fingerprint recognition, and the higher the recognition accuracy.

[0067] On the other hand, the first signal line 710 does not need to be located within the first metal layer 810 or the second metal layer 820, thereby reducing interference from other signal lines within the first metal layer 810 and the second metal layer 820 to the first signal line 710, which in turn helps to ensure the signal transmission stability of the first signal line 710.

[0068] In some embodiments, the first metal layer 810 includes a second signal line 811, and at least a portion of the orthographic projection of the first signal line 710 onto the substrate 100 lies within the orthographic projection range of the second signal line 811 onto the substrate 100. For example, a portion of the orthographic projection of the first signal line 710 onto the substrate 100 may lie within the orthographic projection range of the second signal line 811 onto the substrate 100; or, the entire orthographic projection of the first signal line 710 onto the substrate 100 may lie within the orthographic projection range of the second signal line 811 onto the substrate 100.

[0069] On the one hand, this reduces the total pixel area occupied by the first signal line 710 and the second signal line 811. This not only helps reduce the area of ​​individual pixels, allowing the display panel with this array substrate to be improved towards higher resolution and higher PPI, thus enhancing the performance of the display panel, but also helps increase the light-transmitting area of ​​the array substrate, improving the performance of under-display functional devices. On the other hand, since the first signal line 710 is not co-layered with the second signal line 811, mutual interference between the first signal line 710 and the second signal line 811 can be reduced, thereby helping to ensure the signal transmission stability of both the first signal line 710 and the second signal line 811.

[0070] Optionally, the width of the orthographic projection of the first signal line 710 on the substrate 100 is not greater than the width of the orthographic projection of the second signal line 811 on the substrate 100. That is, the width of the orthographic projection of the first signal line 710 on the substrate 100 can be less than the width of the orthographic projection of the second signal line 811 on the substrate 100, or the width of the orthographic projection of the first signal line 710 on the substrate 100 can be equal to the width of the orthographic projection of the second signal line 811 on the substrate 100. This facilitates ensuring that the orthographic projection of the first signal line 710 on the substrate 100 is completely within the range of the orthographic projection of the second signal line 811 on the substrate 100. This further helps to reduce the total pixel area occupied by the first signal line 710 and the second signal line 811, and may even eliminate the need for the first signal line 710 to occupy additional pixel area outside of the second signal line 811. This further reduces the area of ​​a single pixel, allowing the display panel with this array substrate to be improved towards higher resolution and higher PPI, thereby enhancing the performance of the display panel.

[0071] Optionally, the first signal line 710 can be a first initialization signal line; or, the first signal line 710 can be a second initialization signal line; or, the first signal line 710 can include at least two lines, wherein a portion of the first signal line 710 is a first initialization signal line and a portion of the first signal line 710 is a second initialization signal line. For example, the first signal line 710 can include two lines, one of which is a first initialization signal line and the other is a second initialization signal line.

[0072] For example, the first initialization signal line can be an anode initialization signal line, and the second initialization signal line can be a capacitor gate signal line. In specific implementation, the first signal line 710 can be an anode initialization signal line, and the capacitor gate signal line can be disposed within the first metal layer 810 or the second metal layer 820; or, the first signal line 710 can be a capacitor gate signal line, and the anode initialization signal line can be disposed within the first metal layer 810 or the second metal layer 820; or, the first signal line 710 can include at least two lines, with part of the first signal line 710 being an anode initialization signal line and part of the first signal line 710 being a capacitor gate signal line.

[0073] This ensures that the orthogonal projection of at least one of the anode initialization signal line and the capacitor gate signal line onto the substrate 100 lies within the orthogonal projection range of at least one of the first metal layer 810 and the second metal layer 820 onto the substrate 100. This reduces the total pixel area occupied by the anode initialization signal line, the capacitor gate signal line, and other signal lines within the first metal layer 810 and / or the second metal layer 820. Consequently, this not only improves the resolution and PPI of the display panel with the array substrate but also enhances the performance of under-display functional devices. Furthermore, it eliminates the need for at least one of the anode initialization signal line and the capacitor gate signal line to be located within the first metal layer 810 or the second metal layer 820, thus ensuring signal transmission stability.

[0074] Optionally, the second signal line 811 can be a scan signal line (Scan); or, the second signal line 811 can be a light emission signal line (EM); or, the second signal line 811 can include at least two lines, wherein part of the second signal line 811 is a scan signal line (Scan) and part of the second signal line 811 is a light emission signal line (EM). For example, the second signal line 811 can include two lines, one of which is a scan signal line (Scan) and the other is a light emission signal line (EM).

[0075] For example, the orthogonal projection of the first signal line 710 on the substrate 100 may be located within the orthogonal projection range of the scan signal line Scan on the substrate 100, or within the orthogonal projection range of the light-emitting signal line EM on the substrate 100, or partly within the orthogonal projection range of the scan signal line Scan on the substrate 100 and partly within the orthogonal projection range of the light-emitting signal line EM on the substrate 100.

[0076] This reduces the total pixel area occupied by the first signal line 710, the scan signal line Scan, and the light-emitting signal line EM, which not only helps improve the resolution and PPI of the display panel with the array substrate, but also improves the performance of the under-display functional devices. At the same time, it eliminates the need for the first signal line 710 to be located in the same metal layer as the scan signal line Scan and the light-emitting signal line EM, thus ensuring the signal transmission stability of the first signal line 710, the scan signal line Scan, and the light-emitting signal line EM.

[0077] In other embodiments, the second metal layer 820 includes a third signal line 821, wherein at least a portion of the orthographic projection of the first signal line 710 onto the substrate 100 lies within the orthographic projection range of the third signal line 821 onto the substrate 100. For example, a portion of the orthographic projection of the first signal line 710 onto the substrate 100 may lie within the orthographic projection range of the third signal line 821 onto the substrate 100; or, the entire orthographic projection of the first signal line 710 onto the substrate 100 may lie within the orthographic projection range of the third signal line 821 onto the substrate 100.

[0078] On the one hand, this reduces the total pixel area occupied by the first signal line 710 and the third signal line 821. This not only helps reduce the area of ​​individual pixels, allowing the display panel with this array substrate to be improved towards higher resolution and higher PPI, thus enhancing the performance of the display panel, but also helps increase the light-transmitting area of ​​the array substrate, improving the performance of under-display functional devices. On the other hand, the first signal line 710 is not co-layered with the third signal line 821, reducing mutual interference between them and thus ensuring the signal transmission stability of both the first signal line 710 and the third signal line 821.

[0079] Optionally, the width of the orthographic projection of the first signal line 710 onto the substrate 100 is not greater than the width of the orthographic projection of the third signal line 821 onto the substrate 100. That is, the width of the orthographic projection of the first signal line 710 onto the substrate 100 can be less than the width of the orthographic projection of the third signal line 821 onto the substrate 100, or the width of the orthographic projection of the first signal line 710 onto the substrate can be equal to the width of the orthographic projection of the third signal line 821 onto the substrate 100. This is beneficial for further reducing the total pixel area occupied by the first signal line 710 and the third signal line 821, and even eliminating the need for the first signal line 710 to occupy additional pixel area beyond that of the third signal line 821. This further helps to reduce the area of ​​a single pixel, enabling the display panel with this array substrate to be improved towards higher resolution and higher PPI, thereby improving the performance of the display panel.

[0080] For example, the first signal line 710 includes one of a first initialization signal line and a second initialization signal line, and the third signal line 821 includes the other of the first initialization signal line and the second initialization signal line. In a specific implementation, the first signal line 710 includes an anode initialization signal line, and the third signal line 821 includes a capacitor gate signal line; or, the first signal line 710 includes a capacitor gate signal line, and the third signal line 821 includes an anode initialization signal line.

[0081] On the one hand, placing the anode initialization signal line and the capacitor gate signal line on different metal layers reduces mutual interference between them, thus helping to ensure the signal transmission stability of the first signal line 710 and the third signal line 821. On the other hand, it reduces the total pixel area occupied by the anode initialization signal line and the capacitor gate signal line, which not only improves the resolution and PPI of the display panel with this array substrate, but also enhances the performance of under-display functional devices.

[0082] Optionally, the light-shielding metal layer 700 includes a light-shielding portion 720, and the orthographic projection of the semiconductor layer 600 on the substrate 100 is located within the orthographic projection range of the light-shielding portion 720 on the substrate 100. This allows the light-shielding portion 720 of the light-shielding metal layer 700 to effectively shield the semiconductor layer 600, thereby preventing transmitted light from the bottom of the array substrate from adversely affecting the thin-film transistors in the array substrate during the fabrication process.

[0083] For example, the first signal line 710 and the light-shielding part 720 may be located at different positions of the light-shielding metal layer 700; or, the first signal line 710 and the light-shielding part 720 may be located at the same position of the light-shielding metal layer 700, that is, the light-shielding part 720 may serve as the first signal line 710.

[0084] Secondly, embodiments of this application provide a display panel, including an array substrate. Exemplarily, the display panel may be a display panel for a mobile phone, a tablet computer, a smartwatch, or other display devices known to those skilled in the art.

[0085] The display panel provided in this application includes an array substrate, which is an important component ensuring the display panel achieves its display function. The display panel also includes a light-emitting layer. Exemplarily, the light-emitting layer can be a liquid crystal light-emitting layer, an organic light-emitting diode (OLED) layer, or other types of light-emitting layers known to those skilled in the art. The light-emitting layer is located on the side of the array substrate facing away from the substrate. The array substrate can control the light-emitting layer to emit light, thereby enabling the display panel to achieve its display function.

[0086] Since the display panel provided in this application embodiment includes the above-mentioned array substrate, the display panel in this application embodiment also has the beneficial effects of the above-mentioned array substrate. For details, please refer to the above description of the array substrate, which will not be repeated here.

[0087] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0088] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, It includes a substrate, a light-shielding metal layer, a semiconductor layer, a first metal layer, and a second metal layer, which are stacked sequentially. The light-shielding metal layer includes a first signal line and a light-shielding portion. The first metal layer includes a second signal line, and the second metal layer includes a third signal line. The first signal line includes one of a first initialization signal line and a second initialization signal line, and the third signal line includes the other of the first initialization signal line and the second initialization signal line. The second signal line is a scanning signal line or a light-emitting signal line, or the second signal line includes at least two lines, wherein a portion of the second signal line is a scanning signal line and a portion of the second signal line is a light-emitting signal line. At least a portion of the orthographic projection of the first signal line onto the substrate lies within the orthographic projection range of at least one of the second and third signal lines onto the substrate; The orthogonal projection of the semiconductor layer onto the substrate lies within the orthogonal projection range of the light-shielding portion onto the substrate.

2. The array substrate according to claim 1, characterized in that, The width of the orthographic projection of the first signal line onto the substrate is not greater than the width of the orthographic projection of the second signal line onto the substrate.

3. The array substrate according to claim 1, characterized in that, The width of the orthographic projection of the first signal line onto the substrate is not greater than the width of the orthographic projection of the third signal line onto the substrate.

4. A display panel, characterized in that, The array substrate includes any one of claims 1-3.

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