A primary-secondary delay-locked loop with dual delay lines

Abstract

The present invention discloses a primary and secondary delay locked loop with double delay lines, comprising: a power-on reset module POR, a primary delay locked loop DLL1, a secondary delay locked loop DLL2, and a lock indication module LI; the power-on reset module is connected to the reset control module of the primary delay locked loop, the output voltage signal V1 of the primary delay locked loop is connected to the short chain of the secondary double-chain voltage-controlled delay line, an external input clock signal CLK is connected to the primary delay locked loop and the secondary delay locked loop, the total reset signal generated by the primary delay locked loop is connected to the filter module of the secondary delay locked loop, and the output signals of the phase frequency detector module PFD1 and the phase frequency detector module PFD2 are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead, etc.

Description

Technical Field

[0001] This invention pertains to digital clock generation technology in the field of integrated circuits, and more specifically, relates to a primary and secondary delay phase-locked loop with dual delay lines. Background Technology

[0002] With the development of semiconductor technology and continuous improvement in its processes, intelligent electronic devices have long become an integral part of people's daily lives. These electronic devices all rely on power supplies, which are widely used in all aspects of life. As a crucial component of integrated circuit (IC) systems, the clock generation circuit's performance directly impacts the overall system performance. As chip operating frequencies increase, the requirements for clock signals also rise, making the digitalization of switching power supplies a growing trend. In digitally controlled switching power supplies, Digital Pulse Width Modulation (DPWM) is a vital component.

[0003] The hybrid DPWM circuit combines a counting-compare structure and a delay line structure. The front stage uses a counting-compare structure for coarse adjustment, generating set and reset signals to control the RS flip-flop. The rear stage uses a delay line structure for fine adjustment, performing a corresponding phase shift on the reset signal.

[0004] The two-stage delay line structure reduces the number of delay units. A delay-locked loop (DLL) provides the control voltage for the delay units, making it less susceptible to external influences. The two DLL modules control the coarse and fine delay lines respectively; however, the DLL controlling the fine delay line has a larger number of voltage-controlled delay units, resulting in a larger layout area. Summary of the Invention

[0005] To overcome the problems in the prior art, the purpose of this application is to provide a primary and secondary delay phase-locked loop with dual delay lines. The delay phase-locked loop avoids the use of long delay lines when controlling the thickness of the delay lines of DPWM, and ensures that the secondary phase-locked loop is locked after the primary delay phase-locked loop is locked.

[0006] The technical solution adopted by this invention to solve its technical problem is:

[0007] A primary and secondary delay phase-locked loop with dual delay lines includes:

[0008] The system includes a power-on reset module (POR), a primary delay phase-locked loop (DLL1), a secondary delay phase-locked loop (DLL2), and a lockout indicator module (LI); among which...

[0009] The power-on reset module and the external reset signal are used to generate system operation control signals;

[0010] The main stage delay phase-locked loop includes a frequency and phase detector module PFD1, a charge pump module CP1, a reset control module SC, a filter module Filter1, and a main stage voltage-controlled delay line module VCDL1.

[0011] The secondary delay phase-locked loop includes a frequency and phase detector module PFD2, a charge pump module CP2, a filter module Filter2, and a dual-chain voltage-controlled delay line module VCDL2.

[0012] The locking indicator module is used to determine whether the two phase-locked loops have completed locking;

[0013] The power-on reset module is connected to the reset control module of the primary delay phase-locked loop (PLL). The output voltage signal V1 of the primary PLL is connected to the short chain of the secondary dual-chain voltage-controlled delay line. The external input clock signal CLK is connected to the primary PLL and the secondary PLL. The total reset signal generated by the primary PLL is connected to the secondary PLL filter module. The output signals of the frequency and phase detector modules PFD1 and PFD2 are respectively connected to the lockout indicator module.

[0014] The voltage-controlled delay line in the secondary delay phase-locked loop is a double chain, and the delay unit in the first delay chain is the same as the delay unit in the primary delay line.

[0015] The reset signal of the power-on reset circuit is a ramp signal during the power-on process of the circuit, which is used to prevent the phase-locked loop from locking incorrectly during power-on.

[0016] The locking indication module performs an XOR operation on the two output signals of the frequency and phase detector in the primary delay phase-locked loop, and then performs an AND operation on the resulting signal after a short delay. The secondary delay phase-locked loop performs the same operation, and finally performs an OR operation on the two resulting signals.

[0017] The delay time of the second delay chain of the secondary dual-chain voltage-controlled delay line is equal to the accuracy of the digital pulse width modulator, and the total delay time of the delay chain is the delay time after the primary delay unit is locked.

[0018] In the aforementioned secondary delay phase-locked loop dual-chain structure, after the primary delay phase-locked loop is locked, the total time of the first chain of the secondary delay phase-locked loop is determined, the input reference signal of the frequency and phase detector of the secondary delay line is determined, and its output signal locks the secondary delay phase-locked loop by controlling the charging and discharging of the capacitor through the charge pump, thus obtaining the locking voltage V2.

[0019] The delay time and number of delay units of the primary delay line are determined based on the period of the input clock signal. The number of delay units and delay time of the secondary delay line are determined based on the delay accuracy and the number of delay units of the primary delay line.

[0020] The frequency and phase detector modules PFD1 and PFD2 are equipped with parasitic capacitors to precharge the circuit before the rising edge of the input signal arrives, thereby increasing the circuit's operating speed. The circuit uses a smaller channel length and a larger aspect ratio to reduce the conduction time of the frequency and phase detectors.

[0021] The charge pump modules CP1 and CP2 have their charge / discharge switches located at the source end to reduce charge sharing.

[0022] Both the main-stage voltage-controlled delay line module VCDL1 and the dual-chain voltage-controlled delay line module VCDL2 are equipped with delay units. They adopt a pseudo-differential structure to control the voltage control adjustment characteristics of the delay time by controlling the RC time constant of the output node. The delay time increases as the control voltage increases.

[0023] The beneficial effects of this invention are:

[0024] This invention employs a primary and secondary delay phase-locked loop (PLL) with dual delay lines. For high-precision digital pulse width modulation (DPWM) systems, a hybrid DPWM structure is used. Without considering the delay units that maintain consistency in each delay line, if the fine-tuning part uses a single delay line structure, there will be 2*(T / d2) delay units; using a primary and secondary DLL structure, there will be T / d2+2(T / d1)+d1 / d2 delay units; the structure proposed in this invention requires 2(d1 / d2+T / d1)+4 delay units, where T is the clock period, d1 is the delay time of the coarse delay unit, and d2 is the delay time of the fine delay unit, i.e., the precision. When higher precision is required, T / d2 is large. The structure proposed in this invention effectively avoids this issue, achieving the effect of reducing the number of delay units, thereby reducing the area of ​​the delay units in the layout. Attached Figure Description

[0025] Figure 1 This is a block diagram of a digital pulse width modulator provided in an embodiment of the present invention.

[0026] Figure 2 This is a block diagram of the main stage delay phase-locked loop and reset signal structure provided in an example of the present invention.

[0027] Figure 3 This is a block diagram of the secondary delay phase-locked loop structure provided in an example of the present invention.

[0028] Figure 4 This is a block diagram of the secondary delay phase-locked loop double-chain delay line structure provided in an example of the present invention.

[0029] Figure 5 This is a block diagram of the overall structure of the primary and secondary delay phase-locked loop with dual delay lines provided in an example of the present invention.

[0030] Figure 6 This is a waveform diagram provided in an example of the present invention.

[0031] Figure 7 This is a structural block diagram of the system lock indication module provided in the embodiment of the present invention.

[0032] Figure 1 In the middle, there is a counter 101, a comparator 102, a coarse adjustment voltage-controlled delay line 103, a fine adjustment voltage-controlled delay line 104, a frequency divider 105, an RS latch 106, a data selector one (MUX1) 107, a data selector two (MUX2) 108, and a primary and secondary delay phase-locked loop with dual delay lines 109.

[0033] Figure 2 In the middle, there is a frequency and phase detector (PFD1) 201, a charge pump (CP1) 202, a filter (Filter1) 203, a main stage voltage-controlled delay line (VCDL1) 204, a power-on reset circuit (POR) 205, and a reset circuit (SC) 206.

[0034] Figure 3 In the middle, there is a frequency and phase detector (PFD2) 301, a charge pump (CP2) 302, a filter (Filter2) 303, and a dual-chain voltage-controlled delay line (VCDL2) 304;

[0035] Figure 4 In the middle, there is a coarse delay unit M1X and a fine delay unit M2X. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments in this application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0037] The hybrid digital pulse width modulation (PWM) system consists of a coarse adjustment section comprised of a counter-comparator, with the clock period as the adjustment precision. After the coarse adjustment, a voltage-controlled delay line (VCD) forms the fine adjustment section, with the minimum delay time as the adjustment precision. The VCD has multiple delay units, generating multiple sequentially delayed clock signals with fixed time intervals based on the clock signal CLK. More specifically, the clock signal CLK can be decomposed into a set of delayed clock signals with different phases or sequentially delayed time intervals of t, referred to as delayed clock signals. The output tap voltage of the VCD is connected to a data selector to adjust the output delay time, thereby performing digital pulse width modulation.

[0038] A delay-locked loop (PLL) consists of a phase frequency detector (PFD), a charge pump (CP), and a voltage-controlled delay line (VCDL). The PFD receives a reference clock from the system clock source and a clock fed back from the VCDL, and compares these two clocks. Based on the phase difference between the two clocks, if the reference clock signal leads the feedback clock signal, a UP signal is generated; if the reference clock signal lags the feedback clock signal, a DN signal is generated. The corresponding UP and DN signals are fed into the charge pump to control the on / off state of the charge pump current source and current sink, thereby charging and discharging the capacitor and generating the corresponding control voltage V. ctrl V ctrl The delay time of the delay unit in the VCDL is controlled and fed back to the frequency and phase detector. The phase of the feedback clock is adjusted and then enters the PFD again. This process is repeated until a stable voltage output is finally generated.

[0039] like Figure 1 The diagram shows the schematic of a hybrid digital pulse width modulation (DPWM) structure. The hybrid DPWM structure includes a counter circuit 101, a comparator circuit 102, a coarse-adjustment voltage-controlled delay line 103, a fine-adjustment voltage-controlled delay line 104, a frequency divider 105, an RS latch 106, a data selector 107 and a data selector 2 108, a primary and secondary delay phase-locked loop (DLL circuit) 109, and a counter 101 input signal CLK.

[0040] CLK is a high-frequency clock. The clock signal is passed through counter 101 and comparator 102 to obtain a low-frequency clock. The low-frequency clock enters the coarse-adjustment voltage-controlled delay line 103. The tap of the delay unit of the coarse-adjustment voltage-controlled delay line 103 is connected to data selector 107. The input signal of data selector 1 is the high-order bit signal of the delay control code. The output signal enters the fine-adjustment delay line 104. The tap of the delay unit of the fine-adjustment delay line 104 is connected to data selector 208. The input signal of data selector 2 is the low-order bit signal of the delay control code. The output delayed signal and the high-frequency clock signal divided by the frequency divider enter the latch together to finally obtain the DPWM signal.

[0041] In this embodiment, as Figure 1As shown, the primary voltage-controlled delay line 103 can be divided into 8 delay units M11-M18, and the secondary voltage-controlled delay line 104 can be divided into 8 delay units M21-M28. Each of the 8 output delayed clock signals M1 is delayed by 1 / 8 of a clock cycle, and the 8 output delayed clock signals clk... <0> , clk <1> … clk <7> , represented as clk<7:0>; M2 can be divided into 1 / 64 clock cycles, outputting 8 delayed clock signals clk <8> , clk <9> … clk <15> This is represented as clk<15:8>. For example, if the input clock frequency is 80MHz and the period is 12.5ns, then after a coarse delay unit, the delay is 1.56ns, and after a fine delay unit, the delay is 195ps. And so on, the clock signal CLK, after passing through the delay circuit, yields... Figure 1 The example shown is a set of delayed clock signals clk<15:0>.

[0042] A primary and secondary delay phase-locked loop 109 with dual delay lines includes: a power-on reset module POR, a primary delay phase-locked loop module DLL1, a secondary delay phase-locked loop module DLL2, and a lockout indicator module LI; wherein the power-on reset module, the primary delay phase-locked loop module, and the secondary delay phase-locked loop module are connected in sequence; control voltages V1 and V2 of two delay chain delay units are obtained, and the control voltages are connected to the delay chain of the DPWM system to finally obtain an analog duty cycle signal.

[0043] When the main stage delay phase-locked loop is working, the input clock signal passes through a frequency and phase detector, a charge pump, and a voltage-controlled delay chain to obtain signal F1. div F1 div The input is fed to another port of the frequency and phase detector. The frequency and phase detector determines the phase difference between the two signals and outputs UP and DN signals. The UP and DN signals are input to the charge pump to control the charging and discharging of the capacitor, obtaining the voltage V1 on the capacitor. V1 is input to the voltage-controlled delay unit, thereby changing the output signal F1. div After this feedback process, DLL1 reaches a locked state, locking voltage V1;

[0044] like Figure 2As shown, the main stage delay phase-locked loop (DLL1) circuit includes a frequency and phase detector (PFD1) 201, a charge pump (CP1) 202, a filter (Filter1) 203, a main stage voltage-controlled delay line (VCDL1) 204, and a reset circuit (SC) 205. The voltage-controlled delay line is composed of a voltage-controlled delay unit M1. The clock signal CLK provides a reference clock with a period of T for the entire digital pulse width modulation circuit. The input of the frequency and phase detector is connected to the clock signal CLK. The reference clock, after passing through the frequency and phase detector 201, generates two signals, UP1 and DN1, which are connected to the charge pump 202 to control its switching. The charge pump 202 controls the charging and discharging of the capacitor in the filter circuit 203 to obtain V1. V1 is connected to the voltage-controlled delay line 204. The clock signal of the voltage-controlled delay line is the system clock CLK, and the control voltage is the filter output voltage V1. The signal passes through the voltage-controlled delay line 204 and outputs signal F1. div F1 div Feedback is sent to another input port of the frequency and phase detector, and this process repeats until the feedback loop stabilizes. CLK and F1... div The difference is one cycle, meaning that F1 is obtained after a series of delays following the rise of CLK. div At this time, F1 div It overlaps with CLK, but F1 div It lags behind CLK by one cycle.

[0045] The secondary delay-locked loop (PLL) consists of a frequency and phase detector module, a charge pump module, and a dual-chain voltage-controlled delay line (VCD) module. The dual-chain VCD consists of delay units M1X from the primary VCD and delay units M2X from the secondary VCD. The primary DLL (VCD1) has eight delay units M1X, while the secondary DLL has both M1X and M2X delay units. The total delay time of the secondary delay units M2X is equal to the delay time of a single M1X module from the primary DLL1. The locking state of the secondary PLL DLL2 is determined by the locking voltage V1 of the primary DLL1 and its own feedback, ensuring that the DLL2 circuit locks after the DLL1 circuit locks.

[0046] like Figure 3 The diagram shows the secondary delay phase-locked loop (DLL2) structure. The input signal of the frequency and phase detector 301 is the output signal F of the dual-chain voltage-controlled delay line 304. ref and F div The output signal of the frequency and phase detector 301 is connected to the charge pump 302. The charge pump 302 controls the charging and discharging of the capacitor in the filter 303 to obtain voltage V2. V2 is connected to the dual-chain voltage-controlled delay line 304.

[0047] The dual-chain voltage-controlled delay line uses a coarse delay chain as its first delay chain, with its delay unit being the delay unit M1X of the master-level delay phase-locked loop (PLL). The second delay chain is a fine delay chain, with its delay unit being M2X. When the PLL is locked, the total delay time of the two chains is the same. The signal returned by the input clock after passing through the first delay chain is F. ref As the first input signal to the frequency and phase detector, the signal returned by the input clock after passing through the second delay chain is F. div This serves as the second input signal for the frequency and phase detector.

[0048] like Figure 4 The diagram shows the structure of the dual-chain delay-locked loop 304 of the secondary delay-locked loop DLL2. The CLK input passes through a buffer delay unit M11 and is then connected to delay lines 401 and 402 respectively. The output signal of CLK after delay line 401 is F. ref The output signal after delay line 402 is F div The input signal V1 is the output voltage of the master stage voltage-controlled delay line.

[0049] Figure 4 The total delay time of the 8 M2Xs is equal to the delay time of 1 M1X. The delay times of M21-M28 are equal to the delay time of M12, that is...

[0050] M11+M21+⋯+M28+M15=M11+M12+M13

[0051] M21+⋯+M29=M12.

[0052] F ref When the signal is unlocked in the primary delay-locked loop (DLL), its phase is unstable, so the secondary DLL is also unlocked. When the primary DLL is unlocked, the delay time of each delay unit in the low-precision delay chain is not fixed, thus preventing the high-precision delay chain from locking as well. This ensures that DLL2 locks after DLL1. After the primary DLL locks, F... ref With phase stability, the secondary delay phase-locked loop's frequency and phase detector, charge pump, and second delay chain begin phase-locking operation, and finally F... ref With F div When the same phase is achieved, the delay phase-locked loop is locked at this stage, with a locking voltage of V2.

[0053] In this example, V1 is the control voltage of the voltage-controlled delay line 401, and CLK outputs signal F through the voltage-controlled delay line 401. ref CLK outputs signal F after passing through voltage-controlled delay line 402. div Once the master-level delay-locked loop stabilizes, F ref Only when the phase of the secondary delay phase-locked loop no longer changes can the system feedback loop reach stability, at which point F... refWith F div The periodic phases all coincide. To ensure consistency with the DPWM circuit, the same load as the MUX input stage is connected after each delay unit of the 109.

[0054] like Figure 6 As shown in this example, T = 12.5 ns, assuming d1 = 1.56 ns and d2 = 195 ps, that is, after the delay phase-locked loop is locked, the delay time of each M1 is 1.56 ns and the delay time of each M2 is 195 ps. Then n = T / d1 = 8 and m = d1 / d2 = 8. If a single delay line structure is used, 2mn = 128 delay units are needed. If a primary and secondary delay phase-locked loop structure is used, mn + 2n + m = 88 delay units are needed. The structure of this invention requires 2(m + n) + 4 = 36 delay units, which can effectively reduce the number of delay units.

[0055] The POR (Power On Reset) circuit 206 uses a ramp signal for power-on voltage to prevent delayed phase-locked loop (PLL) locking before the system operating voltage is reached. The power-on reset signal and the external reset signal together constitute the input signal of the reset module. The POR circuit ensures that no mis-locking occurs during power-on. In addition, an external reset signal and reset circuit 205 are added to the circuit, which together with the external Reset_in signal form the reset signal Reset.

[0056] like Figure 2 In Figure 3, 201 and 301 are pre-charge frequency and phase detectors. Before the rising edge of the input signal arrives, the circuit will pre-charge due to the presence of parasitic capacitance, which increases the operating speed of the circuit. The circuit uses a small channel length and a large aspect ratio to reduce the PFD conduction time.

[0057] like Figure 2 The 205 circuit in the system uses a D flip-flop as its core. When the system starts normally, the Start signal is low to reset the D flip-flop, generating a Reset signal to make the initial values ​​of the control voltages V1 and V2 zero.

[0058] like Figure 5 The diagram shows the overall structure of 109. The input signal is a high-frequency clock CLK, and the output signals are V1 of the voltage-controlled delay line 103 and V2 of the voltage-controlled delay line 104.

[0059] like Figure 7 The lock indication module 501 (LI) shown is composed of XOR operation, AND operation, OR operation and delay module. The XOR operation is performed on the output signal of the frequency detector in the primary delay phase-locked loop to obtain signal D11; the XOR operation is performed on the output signal of the frequency detector in the secondary delay phase-locked loop to obtain signal D21.

[0060] Signal D11 is delayed to obtain signal D12. A bitwise AND operation between D12 and D11 yields signal S1. When signal S1 is low and remains unchanged, it indicates that the primary delay-locked loop (PLL) is locked. Signal D21 is delayed to obtain signal D22. A bitwise AND operation between D22 and D21 yields signal S2. When signal S2 is low and remains unchanged, it indicates that the secondary delay-locked loop (PLL) is locked. Signal S1 and S2 are ORed to obtain signal LI. When signal LI is low and remains unchanged, it indicates that the entire system is locked.

[0061] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A primary and secondary delay phase-locked loop with dual delay lines, characterized in that, include: The system includes a power-on reset module (POR), a primary delay phase-locked loop (DLL1), a secondary delay phase-locked loop (DLL2), and a lockout indicator module (LI); among which... The power-on reset module and the external reset signal are used to generate system operation control signals; The main stage delay phase-locked loop includes a frequency and phase detector module PFD1, a charge pump module CP1, a reset circuit SC, a filter module Filter1, and a main stage voltage-controlled delay line module VCDL1. The secondary delay phase-locked loop includes a frequency and phase detector module PFD2, a charge pump module CP2, a filter module Filter2, and a dual-chain voltage-controlled delay line module VCDL2. The locking indicator module is used to determine whether the two phase-locked loops have completed locking; The power-on reset module is connected to the reset control module of the primary delay phase-locked loop (PLL). The output voltage signal V1 of the primary PLL is connected to the short chain of the secondary dual-chain voltage-controlled delay line. The external input clock signal CLK is connected to the primary PLL and the secondary PLL. The total reset signal generated by the primary PLL is connected to the secondary PLL filter module. The output signals of the frequency and phase detector modules PFD1 and PFD2 are respectively connected to the lock indication module.

2. The primary and secondary delay phase-locked loop with dual delay lines according to claim 1, characterized in that, The voltage-controlled delay line in the secondary delay phase-locked loop is a double chain, and the delay unit in the first delay chain is the same as the delay unit in the primary delay line.

3. A primary and secondary delay phase-locked loop with dual delay lines according to claim 1, characterized in that, The reset signal of the power-on reset circuit is a ramp signal during the power-on process of the circuit, which is used to prevent the phase-locked loop from locking incorrectly during power-on.

4. A primary and secondary delay phase-locked loop with dual delay lines according to claim 1, characterized in that, The locking indication module performs an XOR operation on the two output signals of the frequency and phase detector in the primary delay phase-locked loop, and then performs an AND operation on the resulting signal after a short delay. The secondary delay phase-locked loop performs the same operation, and finally performs an OR operation on the two resulting signals.

5. A primary and secondary delay phase-locked loop with dual delay lines according to claim 2, characterized in that, The delay time of the second delay chain of the secondary dual-chain voltage-controlled delay line is equal to the accuracy of the digital pulse width modulator, and the total delay time of the delay chain is the delay time after the primary delay unit is locked.

6. A primary and secondary delay phase-locked loop with dual delay lines according to claim 2, characterized in that, In the aforementioned secondary delay phase-locked loop dual-chain structure, after the primary delay phase-locked loop is locked, the total time of the first chain of the secondary delay phase-locked loop is determined, the input reference signal of the frequency and phase detector of the secondary delay line is determined, and its output signal locks the secondary delay phase-locked loop by controlling the charging and discharging of the capacitor through the charge pump, thus obtaining the locking voltage V2.

7. A primary and secondary delay phase-locked loop with dual delay lines according to any one of claims 1-6, characterized in that, The delay time and number of delay units of the primary delay line are determined based on the period of the input clock signal. The number of delay units and delay time of the secondary delay line are determined based on the delay accuracy and the number of delay units of the primary delay line.

8. A secondary dual-delay-line primary-secondary delay phase-locked loop according to claim 1, characterized in that, The frequency and phase detector modules PFD1 and PFD2 are equipped with parasitic capacitors to precharge the circuit before the rising edge of the input signal arrives, thereby increasing the circuit's operating speed. The circuit uses a smaller channel length and a larger aspect ratio to reduce the conduction time of the frequency and phase detectors.

9. A primary and secondary delay phase-locked loop with dual delay lines according to claim 1, characterized in that, The charge pump modules CP1 and CP2 have their charge / discharge switches located at the source end to reduce charge sharing.

10. A primary and secondary delay phase-locked loop with dual delay lines according to claim 1, characterized in that, Both the main-stage voltage-controlled delay line module VCDL1 and the dual-chain voltage-controlled delay line module VCDL2 are equipped with delay units. They adopt a pseudo-differential structure to control the voltage control adjustment characteristics of the delay time by controlling the RC time constant of the output node. The delay time increases as the control voltage increases.

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