A filter device packaging method and structure

Abstract

The application discloses a filter device packaging method and structure, and belongs to the field of integrated circuit packaging. The application uses laser local bonding technology to make a silicon-based groove wafer and a glass wafer electric performance adapter plate form a cavity sealing protection area of a filter chip, and through copper columns, metal pads and rewiring metal layers, electric signals of the filter are transmitted from the inside of the chip to the outside through bumps, so that the filter device packaging is realized. The application uses the silicon-based groove wafer as a carrier, embeds the filter chip, and ingeniously uses the glass wafer electric performance adapter plate with better insulation as a vertical interconnection means and a protective cover to construct a cavity and a lead-out end. Then, through a rewiring fan-out method, the contact area and the rewiring density are greatly increased, the bonding difficulty is reduced, the reliability of the device is improved, the manufacturing method is simple, and the application is suitable for large-scale mass production.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit packaging technology, in particular to a filter device packaging method and structure. BACKGROUND

[0002] With the development of 5G communication and the Internet of Things, the integration complexity of high-end intelligent devices is increasingly high, and the demand for radio frequency anti-interference of signals is rapidly increasing. The frequency bands supported by each device are increasingly improved, and the interference from itself and other devices is increasingly large. The application of high-performance BAW filters has a very high performance advantage, and the miniaturized BAW filter chip device is very suitable for high-frequency band signal processing.

[0003] Currently, filter devices are manufactured on wafers, a cavity wafer is bonded on the BAW filter wafer to form a filter device wafer, and finally cut to form a filter device chip. The manufacturing process cost is much higher than that of the relatively low-performance SAW bulk filter. In the high-frequency signal band, the BAW filter is currently the only choice.

[0004] In the next few years, there will be more and more demand for high-frequency and high-performance BAW filters, and a new process needs to be developed to reduce the manufacturing cost of filter devices, which is more conducive to the popularization and development of BAW filters. SUMMARY

[0005] The purpose of the present application is to provide a filter device packaging method and structure to solve the problems of complex device processing process and unstable cavity structure of traditional BAW chips.

[0006] To solve the above technical problems, the present application provides a filter device packaging method, comprising:

[0007] A filter wafer is provided, which has a filter functional area thereon;

[0008] Copper pillars and Sn caps on the copper pillars are prepared on the filter functional area;

[0009] Independent filter chips are formed by dicing;

[0010] In addition, a silicon-based groove wafer is provided, which has a uniform array of grooves etched on the front surface;

[0011] The filter chips are embedded in the bottom of the grooves of the silicon-based groove wafer through a DAF bonding layer;

[0012] A glass wafer electrical performance adapter plate is prepared, and the bottom surface of the glass wafer electrical performance adapter plate and the upper surface of the silicon-based groove wafer with the embedded filter chips are fully pressed together; a local bonding area is formed by heating the pressed surface along the four sides of the groove through laser, and the filter chips are integrally sealed;

[0013] After the whole sealed filter chip is laser bonded, a rewiring metal layer is formed on the front surface of the glass wafer electrical performance adapter plate; a rewiring passivation layer is formed through a photoetching process;

[0014] The uppermost layer of the wiring layer opening is exposed through photoetching, a copper pillar bump is formed, and a Sn cap bump is formed on the copper pillar bump;

[0015] The final wafer-level filter device chip is formed through dicing.

[0016] Optionally, the copper pillar and the Sn cap are prepared through a rewiring process including photoetching, metal film deposition, and electroplating, and the copper pillar is prepared at the pad of the filter functional area.

[0017] Optionally, after the independent filter chip is formed through dicing, the filter device packaging method further comprises:

[0018] The filter chip is cleaned using a chemical reagent, so that the surface activity of the filter functional area is exposed, thereby having electrical performance of the filter chip.

[0019] Optionally, the front surface of the silicon-based groove wafer, i.e., the wafer surface on which the array grooves are located, is a polished surface, and the size of each groove can accommodate a single filter chip.

[0020] Optionally, after the filter chip is embedded in the groove, the Sn cap on the copper pillar exposes the upper surface of the silicon-based groove wafer.

[0021] Optionally, the method for preparing the glass wafer electrical performance adapter plate comprises: providing a TGV adapter plate with metal pads on the surface; forming a glass through hole TGV in the TGV adapter plate through laser drilling, and forming a copper pillar in the glass through hole TGV, to finally form a glass wafer electrical performance adapter plate, wherein the surface on which the metal pads are located is a glass polished surface, i.e., the bottom surface of the glass wafer electrical performance adapter plate.

[0022] Optionally, after the glass wafer electrical performance adapter plate and the silicon-based groove wafer are bonded, the bottom surface of the glass wafer electrical performance adapter plate and the polished surface of the silicon-based groove wafer are at the same level and are fully bonded; the whole sealed filter chip is reflowed, so that the copper pillar is welded to the copper pillar in the glass through hole TGV, to realize conduction.

[0023] The application further provides a filter device packaging structure, comprising a filter chip, a silicon-based groove wafer, and a glass wafer electrical performance adapter plate; the silicon-based groove wafer is etched with uniform array grooves, the filter chip is embedded in the groove, and the bottom surface of the glass wafer electrical performance adapter plate and the upper surface of the silicon-based groove wafer are fully bonded;

[0024] The top surface of the glass wafer electrical performance adapter plate is sequentially provided with a rewiring metal layer, a rewiring passivation layer, a copper column bump and a Sn cap bump.

[0025] Optionally, the filter chip comprises a filter wafer, and the filter wafer is provided with a filter functional area; a copper pillar and a Sn cap on the copper pillar are prepared at a pad of the filter functional area.

[0026] Optionally, the glass wafer electrical performance adapter plate comprises a TGV adapter plate, and the TGV adapter plate is provided with a metal pad; a glass through hole TSV is formed in the TGV adapter plate, and the glass through hole TSV is filled with a copper column; and the copper column is in conduction with the Sn cap and the copper pillar through the metal pad.

[0027] In the filter device packaging method and structure provided by the application, the laser local bonding technology is used to form a cavity sealing protection area of the filter chip by the silicon-based groove wafer and the glass wafer electrical performance adapter plate, and the filter electrical signal is transmitted from the inside of the chip to the outside through the bump and the external connection through the copper column, the metal pad and the rewiring metal layer, so that the filter device packaging is realized. The application uses the silicon-based groove wafer as a carrier, embeds the filter chip, and ingeniously uses the glass wafer electrical performance adapter plate with better insulation as a vertical interconnection means and a protective cover to construct a cavity and a lead-out end. Then, the rewiring fan-out method is used to greatly increase the contact area and the rewiring density, reduce the bonding difficulty, improve the reliability of the device, and the manufacturing method is simple and suitable for large-scale mass production. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structural schematic diagram of a filter wafer with a filter functional area;

[0029] Figure 2 is a structural schematic diagram of preparing a copper pillar and a Sn cap on the filter functional area;

[0030] Figure 3 is a structural schematic diagram of forming an independent filter chip by dicing;

[0031] Figure 4 is a schematic diagram of a silicon-based groove wafer with a uniform array groove etched on the front surface;

[0032] Figure 5 is a schematic diagram of embedding a filter chip in a silicon-based groove wafer;

[0033] Figure 6 is a schematic diagram of a glass wafer electrical performance adapter plate provided by the application;

[0034] Figure 7is a schematic diagram of the full compression of the glass wafer electrical performance adapter plate and the silicon-based groove wafer;

[0035] Figure 8 is a schematic diagram of N-layer rewiring layer on the top surface of the glass wafer electrical performance adapter plate;

[0036] Figure 9 is a schematic diagram of forming copper pillar bumps and Sn cap bumps on the N-layer rewiring layer;

[0037] Figure 10 is a schematic diagram of cutting to form the final wafer-level filter device chip. DETAILED DESCRIPTION

[0038] The filter device packaging method and structure provided by the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0039] The present application provides a filter device packaging method, comprising the following steps:

[0040] A filter wafer 201 is provided, which has a filter functional area 202, as shown in Figure 1 ;

[0041] As shown in Figure 2 , on the filter wafer 201, copper pillars 102 at the pads in the filter functional area 202 and Sn caps 110 above the copper pillars 102 are prepared through rewiring processes such as photolithography, metal film deposition, and electroplating, wherein the copper pillars 102 serve as a carrier and an electrical performance connection;

[0042] Independent filter chips 101 are formed by dicing, as shown in Figure 3 ; the filter chips 101 are cleaned with chemical reagents such as hydrofluoric acid, so that the surface activity of the filter functional area 202 is exposed, thereby having filter chip electrical performance;

[0043] A silicon-based groove wafer 104 with a uniform array of grooves etched on the front surface is provided through etching technology, as shown in Figure 4 ; it should be noted that the front surface of the silicon-based groove wafer 104, i.e., the wafer surface where the array of grooves is located, is a polished surface, and each groove can accommodate a single filter chip;

[0044] As shown in Figure 5As shown, the filter chip 101 is attached to the bottom of the groove of the silicon-based groove wafer 104 through the DAF bonding layer 103, that is, the filter chip 101 is embedded in the silicon-based groove wafer 104 by a die-mounting method. It should be noted that after embedding, the Sn cap 110 on the copper pillar 102 of the filter chip 101 is slightly exposed on the upper surface of the silicon-based groove wafer 104, with an exposed height of a few micrometers.

[0045] A TGV adapter board 106 is provided, with metal pads 112 on its surface; a glass through-hole TGV is formed by laser drilling, and copper pillars 107 inside the glass through-hole TGV are formed through processes such as PECVD, PVD, photolithography, and electroplating, ultimately forming a... Figure 6 The glass wafer electrical performance adapter board shown is shown. It should be emphasized that the surface where the metal pad 112 is located is the polished glass surface, which is also the bottom surface of the glass wafer electrical performance adapter board.

[0046] Will as Figure 6 The bottom surface of the glass wafer electrical performance adapter plate shown is as follows: Figure 5 The upper surface of the polished silicon-based grooved wafer 104 shown is fully pressed together, as... Figure 7 As shown. Due to the action of the DAF bonding layer, the Sn cap 110 on the copper pillar 102 is fully pressed into contact with the metal pad 112. Simultaneously, the bottom surface of the glass wafer electrical performance adapter plate is at the same level and fully adhered to the polished surface of the silicon-based groove wafer 104. A local bonding area 105 is formed by heating the polished surface along the perimeter of the groove using a laser, resulting in a complete sealed filter chip.

[0047] The laser-bonded integral sealed filter chip is reflowed so that the copper pillar 102 is welded to the copper pillar 107 in the glass through-hole TGV to achieve conductivity.

[0048] After laser bonding, a redistribution metal layer 108 is formed on the front surface of the overall sealed filter chip using a glass wafer electrical performance adapter plate, through processes such as photolithography, metal thin film deposition, and electroplating. A redistribution passivation layer 111 is then formed using photolithography. Figure 8 As shown;

[0049] The opening in the topmost wiring layer is exposed by photolithography. Copper pillar bumps 109 with internal and external electrical connections are formed by PVD and electroplating. Sn cap bumps 113 are formed on the copper pillar bumps 109. Figure 9 As shown;

[0050] like Figure 10 As shown, the final wafer-level filter device chip is formed by cutting.

[0051] The above description is only the description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any change and modification made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A filter device packaging method, characterized by, The application relates to a filter device packaging method and a filter device packaging structure. A filter wafer is provided, which has a filter functional area thereon; A copper pillar and a Sn cap on the copper pillar are prepared on the filter functional area; An independent filter chip is formed by dicing; A silicon-based groove wafer is additionally provided, which has a uniform array groove etched on the front surface; The filter chip is embedded into the bottom of the groove of the silicon-based groove wafer through a DAF bonding layer; A glass wafer electrical performance adapter plate is prepared, and the bottom surface of the glass wafer electrical performance adapter plate and the upper surface of the silicon-based groove wafer embedding the filter chip are fully pressed; a local bonding area is formed by heating the pressing surface along the groove periphery through laser, and the filter chip is integrally sealed; After laser bonding of the integrally sealed filter chip, a rewiring metal layer is formed on the front surface of the glass wafer electrical performance adapter plate; and a rewiring passivation layer is formed through a photoetching process; A copper pillar bump is formed by exposing the uppermost layer of the wiring layer opening through photoetching, and a Sn cap bump is formed on the copper pillar bump; The final wafer-level filter device chip is formed by cutting; wherein The method for preparing the glass wafer electrical performance adapter plate comprises the following steps: a TGV adapter plate is provided, which has metal pads on the surface; a glass through hole TGV is formed in the TGV adapter plate through laser drilling, and a copper pillar is formed in the glass through hole TGV, so that the glass wafer electrical performance adapter plate is finally formed, wherein the surface with the metal pads is the glass polishing surface, that is, the bottom surface of the glass wafer electrical performance adapter plate.

2. The filter device packaging method of claim 1, wherein, The copper pillar and the Sn cap are prepared through a rewiring process comprising photoetching, metal film deposition and electroplating, and the copper pillar is prepared at the pad of the filter functional area.

3. The filter device packaging method of claim 2, wherein, After the independent filter chip is formed by dicing, the filter device packaging method further comprises the following steps: The filter chip is cleaned by using a chemical reagent, so that the surface activity of the filter functional area is exposed, and the filter chip has electrical performance.

4. The filter device packaging method of claim 3, wherein, The front surface of the silicon-based groove wafer, that is, the wafer surface with the array groove, is a polishing surface, and the size of each groove can accommodate a single filter chip.

5. The filter device packaging method of claim 4, wherein, After the filter chip is embedded into the groove, the Sn cap on the copper pillar exposes the upper surface of the silicon-based groove wafer.

6. The filter device packaging method of claim 1, wherein, After the glass wafer electrical performance adapter plate and the silicon-based groove wafer are pressed, the bottom surface of the glass wafer electrical performance adapter plate and the polishing surface of the silicon-based groove wafer are at the same level and are fully attached; the integrally sealed filter chip is reflowed, so that the copper pillar is welded to the copper pillar in the glass through hole TGV, and conduction is realized.

7. A filter device package structure based on the filter device package method of claim 1, characterized by, The application relates to a filter device packaging method and a filter device packaging structure. The top surface of the glass wafer electrical performance adapter plate is sequentially provided with a rewiring metal layer, a rewiring passivation layer, a copper pillar bump and a Sn cap bump. The glass wafer electrical performance adapter plate comprises a TGV adapter plate, the TGV adapter plate is provided with a metal pad on the surface; a glass through hole TSV is formed in the TGV adapter plate, and the glass through hole TSV is filled with a copper column; wherein the copper column is in conduction with the copper column through the metal pad and the Sn cap.

8. The filter device package structure of claim 7, wherein, The filter chip comprises a filter wafer, and the filter wafer is provided with a filter functional area; a copper column and a Sn cap on the copper column are prepared at a pad of the filter functional area.

9. The filter device package structure of claim 8, wherein, The glass wafer electrical performance adapter plate comprises a TGV adapter plate, the TGV adapter plate is provided with a metal pad on the surface; a glass through hole TSV is formed in the TGV adapter plate, and the glass through hole TSV is filled with a copper column; wherein the copper column is in conduction with the copper column through the metal pad and the Sn cap.

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