Level conversion circuit, method, integrated circuit, and electronic device

Abstract

The application discloses a level conversion circuit, a method, an integrated circuit and an electronic device. The level conversion circuit comprises a signal input module, a signal output module and a positive feedback module. The signal input module is used for generating an intermediate signal according to an input signal of a first end of the signal input module and transmitting the intermediate signal to a first intermediate node. The signal output module is used for generating an output signal according to the intermediate signal of the first intermediate node and transmitting the output signal to a second end of the signal output module. The positive feedback module is used for adjusting the level value of the intermediate signal of the signal input module according to the output signal during a conversion process in which the level value of the output signal is converted from an initial level to a target level, thereby accelerating the conversion speed and meeting the transmission requirement of high-speed signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and more particularly, to a level conversion circuit, a method, and an electronic device and a method. BACKGROUND

[0002] With the rapid development of technology, integrated circuits (such as system on chip, SOC) have been widely used in various electronic devices, such as mobile phones, tablet computers, notebook computers, etc. To make the integrated circuit work energy-saving and efficiently, each module in the integrated circuit should be allowed to run at different and appropriate voltages according to different needs. Therefore, multi-power voltage domain technology is widely used in integrated circuits.

[0003] In the integrated circuit applying the multi-power voltage domain technology, the level conversion circuit is an important module, which provides an interactive way for the modules working at different voltages, and ensures the correct transmission of signals between voltage domains. However, the rising and falling delays of the input and output signals of the traditional level conversion circuit are relatively long, which has a great impact on high-speed signals, and is not suitable for high-speed and high-performance integrated circuits. SUMMARY

[0004] In view of the above problems, the present application provides a level conversion circuit, a method, an integrated circuit, and an electronic device to improve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a level conversion circuit. The circuit includes a signal input module, a signal output module, and a positive feedback module. The first end of the signal input module is connected to a first reference voltage, the second end of the signal input module is grounded, the third end of the signal input module is connected to the first end of the signal input module, and the fourth end of the signal input module is connected to a first intermediate node; the signal input module is used to generate an intermediate signal according to the input signal of the first end of the signal input module, and transmit the intermediate signal to the first intermediate node. The first end of the signal output module is connected to the first intermediate node, the second end of the signal output module is used to transmit an output signal, the third end of the signal output module is connected to the first reference voltage, and the fourth end of the signal output module is grounded; the signal output module is used to generate an output signal according to the intermediate signal of the first intermediate node, and transmit the output signal to the second end of the signal output module. The first end of the positive feedback module is connected to the first intermediate node, the second end of the positive feedback module is connected to the first reference voltage, and the third end of the positive feedback module is connected to the second end of the signal output module; the positive feedback module is used to adjust the level value of the intermediate signal of the signal input module according to the output signal during the conversion process of the level value of the output signal from an initial level to a target level, thereby speeding up the conversion speed. Wherein, the initial level is a high level or a low level, when the initial level is a high level, the target level is a low level; when the initial level is a low level, the target level is a high level.

[0006] In a second aspect, the embodiments of the present application provide a level conversion method, and the implementation steps of the method include: generating an intermediate signal according to a received input signal; generating an output signal according to the intermediate signal; and adjusting the level value of the intermediate signal according to the output signal during a conversion process in which the level value of the output information is converted from an initial level to a target level, so as to accelerate the conversion speed of the conversion process.

[0007] In a third aspect, the embodiments of the present application provide an integrated circuit, which comprises the level conversion circuit.

[0008] In a fourth aspect, the embodiments of the present application provide an electronic device, which comprises the level conversion circuit or the integrated circuit.

[0009] The level conversion circuit and method provided by the present application comprise a signal input module, a signal output module and a positive feedback module. The signal input module is configured to generate an intermediate signal according to an input signal at a first end of the signal input module and transmit the intermediate signal to a first intermediate node. The signal output module is configured to generate an output signal according to the intermediate signal at the first intermediate node and transmit the output signal to a second end of the signal output module. The positive feedback module is configured to adjust the level value of the intermediate signal of the signal input module according to the output signal during a conversion process in which the level value of the output signal is converted from an initial level to a target level, so as to accelerate the conversion speed and meet the transmission requirement of high-speed signals. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0011] Figure 1 A structure schematic diagram of a level conversion circuit provided by the embodiments of the present application is shown.

[0012] Figure 2 A structure schematic diagram of a signal input module provided by the embodiments of the present application is shown.

[0013] Figure 3 A structure schematic diagram of a first unit provided by the embodiments of the present application is shown.

[0014] Figure 4 A structure schematic diagram of a second unit provided by the embodiments of the present application is shown.

[0015] Figure 5 A structure schematic diagram of a second inverter provided by the embodiments of the present application is shown.

[0016] Figure 6 A structure diagram of a third unit provided by the embodiment of the application is shown.

[0017] Figure 7 A structure diagram of another third unit provided by the embodiment of the application is shown.

[0018] Figure 8 A structure diagram of a signal output module provided by the embodiment of the application is shown.

[0019] Figure 9 A structure diagram of a second inverter provided by the embodiment of the application is shown.

[0020] Figure 10 A structure diagram of a positive feedback module provided by the embodiment of the application is shown.

[0021] Figure 11 A structure diagram of another level conversion circuit provided by the embodiment of the application is shown.

[0022] Figure 12 A structure diagram of a reset module provided by the embodiment of the application is shown.

[0023] Figure 13 A flow diagram of another level conversion circuit provided by the embodiment of the application is shown.

[0024] Figure 14 A transient simulation waveform diagram of a level conversion circuit provided by the embodiment of the application is shown.

[0025] Figure 15 A flow diagram of a level conversion circuit provided by the embodiment of the application is shown.

[0026] Figure 16 A structure diagram of an integrated circuit provided by the embodiment of the application is shown.

[0027] Figure 17 A structure diagram of an electronic device provided by the embodiment of the application is shown.

[0028] Figure 18 A structure diagram of another electronic device provided by the embodiment of the application is shown.

[0029] BRIEF DESCRIPTION OF DRAWINGS: 100, level conversion circuit, 110, signal input module, 110a, first end of signal input module; 110b, second end of signal input module; 110c, third end of signal input module; 111, first unit, 111a, first end of first unit, 111b, second end of first unit, 111c, third end of first unit; 1111, second switch tube, 1111a, first end of second switch tube, 1111b, second end of second switch tube, 1111c, third end of second switch tube; 112, second unit, 112a, first end of second unit, 112b, second end of second unit, 112c, third end of second unit, 112d, fourth end of second unit; 1121, first inverter, 1121a, first end of first inverter, 1121b, second end of first inverter; 11211, fifth switch tube, 11211a, first end of fifth switch tube, 11211b, second end of fifth switch tube, 11211c, third end of fifth switch tube; 11212, sixth switch tube, 11212a, first end of sixth switch tube, 11212b, second end of sixth switch tube, 11212c, third end of sixth switch tube; 1122, third switch tube, 1122a, first end of third switch tube, 1122b, second end of third switch tube, 1122c, third end of third switch tube; 1123, fourth switch tube, 1123a, first end of fourth switch tube, 1123b, second end of fourth switch tube, 1123c, third end of fourth switch tube; 113, third unit, 113a, first end of third unit, 113b, second end of third unit, 113c, third end of third unit, 113d, fourth end of third unit; 1131, seventh switch tube, 1131a, first end of seventh switch tube, 1131b, second end of seventh switch tube, 1131c, third end of seventh switch tube; 1132, eighth switch tube, 1132a, first end of eighth switch tube, 1132b, second end of eighth switch tube, 1132c, third end of eighth switch tube; 120, signal output module, 120a, first end of signal output module, 120b, second end of signal output module, 120c, third end of signal output module, 120d, fourth end of signal output module; 121, second inverter, 121a, first end of second inverter, 121b, second end of second inverter, 121c, third end of second inverter, 121d, fourth end of second inverter; 1211, ninth switch tube, 1211a, first end of ninth switch tube, 1211b, second end of ninth switch tube, 1211c, third end of ninth switch tube; 1212, tenth switch tube, 1212a, first end of tenth switch tube, 1212b, second end of tenth switch tube, 1212c, third end of tenth switch tube;130, positive feedback module, 130a, first end of the positive feedback module, 130b, second end of the positive feedback module, 130c, third end of the positive feedback module, 131, eleventh switch tube, 131a, first end of the eleventh switch tube, 131b, second end of the eleventh switch tube, 131c, third end of the eleventh switch tube; 140, reset module, 140a, first end of the reset module, 140b, second end of the reset module, 140c, third end of the reset module; 141, first switch tube, 141a, first end of the first switch tube, 141b, second end of the first switch tube, 141c, third end of the first switch tube; IN, input signal, OUT, output signal, RST, reset signal, V1, first reference voltage, V2, second reference voltage, A, first intermediate node, B, second intermediate node, C, third intermediate node; 300, integrated circuit; 400, electronic device, 410, shell. DETAILED DESCRIPTION

[0030] In order to enable personnel in the technical field to better understand the scheme of the present application, the technical scheme in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application.

[0031] With the rapid development of science and technology, integrated circuits (such as system on chip (SOC)) have been widely applied to various electronic devices, such as mobile phones, tablet computers, notebook computers, etc. In order to make the integrated circuit work in an energy-saving and efficient manner, each module in the integrated circuit should be allowed to operate at different and appropriate voltages according to different requirements. Generally, modules with critical timing usually operate at a relatively high power supply voltage to meet the speed performance index of the chip; modules with low timing requirements usually operate at a relatively low power supply voltage to reduce the power consumption of the chip. Therefore, the multi-power voltage domain technology is widely applied to integrated circuits. In the integrated circuit applying the multi-power voltage domain technology, a level conversion circuit is an important module, which provides an interaction path for modules operating at different voltage domains and ensures the correct transmission of signals between voltage domains. When a signal is converted from a high voltage domain to a low voltage domain, a general buffer can be used to realize the cross-voltage domain transmission of the signal; when a signal is converted from a low voltage domain to a high voltage domain, a relatively complex level conversion circuit is required.

[0032] However, the inventors found in the research that the conventional level conversion circuit commonly used at present is not quite suitable for high-speed data transmission. Specifically, the rising and falling delay of the input and output signals of the conventional level conversion circuit is long, which is not conducive to the integrity of high-speed signals, and further leads to signal distortion. The conventional level conversion circuit commonly used at present includes a cross-coupled level conversion circuit and a level conversion circuit based on a current mirror, and both of them have the problem of long rising and falling delay of the input and output signals. Therefore, the conventional level conversion circuit is not suitable for high-speed signal transmission, and cannot be applied to high-speed and high-performance integrated circuits, which has great limitations.

[0033] In order to improve the above problems, the inventors provide a level conversion circuit, a method, an integrated circuit and an electronic device, wherein the level conversion circuit comprises a signal input module, a signal output module and a positive feedback module. The signal input module is used to generate an intermediate signal according to the input signal of the first end of the signal input module, and transmit the intermediate signal to the first intermediate node. The signal output module is used to generate an output signal according to the intermediate signal of the first intermediate node, and transmit the output signal to the second end of the signal output module. The positive feedback module is used to adjust the level value of the intermediate signal of the signal input module according to the output signal during the conversion process of the level value of the output signal from an initial level to a target level, so as to speed up the conversion speed and meet the transmission requirements of high-speed signals.

[0034] The level conversion circuit provided by the embodiments of the present application will be described in detail below through specific embodiments.

[0035] Please refer to Figure 1 The level conversion circuit 100 provided by the embodiments of the present application comprises a signal input module 110, a signal output module 120 and a positive feedback module 130.

[0036] In the embodiments of the present application, the first end 110a of the signal input module 110 is connected to the first reference voltage V1, the second end 110b of the signal input module 110 is grounded, the third end 110c of the signal input module 110 is used to receive an input signal IN, and the fourth end 110d of the signal input module 110 is connected to the first intermediate node A. The signal input module 110 is used to generate an intermediate signal according to the input signal IN of the first end 110a of the signal input module 110, and transmit the intermediate signal to the first intermediate node A.

[0037] The input signal IN refers to a signal to be level converted. The input signal IN has different states according to different level change conditions of the input signal IN. For example, the input signal IN can be static, i.e., the level state of the input signal IN remains unchanged. For example, the input signal IN can remain in a high level state; the input signal IN can also remain in a low level state. For another example, the input signal IN can be dynamic, i.e., the level state of the input signal IN changes dynamically. For example, the input signal IN can be converted from a low level state to a high level state; the input signal IN can also be converted from a high level state to a low level state.

[0038] In some embodiments, when the voltage of the input signal IN is a preset voltage, the level state of the input signal IN is a high level state. When the voltage of the input signal IN is zero, the level state of the input signal IN is a low level state.

[0039] In some embodiments, the level state of the intermediate signal changes following the level state change of the input signal IN, and is opposite to the change direction of the input signal.

[0040] For example, when the input signal IN remains in a high level state, the intermediate signal remains in a low level state. When the input signal IN is converted from a low level state to a high level state, the intermediate signal is converted from a high level state to a low level state.

[0041] In the embodiment of the present application, the first end 120a of the signal output module 120 is connected to the first intermediate node A, the second end 120b of the signal output module 120 is used to transmit the output signal OUT, the third end 120c of the signal output module 120 is connected to the first reference voltage V2, and the fourth end 120d of the signal output module 120 is grounded. The signal output module 120 is used to generate the output signal OUT according to the intermediate signal of the first intermediate node A.

[0042] In the embodiment of the present application, the output signal OUT refers to a signal obtained by level converting the input signal IN. According to different level change conditions of the output signal OUT, for example, the output signal OUT can be static, i.e., the level state of the output signal OUT remains unchanged. For example, the output signal OUT can remain in a high level state; the output signal OUT can also remain in a low level state. For another example, the output signal OUT can be dynamic, i.e., the level state of the output signal OUT changes dynamically. For example, the output signal OUT can be converted from a low level state to a high level state; the output signal OUT can also be converted from a high level state to a low level state.

[0043] In some embodiments, the level state of the output signal OUT changes following the level state change of the intermediate signal, and is opposite to the change direction of the intermediate signal.

[0044] For example, when the intermediate signal remains in the high level state, the output signal OUT remains in the low level state. When the intermediate signal is converted from the low level state to the high level state, the output signal OUT is converted from the high level state to the low level state.

[0045] That is, when the level state of the input signal IN changes, the level state of the intermediate signal changes following the level state of the input signal IN, and the change direction is opposite to that of the input signal IN; the output signal OUT changes following the level state of the intermediate signal, and the change direction is opposite to that of the intermediate signal; so as to realize that the level state of the output signal OUT changes following the level state of the input signal IN, and the change direction is the same as that of the input signal IN.

[0046] In some embodiments, the first reference voltage V1 is greater than the preset voltage, that is, the voltage range of the output signal OUT is greater than that of the input signal IN, so that the level conversion circuit 100 of the embodiment can realize conversion of the input signal IN in the low voltage field to the output signal OUT in the high voltage field.

[0047] In the embodiment, the first end 130a of the positive feedback module 130 is connected to the first intermediate node A, the second end 130b of the positive feedback module 130 is connected to the first reference voltage V1, and the third end 130c of the positive feedback module 130 is connected to the second end 120b of the signal output module 120. The positive feedback module 130 is used to adjust the level value of the intermediate signal of the signal input module 110 according to the output signal OUT during the conversion process of the level value of the output signal OUT from the initial level to the target level, so as to accelerate the conversion speed of the conversion process.

[0048] The initial level refers to the level state of the output signal OUT before the level conversion, and the target level refers to the level state of the output signal OUT after the level conversion is completed.

[0049] For example, when the input signal IN is converted from the low level to the high level, the initial level of the output signal OUT is the low level and the target level is the high level, and during the level conversion process, the level state of the intermediate signal is converted from the high level to the low level, and the positive feedback module 130 reduces the current flowing into the first intermediate node A according to the output signal OUT, so as to accelerate the speed of the level state of the intermediate signal from the high level to the low level.

[0050] When the input signal IN is converted from high level to low level, the initial level of the output signal OUT is high level and the target level is low level, and during the level conversion, the level state of the intermediate signal is converted from low level to high level, and the positive feedback module 130 increases the current flowing into the first intermediate node A according to the output signal OUT, thereby accelerating the speed of the level state of the intermediate signal converted from low level to high level.

[0051] In some embodiments, as shown in FIG. 1, the signal input module 110 includes a first unit 111 and a second unit 112. Figure 2

[0052] The first end 111a of the first unit 111 is connected to the first end 110a of the signal input module 110, the second end 111b of the first unit 111 is connected to the first intermediate node A, and the third end 111c of the first unit 111 is grounded. The first end 111a of the first unit 111 receives the input signal IN, and when the input signal IN is high level, the first unit 111 generates the intermediate signal according to the input signal IN and outputs the intermediate signal through the second end 111b of the first unit 111.

[0053] In some embodiments, as shown in FIG. 1, the first unit 111 includes a second switch tube 1111. The first end 1111a of the second switch tube 1111 is connected to the first end 110a of the signal input module 110, the second end 111b of the second switch tube 1111 is grounded, and the third end 1111c of the second switch tube 1111 is connected to the first intermediate node A. Figure 3 When the input signal IN is high level, the second switch tube 1111 is turned on, and the path between the first intermediate node A and the ground is connected, thereby changing the level state of the intermediate signal flowing to the first intermediate node A. When the input signal IN is low level, the second switch tube 1111 is turned off, and the path between the first intermediate node A and the ground is disconnected.

[0054] Optionally, the second switch tube 1111 is an enhancement mode NMOS tube.

[0055] The first end 112a of the second unit 112 is connected to the first end 110a of the signal input module 110, the second end 112b of the second unit 112 is connected to the first intermediate node A, and the third end 112c of the second unit 112 is connected to the first reference voltage V2. The first end 112a of the second unit 112 receives the input signal IN, and when the input signal IN is low level, the second unit 112 generates the intermediate signal according to the input signal IN and outputs the intermediate signal through the second end 112b of the second unit 112.

[0056] In some embodiments, as shown in FIG. 1, the signal input module 110 includes a first unit 111 and a second unit 112.

[0057] Figure 4 ​​As shown, the second unit 112 includes a first inverter 1121, a third switch tube 1122, and a fourth switch tube 1123. The first end 1121a of the first inverter 1121 is connected to the first end 1122a of the third switch tube 1122, and the second end 1121b of the first inverter 1121 is connected to the first intermediate node A.

[0058] In some embodiments, as shown in FIG. 1, the first inverter 1121 includes a fifth switch tube 11211 and a sixth switch tube 11212. Figure 5 As shown, the first inverter 1121 includes a fifth switch tube 11211 and a sixth switch tube 11212. The first end 11211a of the fifth switch tube 11211 is connected to the first intermediate node A, the second end 11211b of the fifth switch tube 11211 is connected to the second reference voltage V2, and the third end 11211c of the fifth switch tube 11211 is connected to the second intermediate node B. The first end 11212a of the sixth switch tube 11212 is connected to the first intermediate node A, the second end 11212b of the sixth switch tube 11212 is grounded, and the third end 11212c of the sixth switch tube 11212 is connected to the second intermediate node B.

[0059] In some embodiments, as shown in FIG. 1, the first inverter 1121 includes a fifth switch tube 11211 and a sixth switch tube 11212.

[0060] In some embodiments, as shown in FIG. 1, the first inverter 1121 includes a fifth switch tube 11211 and a sixth switch tube 11212.

[0061] In some embodiments, as shown in FIG. 1, the first inverter 1121 includes a fifth switch tube 11211 and a sixth switch tube 11212.

[0062] In some embodiments, the first end 1122a of the third switch tube 1122 is connected to the second intermediate node B, the second end 1122b of the third switch tube 1122 is connected to the first end 110b of the signal input module 110, and the third end 1122c of the third switch tube 1122 is connected to the third intermediate node C.

[0063] In some embodiments, the first end 1123a of the fourth switch tube 1123 is connected to the third intermediate node C, the second end 1123b of the fourth switch tube 1123 is connected to the first reference voltage V2, and the third end 1123c of the fourth switch tube 1123 is connected to the first intermediate node A.

[0064] In some embodiments, as shown in FIG. 1, the first inverter 1121 includes a fifth switch tube 11211 and a sixth switch tube 11212.

[0065] When the input signal IN is at a static high level, the second unit 112 does not affect the change of the intermediate signal.

[0066] When the input signal IN changes from high level to low level, the third switch 1122 turns on, thereby turning on the fourth switch 1123, and the intermediate signal changes from low level to high level; then, the first inverter 1121 sets the second intermediate node B to low level according to the high-level intermediate signal, thereby turning off the third switch 1122 and turning off the fourth switch 1123.

[0067] When the input signal IN changes from low level to high level, the second unit 112 does not affect the change of the intermediate signal.

[0068] Optionally, the third switch 1122 is an enhancement-mode NMOS transistor, and the fourth switch 1123 is an enhancement-mode PMOS transistor.

[0069] In some implementations, such as Figure 6 As shown, the signal input module 110 further includes a third unit 113. The third unit 113 is used to maintain the level of the third intermediate node C at a high level when the input signal IN at the first terminal 110a of the signal input module 110 is static.

[0070] Among them, the first terminal 113a of the third unit 113 is connected to the first reference voltage V1, the second terminal 113b of the third unit 113 is connected to the first intermediate node A, the third terminal 113c of the third unit 113 is connected to the third intermediate node C, and the fourth terminal 113d of the third unit 113 is connected to the second terminal 120b of the signal output module 120.

[0071] In some implementations, such as Figure 7 As shown, the third unit 113 includes a seventh switch 1131 and an eighth switch 1132. The first terminal 1131a of the seventh switch 1131 is connected to the second terminal 120b of the signal output module 120, and the second terminal 1131b of the seventh switch 1131 is connected to the first reference voltage V1. The third terminal 1131c of the seventh switch 1132 is connected to the third intermediate node C. The first terminal 1132a of the eighth switch 1132 is connected to the first intermediate node A, the second terminal 1132b of the eighth switch 1132 is connected to the first reference voltage V1, and the third terminal 1132c of the eighth switch 1132 is connected to the third intermediate node C.

[0072] When the input signal IN is at a static low level, the intermediate signal is at a high level, the seventh switch 1131 is turned on, the eighth switch 1132 is turned off, and the level of the third intermediate node C remains at a high level.

[0073] When the input signal IN is a static high level, the intermediate signal is a low level, the seventh switch tube 1131 is off, the eighth switch tube 1132 is on, and the level of the third intermediate node C is kept as a high level.

[0074] When the input signal IN is converted from a high level to a low level, the level of the intermediate signal rises, the seventh switch tube 1131 is on, the eighth switch tube 1132 is off, and the level of the third intermediate node C is set as a low level.

[0075] When the input signal IN is converted from a low level to a high level, the third unit 113 will not affect the change of the intermediate signal.

[0076] Optionally, the seventh switch tube 1131 is an enhancement-mode PMOS tube, and the eighth switch tube 1132 is an enhancement-mode PMOS tube.

[0077] In some embodiments, the first reference voltage V1 is higher than the second reference voltage V2. If the first reference voltage V1 is lower than the second reference voltage V2, the level of the third end 1122c of the third switch tube 1122 can be higher than the second reference voltage V2, and the high voltage can damage the low-voltage device providing the input signal IN, thereby reducing the reliability of the front-end circuit. In the embodiments of the present application, the first inverter 1121 is powered by the second reference voltage V2, the first end 1121a of the first inverter 1121 outputs a high-level signal to control the level of the third end 1122c of the third switch tube 1122 to be less than or equal to the second reference voltage V2, thereby effectively preventing the low-voltage device providing the input signal IN from being damaged by high voltage.

[0078] In some embodiments, as shown in Figure 8 the signal output module 120 includes a second inverter 121. The first end 121a of the second inverter 121 is connected to the first intermediate node A, and the second end 121b of the second inverter 121 is connected to the second end 120b of the signal output module 120.

[0079] In some embodiments, as shown in Figure 9 the second inverter 121 includes a ninth switch tube 1211 and a tenth switch tube 1212. The first end 1211a of the ninth switch tube 1211 is connected to the first intermediate node A, the second end 1211b of the ninth switch tube 1211 is grounded, and the third end 1211c of the ninth switch tube 1211 is connected to the second end 120b of the signal output module 120; the first end 1212a of the tenth switch tube 1212 is connected to the first intermediate node A, the second end 1212b of the tenth switch tube 1212 is connected to the first reference voltage V1, and the third end 1212c of the tenth switch tube 1212 is connected to the second end 120b of the signal output module 120. Optionally, the ninth switch tube 1211 is an enhancement-mode NMOS tube, and the tenth switch tube 1212 is an enhancement-mode PMOS tube.

[0080] When the input signal IN is a static low level, the intermediate signal is a high level, the tenth switch tube 1212 is turned off, the eleventh switch tube 131 is turned on, and the output signal OUT remains a low level.

[0081] When the input signal IN is a static high level, the intermediate signal is a low level, the tenth switch tube 1212 is turned on, the eleventh switch tube 131 is turned off, and the output signal OUT remains a high level.

[0082] When the output signal OUT is converted from a high level to a low level, the tenth switch tube 1212 is turned off, the eleventh switch tube 131 is turned on, and the output signal OUT is converted from a high level to a low level.

[0083] When the output signal OUT is converted from a low level to a high level, the intermediate signal level is lowered, the tenth switch tube 1212 is turned on, the eleventh switch tube 131 is turned off, and the output signal OUT is converted from a low level to a high level.

[0084] The level conversion circuit of the present application does not need to wait for the pull-up switch tube to be turned off during the conversion of the input signal IN from a high level to a low level, and the ninth switch tube 1211 can be directly turned on to connect the path between the ground and the first reference voltage V1, so that the level of the output signal OUT is rapidly lowered, and the lowering speed of the level of the output signal OUT is improved.

[0085] The level conversion circuit of the present application does not need to wait for the pull-up switch tube to be turned off during the conversion of the input signal IN from a low level to a high level, and the tenth switch tube 1212 can be directly turned on to connect the path between the ground and the first reference voltage V1, so that the level of the output signal OUT is rapidly lowered, and the lowering speed of the level of the output signal OUT is improved.

[0086] In some embodiments, as shown in FIG. 1, the positive feedback module 130 includes an eleventh switch tube 131. Figure 10 The first end 131a of the eleventh switch tube 131 is connected to the second end 120b of the signal output module 120, the second end 131b of the eleventh switch tube 131 is connected to the first reference voltage V1, and the third end 131c of the eleventh switch tube 131 is connected to the first intermediate node A.

[0087] When the input signal IN is a static low level, the eleventh switch tube 131 does not affect the change of the intermediate signal.

[0088] When the input signal IN is a static high level, the eleventh switch tube 131 does not affect the change of the intermediate signal.

[0089] When the input signal IN is converted from high level to low level, the output signal OUT is lowered, and the eleventh switch tube 131 is turned on to increase the current flowing to the first intermediate node A, thereby accelerating the rising speed of the intermediate signal.

[0090] When the input signal IN is converted from low level to high level, the output signal OUT is raised, and the eleventh switch tube 131 is turned off to reduce the current flowing to the first intermediate node A, thereby accelerating the falling speed of the intermediate signal.

[0091] Optionally, the eleventh switch tube 131 is an enhancement-mode PMOS tube.

[0092] In some embodiments, the size of the second switch tube 1111 is much larger than that of the eleventh switch tube 131, and when the input signal IN is raised, the second switch tube 1111 is turned on to immediately pull the level of the intermediate signal to low level, and the output signal OUT is raised to high level, without the waiting time for turning off the pull-up switch tube in the traditional cross-coupled level conversion circuit, and the response of the output signal OUT is faster.

[0093] In some embodiments, in the signal maintaining state of the level conversion circuit, the functions of the seventh switch tube 1131, the eighth switch tube 1132, and the eleventh switch tube 131 are to maintain the level of the third intermediate node C and the high level of the intermediate signal, and the sizes of the seventh switch tube 1131, the eighth switch tube 1132, and the eleventh switch tube 131 are small, and only need to provide weak pull-up current in the turned-on state; in the signal changing process of the level conversion circuit, the pull-down current of the third intermediate node C is provided by the third switch tube 1122 in the turned-on state, and the pull-up current and the pull-down current of the intermediate signal are mainly provided by the fourth switch tube 1123 and the second switch tube 1111 in the turned-on state, and the sizes of the second switch tube 1111, the third switch tube 1122, and the fourth switch tube 1123 are large, which can shorten the response time of the signal.

[0094] In some embodiments, as shown in Figure 11 the level conversion circuit of the embodiment of the present application can further include a reset module 140.

[0095] The first end 140a of the reset module 140 is configured to receive a reset signal RST, the second end 140b of the reset module 140 is connected to the second end 120b of the signal output module 120, the third end 140c of the reset module 140 is grounded, and the reset module 140 is configured to set the second end 120b of the output module 120 to a reset level after receiving the reset signal RST.

[0096] In some embodiments, as shown in Figure 12As shown, the reset module 140 includes a first switch tube 141. A first end 141a of the first switch tube 141 is configured to receive a reset signal RST, a second end 141b of the first switch tube 141 is grounded, and a third end 141c of the first switch tube 141 is connected to a second end 120b of the signal output module 120.

[0097] In an embodiment of the present application, the first switch tube 141 is an enhancement mode NMOS tube.

[0098] As shown, the reset module 140 includes a first switch tube 141. A first end 141a of the first switch tube 141 is configured to receive a reset signal RST, a second end 141b of the first switch tube 141 is grounded, and a third end 141c of the first switch tube 141 is connected to a second end 120b of the signal output module 120. Figure 13 As shown, the reset module 140 includes a first switch tube 141. A first end 141a of the first switch tube 141 is configured to receive a reset signal RST, a second end 141b of the first switch tube 141 is grounded, and a third end 141c of the first switch tube 141 is connected to a second end 120b of the signal output module 120.

[0099] In an embodiment of the present application, the signal input module 110 includes a first unit, a second unit, and a third unit.

[0100] The first unit includes a second switch tube 1111. The second switch tube 1111 is an enhancement mode NMOS tube.

[0101] The second unit includes a third switch tube 1122, a fourth switch tube 1123, a fifth switch tube 11211, and a sixth switch tube 11212. The third switch tube 1122 is an enhancement mode NMOS tube, the fourth switch tube 1123 is an enhancement mode PMOS tube, the fifth switch tube 11211 is an enhancement mode PMOS tube, and the sixth switch tube 11212 is an enhancement mode NMOS tube.

[0102] The third unit includes a seventh switch tube 1131 and an eighth switch tube 1132. The seventh switch tube 1131 is an enhancement mode PMOS tube, and the eighth switch tube 1132 is an enhancement mode PMOS tube.

[0103] The signal output module includes a ninth switch tube 1211 and a tenth switch tube 1212. The ninth switch tube 1211 is an enhancement mode NMOS tube, and the tenth switch tube 1212 is an enhancement mode PMOS tube.

[0104] The positive feedback module includes an eleventh switch tube 131. The eleventh switch tube 131 is an enhancement mode PMOS tube.

[0105] The reset module includes a first switch tube 141. The first switch tube 141 is an enhancement mode NMOS tube.

[0106] In the embodiment of the application, the first reference voltage V1 is 1.8V, and the second reference voltage V2 is 1V. When the input signal IN is high, the corresponding voltage is 1V, and when the input signal IN is low, the corresponding voltage is 0V. When the output signal OUT is high, the corresponding voltage is 1.8V, and when the output signal OUT is low, the corresponding voltage is 0V.

[0107] The working process of the level conversion circuit 100 in the embodiment of the application will be described in detail below.

[0108] When the reset signal RST is high, the circuit is in a reset state, and the eleventh switch tube 131 is turned on. At this time, the third end (drain) of the first switch tube is set to low, and thus the output signal OUT is reset to low. At this time, the seventh switch tube 1131 and the eleventh switch tube 131 are turned on, and thus the third end (drain) of the seventh switch tube is set to high. The level conversion circuit 100 in the embodiment of the application has no static current in the reset state.

[0109] When the reset signal RST is low, the level conversion circuit 100 in the embodiment of the application works normally.

[0110] When the input signal IN is static and the input signal IN remains low, the second switch tube 1111 is turned off, and the eleventh switch tube 131 is turned on, so that the intermediate signal is set to high, so that the fifth switch tube 11211 is turned off, the sixth switch tube 11212 is turned on, and thus the third end (drain) of the sixth switch tube is set to low, so that the third switch tube 1122 is turned off. Since the seventh switch tube 1131 is turned on, the third intermediate node C is set to high, so that the tenth switch tube 1212 is turned off and the ninth switch tube 1211 is turned on. Since the second end (source) 1211b of the ninth switch tube is grounded, the output signal OUT remains low.

[0111] When the input signal IN is static and the input signal IN remains high, the second switch tube 1111 is turned on, so that the intermediate signal is set to low, and thus the ninth switch tube 1211 is turned off and the tenth switch tube 1212 is turned on, so that the third end (drain) of the ninth switch tube is set to high, i.e. the output signal OUT remains high.

[0112] When the input signal IN is static, the seventh switch tube 1131, the eighth switch tube 1132 and the eleventh switch tube 131 serve to maintain the high level state of the intermediate signal and the third intermediate node C. The seventh switch tube 1131, the eighth switch tube 1132 and the eleventh switch tube 131 have small sizes and only need to provide weak pull-up current in the on state.

[0113] When the input signal IN is dynamic, as it rises from low to high, the second switch 1111 changes from off to on, providing a pull-down path for the first intermediate node A. The eleventh switch 131 is initially on, but only provides a weak pull-up current, causing the intermediate signal level to drop from high to low. When the first intermediate node A goes low, the ninth switch 1211 turns off while the tenth switch 1212 turns on, causing the output signal OUT to rise.

[0114] The first terminal (gate) of the eleventh switch 131 is connected to the second terminal of the signal output module. Under the action of the output signal OUT, the eleventh switch 131 is gradually turned off. Therefore, the current flowing from the eleventh switch 131 to the first intermediate node A gradually decreases, which also accelerates the decrease of the intermediate signal level. The rise speed of the output signal OUT level is also accelerated until it is converted to a high level.

[0115] When the input signal IN is dynamic, as it drops from high to low, the second switch 1111 changes from on to off. In some embodiments, the third switch 1122 can be much larger than the eighth switch 1132. When the third switch 1122 changes from off to on, the level of the third intermediate node C drops rapidly to near low, so the fourth switch 1123 turns on. The fourth switch 1123 then connects the path between the first intermediate node A and the first reference voltage V1, causing the level of the intermediate signal to rise, and consequently, the level of the output signal OUT to fall.

[0116] Since the first terminal (gate) of the eleventh switch is connected to the second terminal 120b of the signal output module, under the action of the output signal OUT, the eleventh switch 131 changes from off to on, increasing the current flowing from the eleventh switch 131 to the first intermediate node A, thereby accelerating the rise speed of the intermediate signal level, and the fall speed of the output signal OUT level is also accelerated until it is converted to a low level.

[0117] Furthermore, as the level of the intermediate signal rises, the fifth switch 11211 turns off while the sixth switch 11212 turns on, so the level of the second intermediate node B drops until it reaches a low level, and the third switch 1122 eventually turns off.

[0118] The transient simulation waveform of the level conversion circuit 100 in this embodiment is as follows: Figure 14 As shown, in the embodiments of this application, the frequency of the input signal IN is 1 GHz, which is... Figure 14 It is known that the delay of level conversion is less than 90 ps (picoseconds). Therefore, the level conversion circuit 100 of this application embodiment can effectively shorten the response time of the output signal OUT change and improve the speed of level conversion.

[0119] As Figure 15 shown, the embodiment of the present application also provides a level conversion method, and the method steps of the method comprise:

[0120] Step 210, generating an intermediate signal according to the received input signal.

[0121] Step 220, generating an output signal according to the intermediate signal.

[0122] Step 230, in the conversion process of the level value of the output signal from the initial level to the target level, adjusting the level value of the intermediate signal according to the output signal, so as to accelerate the conversion speed of the conversion process.

[0123] As Figure 16 shown, the embodiment of the present application also provides an integrated circuit 300, and the integrated circuit 300 comprises the above-mentioned level conversion circuit 100.

[0124] The embodiment of the present application also provides an electronic device 400, as Figure 17 shown, the electronic device 400 comprises a shell 410 and the above-mentioned level conversion circuit 100. Alternatively, as Figure 18 shown, the electronic device 400 comprises a shell 410 and the above-mentioned integrated circuit 300.

[0125] Optionally, the electronic device can be a mobile phone, a notebook computer, a tablet computer and the like electronic device.

[0126] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not drive the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A level shifting circuit, characterized by, The application relates to a signal conversion circuit. The signal input module is connected to a first reference voltage at a first end, grounded at a second end, used for receiving an input signal at a third end, and connected to a first intermediate node at a fourth end; the signal input module is used for generating an intermediate signal according to the input signal and transmitting the intermediate signal to the first intermediate node; The signal output module is connected to the first intermediate node at a first end, used for transmitting an output signal at a second end, connected to the first reference voltage at a third end, and grounded at a fourth end; the signal output module is used for generating the output signal according to the intermediate signal of the first intermediate node; The positive feedback module is connected to the first intermediate node at a first end, connected to the first reference voltage at a second end, and connected to the second end of the signal output module at a third end; the positive feedback module is used for adjusting the level value of the intermediate signal of the signal input module according to the output signal during the conversion process of the level value of the output signal from an initial level to a target level, thereby accelerating the conversion speed of the conversion process; The initial level is a high level or a low level, the target level is a low level when the initial level is a high level, and the target level is a high level when the initial level is a low level; The signal input module comprises a first unit and a second unit; The first end of the first unit is connected to the first end of the signal input module, the second end of the first unit is connected to the first intermediate node, and the third end of the first unit is grounded; the first end of the first unit receives the input signal, generates the intermediate signal according to the input signal when the input signal is a high level, and outputs the intermediate signal through the second end of the first unit; The first end of the second unit is connected to the first end of the signal input module, the second end of the second unit is connected to the first intermediate node, and the third end of the second unit is connected to the first reference voltage; the first end of the second unit receives the input signal, generates the intermediate signal according to the input signal when the input signal is a low level, and outputs the intermediate signal through the second end of the second unit; The second unit comprises a first inverter, a third switch tube and a fourth switch tube; The first end of the first inverter is connected to a second intermediate node, and the second end of the first inverter is connected to the first intermediate node; The first end of the third switch tube is connected to the second intermediate node, the second end of the third switch tube is connected to the first end of the signal input module, and the third end of the third switch tube is connected to a third intermediate node; The first end of the fourth switch tube is connected to the third intermediate node, the second end of the fourth switch tube is connected to the first reference voltage, and the third end of the fourth switch tube is connected to the first intermediate node; The signal output module comprises a second inverter, a first end of the second inverter is connected to the first intermediate node, and a second end of the second inverter is connected to a second end of the signal output module. The positive feedback module comprises an eleventh switch tube. A first end of the eleventh switch tube is connected to the second end of the signal output module, a second end of the eleventh switch tube is connected to a first reference voltage, and a third end of the eleventh switch tube is connected to the first intermediate node.

2. The level shifting circuit of claim 1, wherein, The level conversion circuit further comprises a reset module, a first end of the reset module is used for receiving a reset signal, a second end of the reset module is connected to the second end of the signal output module, a third end of the reset module is grounded, and the reset module is used for setting the second end of the output module to a reset level after receiving the reset signal.

3. The level shifting circuit of claim 2, wherein, The reset module comprises a first switch tube, a first end of the first switch tube is used for receiving the reset signal, a second end of the first switch tube is grounded, and a third end of the first switch tube is connected to an output signal end.

4. The level shifting circuit of claim 1, wherein, The first unit comprises a second switch tube, a first end of the second switch tube is connected to a first end of the signal input module, a second end of the second switch tube is grounded, and a third end of the second switch tube is connected to the first intermediate node.

5. The level conversion circuit according to claim 1, characterized in that: The first inverter comprises a fifth switch tube and a sixth switch tube; A first end of the fifth switch tube is connected to the first intermediate node, a second end of the fifth switch tube is connected to a second reference voltage, and a third end of the fifth switch tube is connected to the second intermediate node; A first end of the sixth switch tube is connected to the first intermediate node, a second end of the sixth switch tube is grounded, and a third end of the sixth switch tube is connected to the second intermediate node.

6. The level conversion circuit according to claim 5, characterized in that: The first reference voltage is higher than the second reference voltage.

7. The level shifting circuit of claim 1, wherein, The signal input module further comprises a third unit, a first end of the third unit is connected to the first reference voltage, a second end of the third unit is connected to the first intermediate node, a third end of the third unit is connected to a third intermediate node, a fourth end of the third unit is connected to the second end of the signal output module, and the third unit is used for maintaining the level of the third intermediate node at a high level state when an input signal of the first end of the signal input module is static.

8. The level conversion circuit according to claim 7, characterized in that: The third unit comprises a seventh switch tube and an eighth switch tube; A first end of the seventh switch tube is connected to the second end of the signal output module, a second end of the seventh switch tube is connected to the first reference voltage, and a third end of the seventh switch tube is connected to the third intermediate node; A first end of the eighth switch tube is connected to the first intermediate node, a second end of the eighth switch tube is connected to the first reference voltage, and a third end of the eighth switch tube is connected to the third intermediate node.

9. The level shifting circuit of claim 1, wherein, The second inverter comprises a ninth switch tube and a tenth switch tube; a first end of the ninth switch tube is connected to the first intermediate node, a second end of the ninth switch tube is grounded, and a third end of the ninth switch tube is connected to a second end of the signal output module; a first end of the tenth switch tube is connected to the first intermediate node, a second end of the tenth switch tube is connected to the first reference voltage, and a third end of the tenth switch tube is connected to the second end of the signal output module.

10. A method of level shifting, characterized by, The method is applied to the level conversion circuit according to any one of claims 1-9, and the method comprises: generating an intermediate signal according to a received input signal; generating an output signal according to the intermediate signal; in a conversion process in which a level value of the output signal is converted from an initial level to a target level, adjusting the level value of the intermediate signal according to the output signal, so as to accelerate the conversion speed of the conversion process.

11. An integrated circuit, characterized by The level conversion circuit comprises any one of claims 1-9.

12. An electronic device, comprising: The level conversion circuit comprises a housing and the level conversion circuit according to any one of claims 1-9 or the integrated circuit according to claim 11 arranged in the housing.

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