Three-stage dual-isolation voltage sampling method and energy storage BMS device

Abstract

The present disclosure relates to the technical field of energy storage BMS, and in particular to a three-stage dual-isolation voltage sampling method and an energy storage BMS device. The device comprises a primary voltage divider circuit, a secondary voltage divider circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip and a processing chip which are connected in sequence. The primary voltage divider circuit divides the total voltage of a battery cluster to obtain a first intermediate voltage; the secondary voltage divider circuit divides the first intermediate voltage to obtain a second intermediate voltage; the analog signal isolation circuit isolates the second intermediate voltage to obtain a first isolation voltage; the ADC sampling chip obtains a sampling voltage based on the first isolation voltage; the magnetic isolation chip isolates the sampling voltage to obtain a second isolation voltage; and the processing chip calculates the total voltage of the battery cluster based on the second isolation voltage. By using the device of the present disclosure, the sampling accuracy and safety of the total voltage of the battery cluster can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of energy storage BMS, and in particular to a three-stage dual-isolation voltage sampling method and an energy storage BMS device. Background Art

[0002] The current energy storage system consists of multiple battery clusters, and a single battery cluster consists of multiple batteries connected in series. The battery cluster is equipped with an energy storage BMS (BATTERY MANAGEMENT SYSTEM) device, which is used to detect the total voltage, current, temperature and other data of the single battery cell and the entire battery cluster, and calculate key parameters such as SOC (State Of Charge, the percentage of battery remaining power), SOH (State Of Health, battery health), charge and discharge capacity, and perform charge and discharge control, protection, alarm and other tasks of the battery cluster based on the detection and calculation results. With the development of energy storage systems, in order to further improve the conversion efficiency of energy storage systems, the number of batteries in the battery cluster is increasing, and the total voltage level of the entire battery cluster is also increasing, and has now increased from 1000V to 1500V.

[0003] The current energy storage BMS device is equipped with a battery cluster total voltage detection circuit. After the energy storage BMS device detects the total voltage, it estimates the battery cluster SOC, SOH, and charge and discharge capacity, and performs charge and discharge management, protection, and alarms based on the detection and calculation results. The battery cluster total voltage detection circuit of the current energy storage BMS device mainly adopts a primary resistor voltage divider form. The DC high voltage of the battery cluster is converted into a DC low voltage analog signal acceptable to the processing chip in the energy storage BMS device, such as MCU (Microcontroller Unit), through the voltage divider resistor, and connected to the ADC pin of the processing chip. The processing chip converts the DC voltage analog to a digital signal through the internal ADC.

[0004] However, as the total voltage of the battery cluster increases from 1000V to 1500V, the sampling range of the MCU's ADC is increased by 500V, and the sampling accuracy of the total voltage of the battery cluster is correspondingly reduced. The reduction in sampling accuracy causes large errors in the estimation of key parameters such as the battery cluster SOC, SOH, and charge and discharge capacity, resulting in inaccurate operation of the charge and discharge management strategy, fault protection and alarm malfunction or non-action, and other problems.

[0005] At the same time, in the current energy storage BMS device's detection circuit for the total voltage of the battery cluster, the total voltage of the battery cluster is divided by resistors and the divided low-voltage signal is directly connected to the pin of the processing chip of the energy storage BMS device. When the battery cluster is interfered with by other devices or an impact signal is generated, the interference signal and the impact signal will be directly applied to the pin of the processing chip, thereby causing damage to the processing chip. Summary of the invention

[0006] The present disclosure aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present disclosure is to propose a three-stage dual-isolation voltage sampling energy storage BMS device to solve the problems of low sampling accuracy of the total voltage of the battery cluster and low device safety in the prior art.

[0007] A second objective of the present disclosure is to provide a three-stage dual-isolation voltage sampling method.

[0008] In order to achieve the above-mentioned purpose, the first aspect of the present disclosure provides a three-stage dual-isolation voltage sampling energy storage BMS device, including: a primary voltage divider circuit, a secondary voltage divider circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip and a processing chip connected in sequence, wherein:

[0009] The primary voltage divider circuit is connected to the battery cluster, and the primary voltage divider circuit is used to divide the total voltage of the battery cluster to obtain a first intermediate voltage;

[0010] The secondary voltage dividing circuit is used to divide the first intermediate voltage to obtain a second intermediate voltage;

[0011] The analog signal isolation circuit is used to perform isolation processing on the second intermediate voltage to obtain a first isolation voltage;

[0012] The ADC sampling chip is used to obtain a sampling voltage based on the first isolation voltage;

[0013] The magnetic isolation chip is used to isolate the sampled voltage to obtain a second isolation voltage;

[0014] The processing chip is used to calculate the total voltage of the battery cluster based on the second isolation voltage.

[0015] In one embodiment of the present disclosure, the primary voltage-dividing circuit is connected in parallel with the battery cluster, and the primary voltage-dividing circuit is formed by a first voltage-dividing resistor, a second voltage-dividing resistor and a third voltage-dividing resistor connected in series.

[0016] In one embodiment of the present disclosure, the secondary voltage-dividing circuit includes a fourth voltage-dividing resistor, a fifth voltage-dividing resistor, a sixth voltage-dividing resistor, a seventh voltage-dividing resistor, an eighth voltage-dividing resistor and a ninth voltage-dividing resistor connected in series in sequence, the fourth voltage-dividing resistor and the fifth voltage-dividing resistor are connected in parallel with the first voltage-dividing resistor, the sixth voltage-dividing resistor and the seventh voltage-dividing resistor are connected in parallel with the second voltage-dividing resistor, and the eighth voltage-dividing resistor and the ninth voltage-dividing resistor are connected in parallel with the third voltage-dividing resistor.

[0017] In one embodiment of the present disclosure, the analog signal isolation circuit includes a first analog isolator, a second analog isolator, and a third analog isolator, the two ends of the fourth voltage-dividing resistor are connected to the first analog isolator, the two ends of the sixth voltage-dividing resistor are connected to the second analog isolator, and the two ends of the eighth voltage-dividing resistor are connected to the third analog isolator.

[0018] In one embodiment of the present disclosure, the processing chip is used to: calculate the second intermediate voltage based on the second isolation voltage, calculate the first intermediate voltage based on the second intermediate voltage, and calculate the total voltage of the battery cluster based on the first intermediate voltage.

[0019] In one embodiment of the present disclosure, the models of the first analog isolator, the second analog isolator, and the third analog isolator are all TE6664N.

[0020] In one embodiment of the present disclosure, the model of the ADC sampling chip is ADCS8162, and the model of the magnetic isolation chip is BLD7741.

[0021] In one embodiment of the present disclosure, the processing chip uses an MCU chip of model GD32F407.

[0022] In order to achieve the above object, the second aspect of the present disclosure provides a three-stage dual-isolation voltage sampling method, which is implemented by using the three-stage dual-isolation voltage sampling energy storage BMS device in any of the above embodiments, including:

[0023] Dividing the total voltage of the battery cluster to obtain a first intermediate voltage;

[0024] Dividing the first intermediate voltage to obtain a second intermediate voltage;

[0025] Inputting the second intermediate voltage into an analog signal isolation circuit for isolation to obtain a first isolation voltage;

[0026] Performing ADC sampling on the first isolation voltage to obtain a sampled voltage;

[0027] Inputting the sampled voltage into a magnetic isolation chip for isolation to obtain a second isolation voltage;

[0028] The total voltage of the battery cluster is calculated based on the second isolation voltage.

[0029] In one embodiment of the present disclosure, calculating the total voltage of the battery cluster based on the second isolation voltage includes: calculating the second intermediate voltage based on the second isolation voltage, calculating the first intermediate voltage based on the second intermediate voltage, and calculating the total voltage of the battery cluster based on the first intermediate voltage.

[0030] In one or more embodiments of the present disclosure, a primary voltage divider circuit, a secondary voltage divider circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip and a processing chip are connected in sequence. The primary voltage divider circuit divides the total voltage of the battery cluster to obtain a first intermediate voltage; the secondary voltage divider circuit divides the first intermediate voltage to obtain a second intermediate voltage; the analog signal isolation circuit isolates the second intermediate voltage to obtain a first isolation voltage; the ADC sampling chip obtains a sampling voltage based on the first isolation voltage; the magnetic isolation chip isolates the sampling voltage to obtain a second isolation voltage; and the processing chip calculates the total voltage of the battery cluster based on the second isolation voltage. In this case, the primary voltage divider circuit and the secondary voltage divider circuit are used to perform segmented sampling of the total voltage of the battery cluster to improve the sampling accuracy of the total voltage of the battery cluster. In addition, the analog signal isolation circuit and the magnetic isolation chip perform two-stage isolation processing to improve the safety of the energy storage BMS device.

[0031] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0033] Figure 1 A circuit diagram of the prior art;

[0034] Figure 2 A block diagram of a three-stage dual-isolation voltage sampling energy storage BMS device provided in an embodiment of the present disclosure;

[0035] Figure 3 A circuit diagram of a three-stage dual-isolation voltage sampling energy storage BMS device provided by an embodiment of the present disclosure;

[0036] Figure 4 A schematic flow chart of a three-stage dual-isolation voltage sampling method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the embodiments of the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present disclosure as detailed in the appended claims.

[0038] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. It should also be understood that the term "and / or" used in the present disclosure refers to and includes any or all possible combinations of one or more associated listed items.

[0040] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0041] Figure 1 The current energy storage system consists of multiple battery clusters, and a single battery cluster consists of multiple batteries connected in series (see Figure 1 ), the battery cluster is also equipped with a storage BMS device, which is used to detect the total voltage, current, temperature and other data of the single cell and the entire battery cluster, and calculate key parameters such as SOC, SOH, charge and discharge capacity, and perform charge and discharge control, protection, and alarm of the battery cluster based on the detection and calculation results. Figure 1As shown, the existing energy storage BMS device includes a primary resistor voltage-dividing structure composed of a voltage-dividing resistor Ra and a voltage-dividing resistor Rb. The voltage-dividing resistor Ra and the voltage-dividing resistor Rb are used to convert the DC high voltage of the battery cluster into a DC low voltage analog signal acceptable to the processing chip in the energy storage BMS device and connect it to the ADC pin of the processing chip. The processing chip converts the DC voltage analog into a digital signal through the internal ADC. However, with the development of energy storage systems, in order to further improve the conversion efficiency of energy storage systems, the number of batteries in the battery cluster is increasing, and the total voltage level of the entire battery cluster is also increasing. For example, most of them have been increased from 1000V to 1500V. As the total voltage of the battery cluster is increased from 1000V to 1500V, the sampling range of 500V is increased for the ADC of the processing chip, and the sampling accuracy of the total voltage of the battery cluster is correspondingly reduced, which causes a large error in the estimation of key parameters such as SOC, SOH, and charge and discharge capacity of the battery cluster, so as to cause problems such as inaccurate operation of the charge and discharge management strategy, fault protection and alarm malfunction or inaction. In addition, since the existing technology directly connects the divided low voltage signal to the pin of the processing chip of the energy storage BMS device, when the battery cluster is interfered by other devices or an impact signal is generated, the interference signal and the impact signal will be directly applied to the pin of the processing chip, causing damage to the processing chip, thereby making the safety of the energy storage BMS device insufficient. Therefore, it is very important to improve the sampling accuracy of the total voltage of the battery cluster and the safety of the device.

[0042] In a first embodiment, Figure 2 A block diagram of a three-stage dual-isolation voltage sampling energy storage BMS device provided in an embodiment of the present disclosure; Figure 3 A circuit diagram of a three-stage dual-isolation voltage sampling energy storage BMS device provided in an embodiment of the present disclosure. The three-stage dual-isolation voltage sampling energy storage BMS device involved in the present disclosure can be referred to as an energy storage BMS device. The energy storage BMS (BATTERY MANAGEMENT SYSTEM) device is an energy storage battery management device. The three-stage dual-isolation voltage sampling energy storage BMS device solves the problems of low sampling accuracy of the total voltage of the battery cluster and low device safety in the prior art.

[0043] like Figure 2 As shown, the three-stage dual-isolation voltage sampling energy storage BMS device 10 includes a primary voltage divider circuit 11, a secondary voltage divider circuit 12, an analog signal isolation circuit 13, an ADC sampling chip 14, a magnetic isolation chip 15 and a processing chip 16. The primary voltage divider circuit 11, the secondary voltage divider circuit 12, the analog signal isolation circuit 13, the ADC sampling chip 14, the magnetic isolation chip 15 and the processing chip 16 are connected in sequence.

[0044] In this embodiment, the primary voltage divider circuit 11 is connected to the battery cluster. The primary voltage divider circuit 11 is used to divide the total voltage of the battery cluster to obtain a first intermediate voltage. Specifically, the battery cluster is composed of a plurality of batteries connected in series, wherein the batteries at both ends are the positive and negative electrodes of the battery cluster, respectively, and the voltage formed by the positive and negative electrodes of the battery cluster is the total voltage of the battery cluster. The primary voltage divider circuit 11 is connected in parallel with the battery cluster and divides the total voltage of the battery cluster. The total voltage of the battery cluster can range from 0 to 1500V. In some embodiments, the battery cluster can be included in a three-stage dual-isolation voltage sampling energy storage BMS device 10.

[0045] In this embodiment, the first-level voltage-dividing circuit 11 is composed of a plurality of voltage-dividing resistors. At this time, the first-level voltage-dividing circuit 11 divides the total voltage of the battery cluster into a plurality of segments, and each voltage-dividing resistor corresponds to a segment, that is, each voltage-dividing resistor corresponds to a first intermediate voltage. Therefore, the number of the first intermediate voltages is consistent with the number of voltage-dividing resistors in the first-level voltage-dividing circuit 11.

[0046] In some embodiments, the primary voltage divider circuit 11 includes three voltage divider resistors. In this case, the primary voltage divider circuit 11 divides the total voltage of the battery cluster into three sections, and the number of the first intermediate voltages is 3. That is, the first intermediate voltage includes the first divided voltage, the second divided voltage, and the third divided voltage. Figure 3 As shown, the primary voltage divider circuit 11 is formed by a first voltage divider resistor R1, a second voltage divider resistor R2 and a third voltage divider resistor R3 connected in series. Specifically, the negative end of the first voltage divider resistor R1 is connected to the negative electrode of the battery cluster, the positive end of the first voltage divider resistor R1 is connected to the negative end of the second voltage divider resistor R2, the positive end of the second voltage divider resistor R2 is connected to the negative end of the third voltage divider resistor R3, and the positive end of the third voltage divider resistor R3 is connected to the positive electrode of the battery cluster. The first voltage divider is the voltage across the first voltage divider resistor R1, the second voltage divider is the voltage across the second voltage divider resistor R2, and the third voltage divider is the voltage across the third voltage divider resistor R3. In this case, each segment of the total voltage of the battery cluster that is subjected to three-segment voltage division is sampled separately, and the range of the sampling channel is reduced to improve the sampling accuracy.

[0047] In this embodiment, the resistance values ​​of the voltage-dividing resistors may be the same or different.

[0048] In some embodiments, the resistance values ​​of the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 are equal. At this time, the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 evenly divide the total voltage of the battery cluster, that is, the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 are equal. The resistance values ​​of the first voltage-dividing resistor R1, the second voltage-dividing resistor R2 and the third voltage-dividing resistor R3 are, for example, 10MΩ.

[0049] In this embodiment, the two-stage voltage divider circuit 12 is used to divide the first intermediate voltage to obtain the second intermediate voltage.

[0050] In this embodiment, the secondary voltage divider circuit 12 may be composed of a plurality of voltage divider resistors. The secondary voltage divider circuit 12 performs secondary voltage division on the voltage divided by the primary voltage divider circuit 11 through a plurality of voltage divider resistors. Thus, by performing secondary resistor voltage division on each voltage segment for sampling, the voltage signal is reduced to meet the sampling range of the ADC sampling chip.

[0051] In some embodiments, the secondary voltage divider circuit 12 includes six voltage divider resistors. Figure 3 As shown, the secondary voltage-dividing circuit 12 includes a fourth voltage-dividing resistor R4, a fifth voltage-dividing resistor R5, a sixth voltage-dividing resistor R6, a seventh voltage-dividing resistor R7, an eighth voltage-dividing resistor R8 and a ninth voltage-dividing resistor R9 which are sequentially connected in series. The fourth voltage-dividing resistor R4 and the fifth voltage-dividing resistor R5 are connected in parallel with the first voltage-dividing resistor R1, the sixth voltage-dividing resistor R6 and the seventh voltage-dividing resistor R7 are connected in parallel with the second voltage-dividing resistor R2, and the eighth voltage-dividing resistor R8 and the ninth voltage-dividing resistor R9 are connected in parallel with the third voltage-dividing resistor R3.

[0052] Specifically, the secondary voltage-dividing circuit 12 performs secondary voltage-dividing on the voltage across the first voltage-dividing resistor R1 through the fourth voltage-dividing resistor R4 and the fifth voltage-dividing resistor R5, the negative end of the fourth voltage-dividing resistor R4 is connected to the negative end of the first voltage-dividing resistor R1, the positive end of the fourth voltage-dividing resistor R4 is connected to the negative end of the fifth voltage-dividing resistor R5, and the positive end of the fifth voltage-dividing resistor R5 is connected to the positive end of the first voltage-dividing resistor R1; the voltage across the second voltage-dividing resistor R2 is performed secondary voltage-dividing through the sixth voltage-dividing resistor R6 and the seventh voltage-dividing resistor R7, the negative end of the sixth voltage-dividing resistor R6 is connected to the negative end of the first voltage-dividing resistor R1, the positive end of the fourth voltage-dividing resistor R4 is connected to the negative end of the fifth voltage-dividing resistor R5, and the positive end of the fifth voltage-dividing resistor R5 is connected to the positive end of the first voltage-dividing resistor R1. The positive end of the sixth voltage-dividing resistor R6 is connected to the negative end of the second voltage-dividing resistor R2, the positive end of the sixth voltage-dividing resistor R6 is connected to the negative end of the seventh voltage-dividing resistor R7, and the positive end of the seventh voltage-dividing resistor R7 is connected to the positive end of the second voltage-dividing resistor R2; the voltage across the third voltage-dividing resistor R3 is divided into two levels through the eighth voltage-dividing resistor R8 and the ninth voltage-dividing resistor R9, the negative end of the eighth voltage-dividing resistor R8 is connected to the negative end of the third voltage-dividing resistor R3, the positive end of the eighth voltage-dividing resistor R8 is connected to the negative end of the ninth voltage-dividing resistor R9, and the positive end of the ninth voltage-dividing resistor R9 is connected to the positive end of the third voltage-dividing resistor R3.

[0053] In this embodiment, each voltage-dividing resistor in the secondary voltage-dividing circuit 12 performs secondary voltage division on the voltage across the voltage-dividing resistor in the corresponding primary voltage-dividing circuit 11, and three voltage-dividing resistors in the secondary voltage-dividing circuit 12 are selected, and the intermediate voltage after the three voltage-dividing resistors perform secondary voltage division is used as the second intermediate voltage. At this time, the number of the second intermediate voltages is three, and the second intermediate voltage includes the fourth voltage division, the fifth voltage division, and the sixth voltage division. If the fourth voltage-dividing resistor R4, the sixth voltage-dividing resistor R6, and the eighth voltage-dividing resistor R8 are selected, the fourth voltage division is the voltage across the fourth voltage-dividing resistor R4, the fifth voltage division is the voltage across the sixth voltage-dividing resistor R6, and the sixth voltage division is the voltage across the eighth voltage-dividing resistor R8.

[0054] In this embodiment, the resistance values ​​of the voltage-dividing resistors may be the same or different.

[0055] In some embodiments, the fourth voltage-dividing resistor R4, the sixth voltage-dividing resistor R6 and the eighth voltage-dividing resistor R8 have the same resistance value, and the fifth voltage-dividing resistor R5, the seventh voltage-dividing resistor R7 and the ninth voltage-dividing resistor R9 have the same resistance value. The fourth voltage-dividing resistor R4, the sixth voltage-dividing resistor R6 and the eighth voltage-dividing resistor R8 have a resistance value of, for example, 100KΩ, and the fifth voltage-dividing resistor R5, the seventh voltage-dividing resistor R7 and the ninth voltage-dividing resistor R9 have a resistance value of, for example, 10MΩ. At this time, the fourth voltage-dividing resistor, the fifth voltage-dividing resistor and the sixth voltage-dividing resistor can be controlled at 0 to 5V, respectively.

[0056] In this embodiment, the analog signal isolation circuit 13 is used to perform isolation processing on the second intermediate voltage to obtain a first isolation voltage.

[0057] In this embodiment, the analog signal isolation circuit 13 may be composed of analog isolators, and the number of the analog isolators is consistent with the number of the second intermediate voltages.

[0058] In some embodiments, the number of the second intermediate voltages is three, the number of the analog isolators is three, and thus the number of the first isolation voltages is three.

[0059] In some embodiments, Figure 3 As shown, the analog signal isolation circuit 13 includes a first analog isolator U1, a second analog isolator U2 and a third analog isolator U3. The first analog isolator U1 is connected to both ends of the fourth voltage-dividing resistor R4, the second analog isolator U2 is connected to both ends of the sixth voltage-dividing resistor R6, and the third analog isolator U3 is connected to both ends of the eighth voltage-dividing resistor R8. In this case, an analog isolator is used between the analog signal of the battery cluster voltage (i.e., the second intermediate voltage) and the analog signal input end of the ADC sampling chip to effectively isolate interference and impact signals, and at the same time, each of the three-segment voltage-divided signals can match the input range of the ADC sampling chip.

[0060] In some embodiments, Figure 3 As shown, the first analog isolator U1, the second analog isolator U2 and the third analog isolator U3 are all of the model TE6664N. The analog isolator of model TE6664N functions to electrically isolate a 0-5V DC signal, the input voltage is 0-5V, the isolated output is 0-5V (i.e., the output voltage), and the input and the isolated output are in a linear correspondence.

[0061] In some embodiments, Figure 3As shown, pin 8 of the first analog isolator U1 is the pin for the negative input voltage Vi1-, and pin 9 of the first analog isolator U1 is the pin for the positive input voltage Vi1+; pin 8 of the second analog isolator U2 is the pin for the negative input voltage Vi2-, and pin 9 of the second analog isolator U2 is the pin for the positive input voltage Vi2+, pin 8 of the third analog isolator U3 is the pin for the negative input voltage Vi3-, and pin 9 of the third analog isolator U3 is the pin for the positive input voltage Vi3+. The positive end of the fourth voltage-dividing resistor R4 is connected to pin 9 of the first analog isolator U1, and the negative end of the fourth voltage-dividing resistor R4 is connected to pin 8 of the first analog isolator U1; the positive end of the sixth voltage-dividing resistor R6 is connected to pin 9 of the second analog isolator U2, and the negative end of the sixth voltage-dividing resistor R6 is connected to pin 8 of the second analog isolator U2; the positive end of the eighth voltage-dividing resistor is connected to pin 9 of the third analog isolator U3, and the negative end of the eighth voltage-dividing resistor is connected to pin 8 of the third analog isolator U3.

[0062] In some embodiments, Figure 3 As shown, pin 2 of the first analog isolator U1 is the pin for the negative output voltage Vo1-, and pin 1 of the first analog isolator U1 is the pin for the positive output voltage Vo1+; pin 2 of the second analog isolator U2 is the pin for the negative output voltage Vo2-, and pin 1 of the second analog isolator U2 is the pin for the positive output voltage Vo2+, pin 2 of the third analog isolator U3 is the pin for the negative output voltage Vo3-, and pin 1 of the third analog isolator U3 is the pin for the positive output voltage Vo3+.

[0063] The first analog isolator U1 , the second analog isolator U2 , and the third analog isolator U3 receive the fourth divided voltage, the fifth divided voltage, and the sixth divided voltage respectively, and output corresponding first isolation voltages after performing primary isolation.

[0064] In this embodiment, the ADC sampling chip 14 is connected to the analog signal isolation circuit 13, and the ADC sampling chip 14 is used to obtain a sampling voltage based on the first isolation voltage. If the number of the first isolation voltages is 3, the number of the sampling voltages is also 3.

[0065] In some embodiments, Figure 3 As shown, the ADC sampling chip 14 can be an ADC sampling chip U4 of model ADCS8162. The function of the ADC sampling chip U4 of model ADCS8162 is to convert the input 0-5V analog signal into a digital signal, and send the sampling signal (ie, digital signal) to the processing chip through SPI (Serial Peripheral Interface) communication.

[0066] In some embodiments, Figure 3As shown, pin 49 of the ADC sampling chip U4 is the first input voltage V1 pin, pin 50 of the ADC sampling chip U4 is the first ground pin, pin 51 of the ADC sampling chip U4 is the second input voltage V2 pin, pin 52 of the ADC sampling chip U4 is the second ground pin, pin 53 of the ADC sampling chip U4 is the third input voltage V3 pin, and pin 54 of the ADC sampling chip U4 is the third ground pin. Pin 1 of the first analog isolator U1 is connected to pin 49 of the ADC sampling chip U4, and pin 2 of the first analog isolator U1 is connected to pin 50 of the ADC sampling chip U4; pin 1 of the second analog isolator U2 is connected to pin 51 of the ADC sampling chip U4, and pin 2 of the second analog isolator U2 is connected to pin 52 of the ADC sampling chip U4; pin 1 of the third analog isolator U3 is connected to pin 53 of the ADC sampling chip U4, and pin 2 of the third analog isolator U3 is connected to pin 54 of the ADC sampling chip U4. The first input voltage V1 pin receives the fourth divided voltage after the first level of isolation, the second input voltage V2 pin receives the fifth divided voltage after the first level of isolation, and the third input voltage V3 pin receives the sixth divided voltage after the first level of isolation.

[0067] In some embodiments, Figure 3 As shown, pin 9 of the ADC sampling chip U4 is the first analog-to-digital conversion start pin CONVSTA, and pin 10 of the ADC sampling chip U4 is the second analog-to-digital conversion start pin CONVSTB. When pin 9 of the ADC sampling chip U4 is connected to pin 10 of the ADC sampling chip U4, all channels are sampled synchronously. Pin 12 of the ADC sampling chip U4 is the clock signal SCLK pin (such as the SPI communication clock signal pin), and pin 13 of the ADC sampling chip U4 is the chip select signal Pin, pin 24 of the ADC sampling chip U4 is the first output digital signal DOUTA pin, and pin 25 of the ADC sampling chip U4 is the second output digital signal DOUTB pin.

[0068] In this embodiment, the magnetic isolation chip 15 is used to isolate the sampled voltage to obtain a second isolated voltage. If the number of sampled voltages is also three, the number of second isolated voltages is also three.

[0069] In some embodiments, Figure 3As shown, the magnetic isolation chip 15 can be a magnetic isolation chip U5 of model BLD7741. The function of the magnetic isolation chip U5 of model BLD7741 is to electrically isolate the SPI communication signal and transmit data by magnetic coupling. In this case, the communication between the ADC sampling chip 14 and the processing chip 16 adopts the magnetic isolation chip 15 to further isolate the analog signal and the digital signal. When the ADC sampling chip 14 is damaged, it does not affect the normal operation of the processing chip 16, so as to ensure that other functions of the processing chip 16 are available.

[0070] In some embodiments, Figure 3 As shown, pin 11 of the magnetic isolation chip U5 is the primary input signal VID pin, pin 12 of the magnetic isolation chip U5 is the primary third output signal VOC pin, pin 13 of the magnetic isolation chip U5 is the primary second output signal VOB pin, pin 14 of the magnetic isolation chip U5 is the primary first output signal VOA pin, pin 6 of the magnetic isolation chip U5 is the secondary output signal VOD pin, pin 5 of the magnetic isolation chip U5 is the secondary third input signal VIC pin, pin 3 of the magnetic isolation chip U5 is the secondary second input signal VIB pin, and pin 2 of the magnetic isolation chip U5 is the secondary first input signal VIA pin.

[0071] In this embodiment, the processing chip 16 is used to calculate the total voltage of the battery cluster based on the second isolation voltage.

[0072] In some embodiments, Figure 3 As shown, the processing chip 16 can be an MCU chip U6 of model GD32F407. Pin 41 of the MCU chip U6 is a clock signal SPIO-CLK pin, pin 42 of the MCU chip U6 is a signal input SPIO-MISO pin (i.e., a data receiving pin for SPI0 communication), pin 43 of the MCU chip U6 is an analog-to-digital conversion control signal AD-CONVST pin, and pin 40 of the MCU chip U6 is a chip select signal CS pin.

[0073] In this embodiment, the processing chip is used to: calculate the second intermediate voltage based on the second isolation voltage, calculate the first intermediate voltage based on the second intermediate voltage, and calculate the total voltage of the battery cluster based on the first intermediate voltage.

[0074] Specifically, if the number of second isolation voltages is 3, for example, the second isolation voltage includes the first magnetic isolation voltage Va, the second magnetic isolation voltage Vb and the third magnetic isolation voltage Vc, the processing chip obtains the fourth divided voltage after the first-level isolation, the fifth divided voltage after the first-level isolation and the sixth divided voltage after the first-level isolation based on the first magnetic isolation voltage Va, the second magnetic isolation voltage Vb and the third magnetic isolation voltage Vc. Since the input and the isolation output of the analog isolator are in a linear correspondence, the fourth divided voltage, the fifth divided voltage and the sixth divided voltage are obtained, and the first divided voltage, the second divided voltage and the third divided voltage are further obtained according to the resistance voltage division principle. The total voltage of the battery cluster can be obtained by summing the first divided voltage, the second divided voltage and the third divided voltage.

[0075] In some embodiments, Figure 3 As shown, the connection method of ADC sampling chip U4, magnetic isolation chip U5, and MCU chip U6 is as follows: pins 24 and 25 of ADC sampling chip U4 are connected to pin 11 of magnetic isolation chip U5, and pin 13 of ADC sampling chip U4 is connected to pin 12 of magnetic isolation chip U5; pin 12 of ADC sampling chip U4 is connected to pin 13 of magnetic isolation chip U5; pins 9 and 10 of ADC sampling chip U4 are connected to pin 14 of magnetic isolation chip U4. Pin 6 of magnetic isolation chip U5 is connected to pin 42 of MCU chip U6; pin 5 of magnetic isolation chip U5 is connected to pin 40 of MCU chip U6; pin 4 of magnetic isolation chip U5 is connected to pin 41 of MCU chip U6; and pin 3 of magnetic isolation chip U5 is connected to pin 43 of MCU chip U6.

[0076] Among them, the process of MCU chip U6 obtaining the data output by ADC sampling chip U4 includes: pin 40 of MCU chip U6 is connected to pin 5 of magnetic isolation chip U5, and after signal isolation, it is output to pin 13 of ADC sampling chip U4 through pin 12 of magnetic isolation chip U5. This signal is the chip select signal of ADC sampling chip U4, which is controlled by pin 40 of MCU chip U6; pin 41 of MCU chip U6 is connected to pin 4 of magnetic isolation chip U5, and after signal isolation, it is output to pin 12 of ADC sampling chip U4 through pin 13 of magnetic isolation chip U5. This signal is the SPI communication clock signal of ADC sampling chip U4, and the clock signal is sent by pin 41 of MCU chip U6 to synchronize the SPI clock; pin 43 of MCU chip U6 is connected to pin 3 of magnetic isolation chip U5, and after signal isolation, it is output to ADC sampling through pin 14 of magnetic isolation chip U5. Pins 9 and 10 of chip U4 are control pins for converting analog signals of ADC sampling chip U4 into digital signals, and are controlled by pin 43 of MCU chip U6. When the voltage needs to be read, pin 41 of MCU chip U6 sends a clock signal to synchronize the SPI communication clock of ADC sampling chip U4 with the SPI communication clock of MCU chip U6. MCU chip U6 controls the level of its pin 40 to be low, and applies it to pin 13 of ADC sampling chip U4 through magnetic isolation chip U5, so that ADC sampling chip U4 is in an effective working state. MCU chip U6 controls its pin 43 to be high, and applies it to pins 9 and 10 of ADC sampling chip U4 through magnetic isolation chip U5, so as to convert the analog signal into a digital signal and finally send it out through pins 24 and 25 of ADC sampling chip U4, and then send it to pin 42 of MCU chip after isolation by magnetic isolation chip U5.

[0077] Combination Figure 3 The total voltage sampling method of the battery cluster of the energy storage BMS device shown is as follows:

[0078] The total voltage of the battery cluster is divided by a primary voltage divider circuit, wherein the first voltage divider resistor R1, the second voltage divider resistor R2, and the third voltage divider resistor R3 have the same resistance values ​​and evenly divide the total voltage of the battery cluster; the fourth voltage divider resistor R4 and the fifth voltage divider resistor R5 perform secondary voltage division on the voltage across the first voltage divider resistor R1, the sixth voltage divider resistor R6 and the seventh voltage divider resistor R7 perform secondary voltage division on the voltage across the second voltage divider resistor R2, and the eighth voltage divider resistor R8 and the ninth voltage divider resistor R9 perform secondary voltage division on the voltage across the third voltage divider resistor R3;

[0079] After the secondary voltage division, the negative end of the fourth voltage-dividing resistor R4 is connected to pin 8 of the first analog isolator U1, and the positive end of the fourth voltage-dividing resistor R4 is connected to pin 9 of the first analog isolator U1. After the voltage across the fourth voltage-dividing resistor R4 is isolated by the first analog isolator U1, it is output from pins 1 and 2 of the first analog isolator U1 to pins 49 and 50 of the ADC sampling chip U4; the negative end of the sixth voltage-dividing resistor R6 is connected to pin 8 of the second analog isolator U2, the positive end of the sixth voltage-dividing resistor R6 is connected to pin 9 of the second analog isolator U2, and the sixth voltage-dividing resistor R6 is connected to pin 10 of the second analog isolator U2. The voltage across the resistor R6 is isolated by the second analog isolator U2 and then outputted from the pins 1 and 2 of the second analog isolator U2 to the pins 51 and 52 of the ADC sampling chip U4; the negative end of the eighth voltage-dividing resistor R8 is connected to the pin 8 of the third analog isolator U3, the positive end of the eighth voltage-dividing resistor R8 is connected to the pin 9 of the third analog isolator U3, and the voltage across the eighth voltage-dividing resistor R8 is isolated by the third analog isolator U3 and then outputted from the pins 1 and 2 of the third analog isolator U3 to the pins 53 and 54 of the ADC sampling chip U4;

[0080] The analog signal input range of pins 49 and 50, pins 51 and 52, and pins 53 and 54 of the ADC sampling chip U4 is 0-5V. The fourth divided voltage, the fifth divided voltage, and the sixth divided voltage are isolated by the corresponding analog isolators and input to the ADC sampling chip U4 for conversion, and converted into digital signals. The signal outputs of pins 24 and 25 of the ADC sampling chip U4 are sent to pin 11 of the magnetic isolation chip U5. After signal isolation (such as SPI communication signal isolation), the signals are output to pin 42 of the MCU chip U6 through pin 6 of the magnetic isolation chip U5.

[0081] After receiving the data sent by the ADC sampling chip U4, the MCU chip U6 processes it to determine the fourth divided voltage, the fifth divided voltage, and the sixth divided voltage. Since the ADC sampling chip U4 model ADCS8162 is a 16-bit ADC sampling chip, the analog signal input range of its analog signal input channel pins 49 and 50, pins 51 and 52, and pins 53 and 54 is 0 to 5V, and the corresponding digital signal output is 0 to 65535. The MCU chip U6 further converts the digital signal to determine the fourth divided voltage after the first level of isolation, the fifth divided voltage after the first level of isolation, and the sixth divided voltage after the first level of isolation; the calculation formula is as follows:

[0082] The fourth voltage division after primary isolation = current channel digital signal value ÷ 65535 × 5V

[0083] The fifth voltage division after primary isolation = current channel digital signal value ÷ 65535 × 5V

[0084] The sixth voltage division after primary isolation = current channel digital signal value ÷ 65535 × 5V

[0085] The voltage values ​​of the fourth divided voltage, the fifth divided voltage and the sixth divided voltage are obtained based on the voltage values ​​of the fourth divided voltage after the first level isolation, the fifth divided voltage after the first level isolation and the sixth divided voltage after the first level isolation, wherein the input and output voltages of the analog isolator model TE6664N are consistent, so the fourth divided voltage is equal to the fourth divided voltage after the first level isolation, the fifth divided voltage is equal to the fifth divided voltage after the first level isolation, and the sixth divided voltage is equal to the sixth divided voltage after the first level isolation, thereby determining the voltage across the fourth divided voltage resistor R4, the voltage across the sixth divided voltage resistor R6 and the voltage across the eighth divided voltage resistor R8;

[0086] According to the resistor voltage division principle, the voltage across the first voltage-dividing resistor R1, the voltage across the second voltage-dividing resistor R2, and the voltage across the third voltage-dividing resistor R3 are obtained based on the voltage across the fourth voltage-dividing resistor R4, the voltage across the sixth voltage-dividing resistor R6, and the voltage across the eighth voltage-dividing resistor R8. The calculation formula is as follows:

[0087] The voltage across the first voltage-dividing resistor R1 = the voltage across the fourth voltage-dividing resistor R4 ÷ R4 × (R4 + R5)

[0088] The voltage across the second voltage-dividing resistor R2 = the voltage across the sixth voltage-dividing resistor R6 ÷ R6 × (R6 + R7)

[0089] The voltage across the third voltage-dividing resistor R3 = the voltage across the eighth voltage-dividing resistor R8 ÷ R8 × (R8 + R9)

[0090] The voltage across the first voltage-dividing resistor R1 , the voltage across the second voltage-dividing resistor R2 , and the voltage across the third voltage-dividing resistor R3 are summed to obtain the total voltage of the battery cluster.

[0091] In the three-stage dual-isolation voltage sampling energy storage BMS device disclosed in the present invention, a primary voltage divider circuit, a secondary voltage divider circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip and a processing chip are connected in sequence. The primary voltage divider circuit divides the total voltage of the battery cluster to obtain a first intermediate voltage; the secondary voltage divider circuit divides the first intermediate voltage to obtain a second intermediate voltage; the analog signal isolation circuit isolates the second intermediate voltage to obtain a first isolation voltage; the ADC sampling chip obtains a sampling voltage based on the first isolation voltage; the magnetic isolation chip isolates the sampling voltage to obtain a second isolation voltage; the processing chip calculates the total voltage of the battery cluster based on the second isolation voltage. In this case, the primary voltage divider circuit and the secondary voltage divider circuit are used to perform segmented sampling of the total voltage of the battery cluster, which improves the sampling accuracy of the total voltage of the battery cluster. In addition, the analog signal isolation circuit and the magnetic isolation chip perform two-stage isolation processing, which improves the safety of the energy storage BMS device and reduces the failure rate. In addition, the total voltage range of the battery cluster disclosed in the present invention is 0-1500V, and the primary voltage divider circuit includes three voltage divider resistors with equal resistance values. Therefore, the energy storage BMS device disclosed in the present invention is a high-precision three-stage dual-isolation voltage sampling energy storage BMS device that can support 0-1500V DC. It adopts a three-stage voltage divider structure to divide the total voltage of the 0-1500V battery cluster into three sections on average, and then samples the three sections of voltage separately, reducing the range of a single sampling channel, and sampling each section of voltage by performing a secondary resistor voltage divider to reduce the voltage signal to meet the sampling range of the ADC sampling chip. It has the characteristics of a simple system and high sampling accuracy. Compared with traditional sampling devices, the accuracy can reach within ±0.1%. At the same time, the present invention adopts a two-stage isolation technology to perform a primary isolation on the analog signal, and performs a digital signal isolation on the SPI communication signal after passing through the ADC sampling chip, which greatly improves the anti-interference ability and safety.

[0092] The following is an embodiment of the method disclosed herein. For details not disclosed in the embodiment of the method disclosed herein, please refer to the embodiment of the device disclosed herein. The method embodiment of the present disclosure proposes a three-stage dual-isolation voltage sampling method. The three-stage dual-isolation voltage sampling method uses the three-stage dual-isolation voltage sampling energy storage BMS device of the above-mentioned device embodiment to realize voltage sampling.

[0093] Figure 4 A schematic flow chart of a three-stage dual-isolation voltage sampling method provided by an embodiment of the present disclosure. The three-stage dual-isolation voltage sampling method includes:

[0094] S101, dividing the total voltage of the battery cluster to obtain a first intermediate voltage.

[0095] In step S101, the first intermediate voltage is obtained by dividing the total voltage of the battery cluster through a primary voltage dividing circuit. The range (ie, the measurement range) of the total voltage of the battery cluster is 0 to 1500 V. For details, please refer to the relevant description in the above device embodiment, which will not be repeated here.

[0096] S102, dividing the first intermediate voltage to obtain a second intermediate voltage.

[0097] In step S102, the first intermediate voltage is divided by a two-stage voltage divider circuit to obtain a second intermediate voltage. For details, please refer to the relevant description in the above device embodiment, which will not be repeated here.

[0098] S103, inputting the second intermediate voltage into an analog signal isolation circuit for isolation to obtain a first isolation voltage.

[0099] In step S103, the analog signal isolation circuit may be composed of a plurality of analog isolators, and the details are referred to the relevant description in the above device embodiment, which will not be described here.

[0100] S104, performing ADC sampling on the first isolation voltage to obtain a sampled voltage.

[0101] In step S104, the first isolation voltage is sampled by an ADC sampling chip to obtain a sampled voltage. For details, please refer to the relevant description in the above device embodiment, which will not be repeated here.

[0102] S105, inputting the sampled voltage into the magnetic isolation chip for isolation to obtain a second isolation voltage.

[0103] S106, calculating and obtaining the total voltage of the battery cluster based on the second isolation voltage.

[0104] In step S106, the total voltage of the battery cluster is calculated by the processing chip. The total voltage of the battery cluster is calculated based on the second isolation voltage, including: calculating the second intermediate voltage based on the second isolation voltage, calculating the first intermediate voltage based on the second intermediate voltage, and calculating the total voltage of the battery cluster based on the first intermediate voltage. For details, please refer to the relevant description in the above device embodiment, which will not be repeated here.

[0105] It should be noted that the aforementioned explanation of the three-stage dual-isolation voltage sampling energy storage BMS device embodiment is also applicable to the three-stage dual-isolation voltage sampling method of this embodiment, and will not be repeated here.

[0106] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0107] In the three-stage dual-isolation voltage sampling method disclosed in the present invention, the total voltage of the battery cluster is divided to obtain the first intermediate voltage; the first intermediate voltage is divided to obtain the second intermediate voltage; the second intermediate voltage is isolated to obtain the first isolation voltage; the sampling voltage is obtained based on the first isolation voltage; the sampling voltage is isolated to obtain the second isolation voltage; the total voltage of the battery cluster is calculated based on the second isolation voltage. In this case, the sampling accuracy of the total voltage of the battery cluster is improved by multi-stage segmented sampling of the total voltage of the battery cluster. In addition, the safety of the energy storage BMS device is improved through two-stage isolation processing. In addition, the range of the total voltage of the battery cluster is 0 to 1500V. The total voltage of the battery cluster is sampled in segments, which reduces the range of a single sampling channel and has high sampling accuracy. Compared with the traditional sampling method, the accuracy can reach within ±0.1%. At the same time, the present invention adopts a two-stage isolation technology, and the analog signal of each voltage detection is first isolated, and the digital signal after ADC sampling is isolated, so the system has high security and strong anti-interference ability.

[0108] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this disclosure is not limited here.

[0109] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A three-stage dual-isolation voltage sampling energy storage BMS device, characterized in that: It includes a primary voltage divider circuit, a secondary voltage divider circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip and a processing chip connected in sequence, wherein: The primary voltage divider circuit is connected to the battery cluster, and the primary voltage divider circuit is used to divide the total voltage of the battery cluster to obtain a first intermediate voltage; The secondary voltage dividing circuit is used to divide the first intermediate voltage to obtain a second intermediate voltage; The analog signal isolation circuit is used to perform isolation processing on the second intermediate voltage to obtain a first isolation voltage; The ADC sampling chip is used to obtain a sampling voltage based on the first isolation voltage; The magnetic isolation chip is used to isolate the sampled voltage to obtain a second isolation voltage; The processing chip is used to calculate the total voltage of the battery cluster based on the second isolation voltage; The primary voltage divider circuit is connected in parallel with the battery cluster, and the primary voltage divider circuit is formed by connecting a first voltage divider resistor, a second voltage divider resistor and a third voltage divider resistor in series; The secondary voltage-dividing circuit includes a fourth voltage-dividing resistor, a fifth voltage-dividing resistor, a sixth voltage-dividing resistor, a seventh voltage-dividing resistor, an eighth voltage-dividing resistor and a ninth voltage-dividing resistor connected in series in sequence, the fourth voltage-dividing resistor and the fifth voltage-dividing resistor are connected in parallel with the first voltage-dividing resistor, the sixth voltage-dividing resistor and the seventh voltage-dividing resistor are connected in parallel with the second voltage-dividing resistor, and the eighth voltage-dividing resistor and the ninth voltage-dividing resistor are connected in parallel with the third voltage-dividing resistor.

2. The three-stage dual-isolation voltage sampling energy storage BMS device according to claim 1, characterized in that: The analog signal isolation circuit includes a first analog isolator, a second analog isolator, and a third analog isolator. Both ends of the fourth voltage-dividing resistor are connected to the first analog isolator, both ends of the sixth voltage-dividing resistor are connected to the second analog isolator, and both ends of the eighth voltage-dividing resistor are connected to the third analog isolator.

3. The three-stage dual-isolation voltage sampling energy storage BMS device according to claim 1, characterized in that: The processing chip is used for: The second intermediate voltage is calculated based on the second isolation voltage, the first intermediate voltage is calculated based on the second intermediate voltage, and the total voltage of the battery cluster is calculated based on the first intermediate voltage.

4. The three-stage dual-isolation voltage sampling energy storage BMS device according to claim 2, characterized in that: The models of the first analog isolator, the second analog isolator and the third analog isolator are all TE6664N.

5. The three-stage dual-isolation voltage sampling energy storage BMS device according to claim 1, characterized in that: The model of the ADC sampling chip is ADCS8162, and the model of the magnetic isolation chip is BLD7741.

6. The three-stage dual-isolation voltage sampling energy storage BMS device according to claim 1 or 5, characterized in that: The processing chip adopts an MCU chip of model GD32F407.

7. A three-stage dual-isolation voltage sampling method, characterized in that: The three-stage dual-isolation voltage sampling method is implemented using the three-stage dual-isolation voltage sampling energy storage BMS device according to any one of claims 1 to 6, including: Dividing the total voltage of the battery cluster to obtain a first intermediate voltage; Dividing the first intermediate voltage to obtain a second intermediate voltage; Inputting the second intermediate voltage into an analog signal isolation circuit for isolation to obtain a first isolation voltage; Performing ADC sampling on the first isolation voltage to obtain a sampled voltage; Inputting the sampled voltage into a magnetic isolation chip for isolation to obtain a second isolation voltage; The total voltage of the battery cluster is calculated based on the second isolation voltage.

8. The three-stage dual isolation voltage sampling method according to claim 7, characterized in that: The calculating and obtaining the total voltage of the battery cluster based on the second isolation voltage includes: The second intermediate voltage is calculated based on the second isolation voltage, the first intermediate voltage is calculated based on the second intermediate voltage, and the total voltage of the battery cluster is calculated based on the first intermediate voltage.

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