A wire-free power device

Abstract

The present invention provides a wireless power device comprising a first chip, a second chip, a circuit board, and a package. The first chip has a dedicated electrode and one or more common electrodes. The second chip has a second bottom electrode and one or more second top electrodes. The circuit board includes a carrier, one side of the carrier having a plurality of first connection areas and another side of the carrier having a plurality of second connection areas, the first connection areas being electrically connected to corresponding second connection areas. The second chip is disposed above the dedicated electrode, the second bottom electrode being electrically connected to the dedicated electrode. The common electrode is electrically connected to the corresponding first connection area. The first chip, the second chip, and the circuit board are packaged within the package. The wireless power device, through its laminated wireless structure design, can reduce the overall size of the power device and avoid the generation of parasitic inductance.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a wire-free power device. Background Art

[0002] Figure 1 The schematic diagram of the power device circuit formed by cascading depletion-mode GaN and MOS tubes is shown.

[0003] Currently, GaN (gallium nitride) chips are divided into two types: enhancement-mode GaN (E-Mode) and depletion-mode GaN (D-Mode). The fabrication process for enhancement-mode GaN, which is used for high-voltage operation, is still immature, and the resulting devices still suffer from numerous issues, such as small gate voltage swing and unstable threshold voltage. In contrast, depletion-mode GaN offers superior stability and a mature fabrication process. Furthermore, single-cell depletion-mode GaN HEMTs can easily achieve high breakdown voltages exceeding 600V and boast a wide range of drive power supplies.

[0004] However, depletion-mode GaN chips are normally-on devices, significantly increasing the system's static power consumption compared to enhancement-mode GaN chips. In this case, depletion-mode GaN chips are typically cascaded with MOS transistors to form a power device. The MOS transistors control the depletion-mode GaN chips, reducing their static power consumption.

[0005] Refer to the attached drawings Figure 2 The schematic diagram of the structure of a power device under the prior art is shown, and the shaded areas in the figure are all conductive areas. Specifically, a substrate with a conductive surface serves as a carrier for a depletion-mode GaN chip and a MOS transistor chip. The D electrode of the MOS transistor chip is bonded to the surface of the substrate. The connections between the remaining pins of the depletion-mode GaN chip and the MOS transistor chip, as well as the connections between the chip pins and the device pads, are all achieved through wire bonding. On the one hand, the side-by-side arrangement of the two chips and the arrangement of the device pads will result in a large bottom area of ​​the entire device. On the other hand, the large number of wire bonds can easily generate parasitic inductance, affecting the normal operation of the device. Summary of the Invention

[0006] In order to reduce the volume of power devices and avoid the generation of parasitic inductance, an embodiment of the present invention provides a wireless power device and a packaging method thereof. The design of a stacked wireless structure can reduce the overall volume of the power device and avoid the generation of parasitic inductance.

[0007] Accordingly, the present invention provides a wire-free power device, comprising a first chip, a second chip, a circuit board, and a package;

[0008] The first chip has a dedicated electrode and one or more common electrodes, both located on the top surface;

[0009] The second chip has a second bottom surface electrode and one or more second top surface electrodes;

[0010] The circuit board includes a carrier board, a plurality of first connection areas are provided on one side surface of the carrier board, and a plurality of second connection areas are provided on another side surface of the carrier board, and any first connection area is electrically connected to any corresponding second connection area;

[0011] The second chip is arranged above the dedicated electrode, and the second bottom electrode is electrically connected to the dedicated electrode;

[0012] The circuit board is arranged above the common electrode and the circuit board is directly opposite to the common electrode, and the common electrode is electrically connected to the corresponding first connection area;

[0013] The first chip, the second chip and the circuit board are packaged based on the package body.

[0014] In an optional embodiment, a top surface of the second top surface electrode and a top surface of the second connection region are exposed outside the package body;

[0015] A top surface of the second top surface electrode and a top surface of the second connection region are at the same height.

[0016] In an optional embodiment, the first connection region or the second connection region includes a base layer, and the base layer is disposed on the carrier board.

[0017] In an optional embodiment, the first connection area or the second connection area further includes a raising layer, the raising layer is arranged on the base layer, and the raising layer is electrically connected to the base layer.

[0018] In an optional embodiment, the padding layer is bonded to the corresponding base layer via a dielectric layer formed of solder;

[0019] Or the cushion layer and the base layer are an integrated structure.

[0020] In an optional embodiment, the common electrode is electrically connected to the corresponding first connection area through a dielectric layer formed by solder.

[0021] In an optional embodiment, the second bottom electrode is bonded to the dedicated electrode through a dielectric layer formed by solder.

[0022] In an optional embodiment, the circuit board is also directly opposite to the dedicated electrode;

[0023] The dedicated electrode is electrically connected to a corresponding first connection area, and the second chip is disposed on the corresponding second connection area;

[0024] The second bottom electrode is electrically connected to the corresponding second connection region.

[0025] In an optional embodiment, the dedicated electrode is electrically connected to the corresponding first connection area through a dielectric layer formed by solder, and the second bottom electrode is bonded to the corresponding second connection area through a dielectric layer formed by solder.

[0026] In an optional embodiment, the first chip is a gallium nitride chip, and the gallium nitride chip has a first S pole, a first D pole, and a first G pole located on a top surface, the first S pole is a dedicated electrode, and the first D pole and the first G pole are both common electrodes;

[0027] The second chip is a switch tube chip, which has a second D pole located on the bottom surface, and a second G pole and a second S pole located on the top surface. The second D pole is a second bottom electrode, and the second G pole and the second S pole are respectively second top electrodes.

[0028] In an optional embodiment, a projection outline of the second chip on the top surface of the dedicated electrode is located within an area surrounded by the top surface outline of the dedicated electrode.

[0029] In summary, the present invention provides a wire-free power device, which redesigns the packaging structure of the power device. Compared with the implementation structure under the prior art, the wire-free power device of the present invention reduces the footprint of the power device by stacking the gallium nitride chip and the switch tube chip and not adopting the implementation structure such as adding lead pins, which is conducive to the miniaturization of the power device; the implementation structure of not adopting wire connection in the power device can, on the one hand, increase the conductive cross-sectional area and improve the transmission power of the power device; on the other hand, no gap for wire bonding is required in the structural layout, which can reduce the volume of the power device; in actual implementation, the thickness of the pad layer, dielectric layer, and carrier board can be flexibly adjusted according to the thickness of the switch tube chip to minimize the volume of the power device; in the packaging process of the power device, there is no wire bonding process, and the conduction between the chips mainly depends on the routing of the metal layer and the solder conduction. The metal layer is directly led out as a pin without the need for wire bonding, which simplifies the packaging process while avoiding the parasitic inductance caused by wire bonding, and has good production convenience. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 This is the schematic diagram of the power device circuit formed by the cascade connection of depletion-mode GaN and MOS tubes.

[0032] Figure 2 Schematic diagram of the structure of a power device in the prior art.

[0033] Figure 3 Schematic diagram of the three-dimensional structure of the gallium nitride chip according to an embodiment of the present invention.

[0034] Figure 4 Schematic diagram of the three-dimensional structure of the switch tube chip according to an embodiment of the present invention.

[0035] Figure 5 Schematic diagram of the three-dimensional structure of the bond-free power device according to the first embodiment of the present invention.

[0036] Figure 6 This is a schematic diagram of the front view of the structure of the wire-free power device on the second G-pole side according to the first embodiment of the present invention.

[0037] Figure 7 This is a schematic front view of the structure of the wire-free power device according to the first embodiment of the present invention on one side of the first G-pole upper connection area.

[0038] Figure 8 This is a schematic side view of the structure of the wire-free power device according to the first embodiment of the present invention on the side of the first D-pole upper connection area.

[0039] Figure 9 Schematic diagram of the three-dimensional structure of the wire-free power device according to the second embodiment of the present invention.

[0040] Figure 10 This is a schematic diagram of the front view of the structure of the wire-free power device on the second G-pole side according to the second embodiment of the present invention.

[0041] Figure 11 This is a schematic front view of the structure of the wire-free power device according to the second embodiment of the present invention on one side of the first G-pole upper connection area.

[0042] Figure 12 This is a schematic side view of the structure of the wire-free power device according to the second embodiment of the present invention on the side of the first D-pole upper connection area.

[0043] Figure 13FIG. 1 is a schematic diagram of a three-dimensional structure of a wire-free power device having a package body according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] First, the basic structure of a wireless power device according to an embodiment of the present invention is described. Basically, an embodiment of the present invention provides a wireless power device, including a first chip, a second chip, a circuit board, and a package.

[0046] Basically, the structural limitation of the first chip is that the first chip has a dedicated electrode and one or more universal electrodes, both of which are located on the top surface; the dedicated electrode and the universal electrode are only named to facilitate the subsequent description. In essence, the dedicated electrode and the universal electrode are both conventional electrode structures.

[0047] The second chip has a second bottom electrode and one or more second top electrodes. According to the specification, the second bottom electrode is located on the bottom surface of the second chip, and the second top electrode is located on the top surface of the second chip.

[0048] The circuit board includes a carrier board, and a plurality of first connection areas are provided on one side of the carrier board, and a plurality of second connection areas are provided on the other side of the carrier board, and any first connection area is electrically connected to a corresponding second connection area. Generally, a common circuit board is composed of a carrier board and a conductive layer distributed on both sides of the carrier board. The conductive layer can arrange the circuit according to the needs, and the arrangement of the circuit will produce corresponding electrical conduction and electrical isolation. In an embodiment of the present invention, for the convenience of description, according to the implementation characteristics of the wire-free power device of the embodiment of the present invention, a plurality of first connection areas are provided on one side of the carrier board, and different first connection areas can be connected or disconnected according to needs; similarly, a plurality of second connection areas are provided on the other side of the carrier board, and different second connection areas can be connected or disconnected according to needs; a first connection area and a corresponding second connection area are paired and connected, so that current can be transmitted across the carrier board.

[0049] It should be noted that the first connection region and the second connection region in the embodiment of the present invention merely represent a conductive structure provided on the carrier, and do not represent only a conventional conductive layer structure.

[0050] The second chip is arranged above the dedicated electrode, and the second bottom electrode is electrically connected to the dedicated electrode; specifically, the second chip is arranged above the dedicated electrode, and in addition to the wire connection, there are multiple ways to electrically connect the second bottom electrode and the dedicated electrode, which will be further explained in conjunction with specific embodiments later.

[0051] The circuit board is arranged above the universal electrode and the circuit board is opposite to any universal electrode, and any universal electrode is electrically connected to the corresponding first connection area; basically, the structural design of the circuit board and its coverage area need to meet the limiting condition of being opposite to the universal electrode, and accordingly, any universal electrode can be electrically connected to the corresponding first connection area. Specifically, the specific implementation method of the universal electrode being able to be electrically connected to the corresponding first connection area will be further explained in conjunction with specific examples later.

[0052] The top surface of any second top surface electrode and the top surface of any second connection region are at the same height. The first chip, the second chip, and the circuit board are packaged within the package, and the top surface of any second top surface electrode and the top surface of any second connection region are exposed from the package. Specifically, since the package generally has a regular rectangular parallelepiped structure, to facilitate device use, during design, it is necessary to meet the requirement that the top surface of any second top surface electrode and the top surface of any second connection region are at the same height, ensuring that the top surface of any second top surface electrode and the top surface of any second connection region can be simultaneously exposed from the package for external use.

[0053] It should be noted that, in the specific implementation, due to the influence of factors such as the second chip size (mainly the height dimension), the circuit board thickness, and the construction process, in order to ensure that the top surface of any second top surface electrode and the top surface of any second connection area are at the same height, it is necessary to flexibly design its implementation structure, which will be explained in conjunction with specific embodiments later.

[0054] For ease of explanation, the embodiment of the present invention is specifically described by taking an example where the first chip is a gallium nitride chip and the second chip is a switch tube chip.

[0055] Combined with the attached drawings Figure 3 and attached pictures Figure 4 Schematic structure, specifically, the first chip is a gallium nitride chip 10, and the gallium nitride chip has a first S pole 12, a first D pole 11 and a first G pole 13 located on the top surface, the first S pole is a dedicated electrode, and the first D pole and the first G pole are both common electrodes;

[0056] The second chip is a switch tube chip 20, which has a second D pole 23 located on the bottom surface, and a second G pole 21 and a second S pole 22 located on the top surface. The second D pole is a second bottom electrode, and the second G pole and the second S pole are respectively second top electrodes.

[0057] Specifically, the carrier plate 30 has a first mounting surface and a second mounting surface. It should be noted that the carrier plate 30 in this embodiment of the present invention only refers to the portion of the structure that supports the load. The carrier plate 30 itself can be made of existing materials. Furthermore, the combination of the conductive structure and other components provided on the carrier plate 30 described later and the carrier plate 30 can also be obtained by further processing existing finished products. The first connection area is provided on the first mounting surface, and the second connection area is provided on the second mounting surface.

[0058] In view of the direction shown in the figure, in order to facilitate distinction, in the subsequent component naming, the first connection area is suffixed as the lower connection area, and the second connection area is suffixed as the upper connection area.

[0059] Basically, the carrier 30 is provided on the first mounting surface with a first D-pole lower connection region 33 corresponding to the first D-pole 11 and a first G-pole lower connection region 36 corresponding to the first G-pole 13. The first D-pole 11 is bonded to the first D-pole lower connection region 33, and the first G-pole 13 is bonded to the first G-pole lower connection region 36. Specifically, the corresponding relationship described in this embodiment of the present invention refers to a positional correspondence, facilitating direct bonding of the first D-pole 11 and the first G-pole 13.

[0060] Furthermore, the carrier 30 is provided with a first D-pole upper connection area 34 electrically connected to the first D-pole lower connection area 33 and a first G-pole upper connection area 35 electrically connected to the first G-pole lower connection area 36 on the second mounting surface.

[0061] Specifically, the specific implementation structure of the first D-pole upper connection area 34 and the first G-pole upper connection area 35 needs to be confirmed based on the relative positional relationship between the height of the chip and the thickness of the carrier board.

[0062] Basically, the first connection area (i.e., the lower connection area) or the second connection area (i.e., the upper connection area) includes a base layer, which is provided on the carrier. The base layer can be understood as a conventional conductive layer structure of a circuit board. Correspondingly, for clarity of description, the embodiment takes the second connection area (i.e., the upper connection area) as an example, where the base layer includes the first D-pole upper connection area 34 as the first D-pole base layer, and the base layer of the first G-pole upper connection area 35 as the first G-pole base layer.

[0063] In the case of only the base layer, if the top surface height of the second connection region is still lower than the top surface height of the second top electrode, a padding layer needs to be added on the basis of the base layer to make up for the height difference.

[0064] Specifically, the first connection area (ie, the lower connection area) or the second connection area further includes a raising layer, the raising layer is arranged on the base layer, and the raising layer is electrically connected to the base layer.

[0065] Specifically, the padding layer and the base layer may be an integral structure, or the padding layer may be bonded to the corresponding base layer via a dielectric layer formed by solder.

[0066] The switch tube chip 20 is arranged above the first S pole 12, and the second D pole 23 is electrically connected to the first S pole 12; specifically, regarding the implementation method of electrically connecting the second D pole 23 to the first S pole 12, the subsequent embodiment 1 and embodiment 2 respectively provide two embodiments for reference.

[0067] Specifically, the packaging layer encapsulates the gallium nitride chip 10, the switch chip 20, and the carrier 30. The top surfaces of the first D-pole upper connection region 34, the first G-pole upper connection region 35, the second S-pole 22, and the second G-pole 21 are all located at the same height and exposed to the package. Specifically, the package of this embodiment of the present invention integrally encapsulates the gallium nitride chip 10, the switch chip 20, and the carrier 30 to protect them and form a regular outer structure for ease of subsequent use. Specifically, the power device is subsequently used as a single integral component. In this embodiment of the present invention, all externally directed pins are located on the same side and at the same height, facilitating surface mount (SMD) use.

[0068] Specifically, in the power device introduced in the embodiment of the present invention, a more important point is how to ensure that the top surface of the first D-pole upper connection area 34, the top surface of the first G-pole upper connection area 35, the top surface of the second S-pole 22 and the top surface of the second G-pole 21 are all located at the same height and exposed to the package body; in order to achieve consistent top surface heights of multiple components, detailed structural definitions are required for all related structures involved.

[0069] Specifically, with respect to the common structure of Embodiments 1 and 2, the first D-pole 11 is bonded to the first D-pole lower connection region 33 based on a first dielectric layer 32; and / or the first G-pole 13 is bonded to the first G-pole lower connection region 36 based on a second dielectric layer 37. Specifically, the dielectric layer may be a bonding structure composed of materials such as silver paste and solder. The dielectric layer is typically formed by transforming a liquid raw material into a solid structure. Therefore, in practice, its thickness can be flexibly adjusted. To ensure that the final structure of the power device meets the requirements, the thickness of the dielectric layer needs to be considered during design. Furthermore, as a structure with flexible thickness adjustment during processing, the dielectric layer can also be used to adjust its thickness within a certain range to account for actual implementation errors, so that the top surfaces of the first D-pole upper connection region 34, the first G-pole upper connection region 35, the second S-pole 22, and the second G-pole 21 are all located at the same height.

[0070] The carrier plate is initially a flat plate structure having a standard thickness (reference value).

[0071] Furthermore, the standard thickness of the carrier 30 is a preset value. According to the thickness difference between the switch tube chip 20 and the carrier 30, the carrier 30 can be better adapted to the height of the switch tube chip 20 by cutting or other processing methods. Optionally, the thickness of the carrier 30 at the position corresponding to the first D-pole lower connection area 33 and the first D-pole upper connection area 34 is less than or equal to the standard thickness; and / or the thickness of the carrier 30 at the position corresponding to the first G-pole lower connection area 36 and the first G-pole upper connection area 35 is less than or equal to the standard thickness.

[0072] In addition, combined Figure 5 and Figure 6 In the schematic structure, the space for installing the switch tube chip 20 is limited, and the switch tube cannot block the installation of the side elevation layer. Therefore, in an optional embodiment, the projection of the switch tube chip 20 on the top surface of the first S-pole 12 is located within the area surrounded by the top surface outline of the first S-pole 12. Correspondingly, the projection of the switch tube chip on the top surface of the gallium nitride chip is located within the top surface outline of the gallium nitride chip, which can ensure the minimization of the power device volume.

[0073] Specifically, the implementation of electrically connecting the second D pole and the first S pole will be described below using the examples of embodiment 1 and embodiment 2 as examples.

[0074] Example 1:

[0075] Refer to the attached drawings Figure 5 FIG. 1 shows a schematic diagram of a three-dimensional structure of a wire-free power device according to an embodiment of the present invention.

[0076] Based on the foregoing, the carrier 30 of the embodiment of the present invention forms a relief region above the first S-pole 12. Specifically, the carrier 30 has physical structures only at locations corresponding to the first D-pole 11 and the first G-pole 13, and no physical structure of the carrier 30 exists above the first S-pole 12. The switch chip 20 is disposed in the relief region, and the second D-pole 23 is bonded to the first S-pole 12.

[0077] Specifically, the advantage of the implementation scheme of the embodiment of the present invention is that the avoidance area formed by the special-shaped carrier board 30 structure for the switch tube chip 20 to be installed can minimize the overall thickness of the device, which is conducive to the miniaturization of the device.

[0078] Specifically, in actual implementation, the second D pole 23 needs to be bonded to the first S pole 12 based on the third dielectric layer 31. The thickness of the third dielectric layer 31 will affect the top surface height of the second S pole 12 and the second G pole 21. Therefore, the thickness of the third dielectric layer 31 needs to be designed in advance.

[0079] It should be noted that the implementation condition of Example 1 is that the height of the second top surface electrode is greater than or equal to the height of the base layer. If the height of the second top surface electrode is greater than the height of the base layer, it is necessary to increase the padding layer to make up for the height difference to meet the implementation requirements.

[0080] Example 2:

[0081] Refer to the attached drawings Figure 9 FIG. 1 shows a schematic diagram of a three-dimensional structure of a wire-free power device according to an embodiment of the present invention.

[0082] Specifically, the carrier 30 is further provided with a first S-pole lower connection area 41 corresponding to the first S-pole 12 on the first mounting surface, and the carrier 30 is further provided with a first S-pole upper connection area 42 connected to the first S-pole lower connection area 41 on the second mounting surface; the switching tube chip 20 is located on one side of the second mounting surface of the carrier 30, and the second D-pole 23 is bonded to the first S-pole upper connection area 42.

[0083] Different from the first embodiment, the carrier 30 of the embodiment of the present invention is provided with a first S-pole lower connection area 41 and a first S-pole upper connection area 42 at a position corresponding to the first S-pole 12. The carrier 30 itself has a regular shape. The first S-pole lower connection area 41 is bonded to the first S-pole 12, and the first S-pole upper connection area 42 is bonded to the second D-pole 23.

[0084] Specifically, the advantages of the implementation scheme of the embodiment of the present invention are that the carrier 30 itself is a regular square structure, the material utilization rate is high, and the implementation difficulty is low; the structure of the carrier 30 is conducive to the processing of other components based on the carrier 30, which is conducive to simplifying the performance requirements of the equipment from the implementation process.

[0085] In addition, for the implementation condition that cannot be met in the first embodiment, that is, when the height of the second top surface electrode is less than the height of the base layer, since the structure of the second chip cannot be changed, it is necessary to help the circuit board to lift the second chip.

[0086] Due to the setting of the carrier 30, the superposition of the thickness of the carrier 30 and the thickness of the switch tube chip 20 will increase the thickness of the final formed device. Therefore, in order to reduce the thickness of the power device, similarly, the thickness of the carrier 30 at the position corresponding to the first S-pole lower connection area 41 and the first S-pole upper connection area 42 is less than or equal to the standard thickness.

[0087] In addition, the second D pole 23 needs to be bonded to the first S pole upper connection area 42 based on the fourth dielectric layer 43. In order to accurately control the height of the corresponding position, the thickness of the fourth dielectric layer 43 is a preset value; similarly, the first S pole 12 is bonded to the first S pole lower connection area 41 based on the fifth dielectric layer 44, and the thickness of the fifth dielectric layer 44 is a preset value.

[0088] Based on the implementation schemes of Example 1 and Example 2, the structure of the aforementioned wire-free power device is described, which mainly involves the size limitations of three areas. Figure 5 and attached pictures Figure 9 Schematic structure. Specifically, to ensure that the second G-pole 21, second S-pole 22, first D-pole upper connection area 34, and first G-pole upper connection area 35 are at the same height after packaging, facilitating subsequent chip placement, it is necessary to accurately control the final top surface height of the second G-pole 21 (second S-pole 22), first D-pole upper connection area 34, and first G-pole upper connection area 35 during actual processing. It should be noted that the second G-pole 21 and second S-pole 22 are structures on the same chip and their heights are assumed to be consistent.

[0089] Example 3:

[0090] Specifically, in combination with the description of embodiment 1, Figure 6 FIG. 1 shows a schematic diagram of the front view of the structure of the non-bonding wire power device on the second G-pole side. Figure 7 FIG. 1 shows a front view of the structure of the non-bonding wire power device on one side of the first G-pole upper connection area 35 . Figure 8 A schematic side view of the structure of the wire-free power device on the side of the first D-pole upper connection area is shown.

[0091] It should be noted that the top surface electrodes (first D pole, first S pole, first G pole) on the gallium nitride chip are all planar structures exposed only on the top surface of the gallium nitride chip. Taking the top surface height of the gallium nitride chip as a reference, the top surface height of the top surface electrodes is 0, and the top surface of the top surface electrodes is the same as the top surface height of the gallium nitride chip.

[0092] Specifically, the embodiment of the present invention is described with the final top surface forming height H of the second G pole 21 (second S pole 22 ), the first D pole upper connection area 34 and the first G pole upper connection area 35 .

[0093] According to the accompanying drawings Figure 6 The final height of the top surface of the second G-pole 21 (second S-pole 22) is H, and the elements that constitute the final height of the top surface of the second G-pole (second S-pole) include: the thickness a of the gallium nitride chip 10, the thickness b of the third dielectric layer 31, the thickness g of the switch tube chip 20, and the thickness n of the second G-pole 21 (second S-pole 22). It should be noted that if the second G-pole 21 (second S-pole 22) is a structure embedded in the switch tube chip, then n is 0.

[0094] According to the accompanying drawings in the figure Figure 7 The final height of the top surface of the first G-pole upper connection area 35 is H, and the elements constituting the final height of the top surface of the first G-pole upper connection area 35 include: the thickness a of the gallium nitride chip 10, the thickness h of the second dielectric layer 37, the thickness i of the first G-pole lower connection area 36, ​​the thickness d of the carrier 30 and the thickness j of the first G-pole upper connection area 35.

[0095] According to the accompanying drawings Figure 8 The final height of the top surface of the first D-pole upper connection area 34 is H, and the elements constituting the final height of the top surface of the first D-pole upper connection area 34 include: the thickness a of the gallium nitride chip 10, the thickness k of the first dielectric layer 32, the thickness I of the first D-pole lower connection area 33, the thickness d of the carrier 30 and the thickness m of the first D-pole upper connection area 34.

[0096] Example 4:

[0097] Specifically, in combination with the description of Example 2, Figure 10 FIG. 1 shows a schematic diagram of the front view of the structure of the non-bonding wire power device on the second G-pole side. Figure 11 This is a schematic front view of the structure of the wire-free power device according to the second embodiment of the present invention on the side of the first G-pole upper connection area. Figure 12 This is a schematic side view of the structure of the wire-free power device according to the second embodiment of the present invention on the side of the first D-pole upper connection area.

[0098] Specifically, the embodiment of the present invention is described with the final top surface forming height H of the second G pole 21 (second S pole 22), the first D pole upper connection area 34, and the first G pole upper connection area 35. Specifically, the second G pole 21 and the second S pole 22 are generally the same, so only one of the electrodes is used as an example for description.

[0099] According to the accompanying drawings Figure 10 The final height of the top surface of the second G-pole 21 (second S-pole 22) is H, and the elements that constitute the final height of the top surface of the second G-pole 21 (second S-pole 22) include: the thickness a of the gallium nitride chip 10, the thickness b of the third dielectric layer 31, the thickness c of the first S-pole lower connection area 41, the thickness d of the carrier 30, the thickness e of the first S-pole upper connection area 42, the thickness f of the fourth dielectric layer 43, the thickness g of the switch tube chip 20, and the thickness n of the second G-pole 21 (second S-pole 22). It should be noted that if the second G-pole 21 (second S-pole 22) is a structure embedded in the switch tube chip, then n is 0.

[0100] According to the accompanying drawings Figure 11 The final height of the top surface of the first G-pole upper connection area 35 is H, and the elements constituting the final height of the top surface of the first G-pole upper connection area 35 include: the thickness a of the gallium nitride chip 10, the thickness h of the second dielectric layer 37, the thickness i of the first G-pole lower connection area 36, ​​the thickness d of the carrier 30 and the thickness j of the first G-pole upper connection area 35.

[0101] According to the accompanying drawings Figure 12 The final height of the top surface of the first D-pole upper connection area 34 is H, and the elements constituting the final height of the top surface of the first D-pole upper connection area 34 include: the thickness a of the gallium nitride chip 10, the thickness k of the first dielectric layer 32, the thickness I of the first D-pole lower connection area 33, the thickness d of the carrier 30 and the thickness m of the first D-pole upper connection area 34.

[0102] In conjunction with the implementation contents of the third and fourth embodiments, specifically, in the wireless power device of the embodiment of the present invention, the dielectric layer is a connection structure used to connect different components. The dielectric layer is processed last during the manufacturing process. During the design stage, the designers, based on theoretical data and limited by the total height of the stacking position of the gallium nitride chip 10 and the switch tube chip 20, change the thickness of the other components accordingly.

[0103] In specific implementation, the processing thickness of each component except the dielectric layer will be affected by the processing accuracy and have certain differences; in actual processing, the dielectric layer is the last structure to be processed and the dielectric layer is generally a structure converted from liquid to solid. Therefore, in actual implementation, in order to ensure the height consistency of the top surface of the raising layer set in the second connection area, the second G pole and the second S pole top surface, the forming thickness of each dielectric layer can be controlled by real-time monitoring and control.

[0104] Embodiment 5:

[0105] Combined with the attached drawings Figure 5 and attached pictures Figure 9 The power device structure shown in FIG. 1 is designed so that the electrodes that need to be connected to the outside of the power device are connected to the same plane, so that the power device can be used as a patch. For details, refer to FIG. Figure 13 The schematic diagram of the three-dimensional structure of the power device with the package body is shown in FIG. Figure 5 On the basis of the implementation structure, the first chip, the second chip and the circuit board are packaged based on a package body, and the top surface of the second top surface electrode and the top surface of the second connection area are exposed from the package body 60.

[0106] Specifically, in the embodiment of the present invention, the top surface of the second G pole 21 , the top surface of the second S pole 22 , the top surface of the first D pole upper connection region 34 , and the top surface of the first G pole upper connection region 35 are exposed to the package body 60 .

[0107] In summary, the present invention provides a wire-free power device that redesigns the packaging structure of the power device. Compared with the implementation structure under the prior art, the wire-free power device of the embodiment of the present invention reduces the footprint of the power device by stacking the gallium nitride chip 10 and the switch tube chip 20, without using wire bonding connection, and without adding lead pins, which is conducive to the miniaturization of the power device. The implementation structure of not using wire bonding connection in the power device can, on the one hand, increase the conductive cross-sectional area and improve the transmission power of the power device. On the other hand, no gap for wire bonding is required in the structural layout, which can reduce the volume of the power device. In actual implementation, the thickness of the pad layer, dielectric layer, and circuit board can be flexibly adjusted according to the thickness of the switch tube chip 20 to minimize the volume of the power device. In the packaging process of the power device, there is no wire bonding process. The conduction between the chips mainly relies on the routing of the metal layer and the solder conduction. The metal layer is directly led out as a pin without the need for wire bonding, which simplifies the packaging process and avoids the parasitic inductance caused by wire bonding, and has good production convenience.

[0108] The above is a detailed introduction to a wire-free power device provided by an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A wireless power device, characterized in that: comprising a first chip, a second chip, a circuit board and a package; The first chip has a dedicated electrode and one or more common electrodes, both located on the top surface; The second chip has a second bottom surface electrode and one or more second top surface electrodes; The circuit board includes a carrier board, a plurality of first connection areas are provided on one side surface of the carrier board, and a plurality of second connection areas are provided on another side surface of the carrier board, and any first connection area is electrically connected to any corresponding second connection area; The second chip is arranged above the dedicated electrode, and the second bottom electrode is electrically connected to the dedicated electrode; The circuit board is arranged above the common electrode and the circuit board is directly opposite to the common electrode, and the common electrode is electrically connected to the corresponding first connection area; The first chip, the second chip and the circuit board are packaged based on the package body; The first chip is a gallium nitride chip, and the gallium nitride chip has a first S pole, a first D pole, and a first G pole located on the top surface, the first S pole is a dedicated electrode, and the first D pole and the first G pole are both common electrodes; The second chip is a switch tube chip, which has a second D pole located on the bottom surface, and a second G pole and a second S pole located on the top surface. The second D pole is a second bottom electrode, and the second G pole and the second S pole are respectively second top electrodes.

2. The wire-free power device according to claim 1, wherein: The top surface of the second top surface electrode and the top surface of the second connection region are exposed outside the package body; the top surface of the second top surface electrode and the top surface of the second connection region are at the same height.

3. The wire-free power device according to claim 1, wherein: The first connection region or the second connection region includes a base layer, and the base layer is arranged on the carrier board.

4. The wire-free power device according to claim 3, wherein: The first connection area or the second connection area further includes a raising layer, the raising layer is arranged on the base layer, and the raising layer is electrically connected to the base layer.

5. The wire-free power device according to claim 4, wherein: The padding layer is bonded to the corresponding base layer through a dielectric layer formed by solder; Or the cushion layer and the base layer are an integrated structure.

6. The wire-free power device according to claim 1, wherein: The common electrode is electrically connected to the corresponding first connection area through a dielectric layer formed by solder.

7. The wire-free power device according to claim 1, wherein: The second bottom electrode is bonded to the dedicated electrode through a dielectric layer formed by solder.

8. The wire-free power device according to claim 1, wherein: The circuit board is also directly opposite to the dedicated electrode; The dedicated electrode is electrically connected to a corresponding first connection area, and the second chip is disposed on the corresponding second connection area; The second bottom electrode is electrically connected to the corresponding second connection region.

9. The wire-free power device according to claim 8, wherein: The dedicated electrode is electrically connected to the corresponding first connection area through a dielectric layer formed by solder, and the second bottom electrode is bonded to the corresponding second connection area through a dielectric layer formed by solder.

10. The wire-free power device according to claim 1, wherein: The projection outline of the second chip on the top surface of the dedicated electrode is located within the enclosed area of ​​the top surface outline of the dedicated electrode.

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