Structure, manufacturing method and electronic device of gold hemi-contact device

Abstract

A structure, manufacturing method, and electronic device for a gold semiconductor contact device, belonging to the field of semiconductor technology, comprises a substrate, an edge ring structure, and a metal layer; the edge ring structure is located in the substrate; the metal layer covers the substrate and exposes the edge ring structure; wherein the edge ring structure includes n ion-doped well regions; n is a natural number greater than 1; the i-th ion-doped well region is located in the (i+1)-th ion-doped well region; i is a positive integer less than n; since the metal layer covers the substrate and exposes the edge ring structure, and the edge ring structure includes n ion-doped well regions; the i-th ion-doped well region is located in the (i+1)-th ion-doped well region, the edge of the metal layer forms a gradually weakening electric field distribution due to the nested ion-doped well regions, thereby improving the maximum reverse bias voltage and the reliability of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to the structure, manufacturing method and electronic device of a gold semiconductor contact device. Background Technology

[0002] Among the various power components used in the field of power electronics, such as Figure 1 As shown, the metal edge of the metal-semiconductor contact (metal-semiconductor contact) where the applied voltage is applied is often where the maximum reverse bias occurs, which limits the maximum reverse bias of the device and reduces the reliability of the device.

[0003] Device engineers have proposed many compensation methods for both three-dimensional and planar structures, such as... Figure 2 As shown, the electric field distribution can be changed by using single-layer or multi-layer junction termination extension (JTE). However, this method requires additional masks or even several masks. Multi-layer JTE requires multiple masks, which makes the process complex and reduces competitiveness in the cost-sensitive power electronics market.

[0004] Therefore, the design of traditional gold-plated semiconductor contact devices is not only complex but also costly. Summary of the Invention

[0005] The purpose of this application is to provide a structure, manufacturing method and electronic device for a gold semiconductor contact device, aiming to solve the problems that related gold semiconductor contact devices are not only complex in design but also costly.

[0006] This application provides a structure for a gold semiconductor contact device, including a substrate, an edge ring structure, and a metal layer;

[0007] The edge ring structure is located in the substrate;

[0008] The metal layer covers the substrate and exposes the edge ring structure;

[0009] The edge ring structure includes n ion-doped well regions; n is a natural number greater than 1.

[0010] The i-th ion-doped well region is located in the (i+1)-th ion-doped well region; i is a positive integer less than n.

[0011] In one embodiment, the majority carrier concentration of the i-th ion-doped well region is greater than that of the (i+1)-th ion-doped well region.

[0012] In one embodiment, the substrate is an N-type region, and the edge ring structure is a P-type region; or

[0013] The substrate is a P-type region, and the edge ring structure is an N-type region.

[0014] In one embodiment, in the vertical direction, the edge of the edge ring structure is located in the same plane as the edge of the metal layer.

[0015] This invention also provides a method for manufacturing a gold-semiconductor contact device, the method comprising:

[0016] Step A: Form the (m+1)th composite layer on the substrate or the mth composite layer; wherein the mth composite layer includes the mth groove and m material regions, and the mth material region to the 1st material region are arranged linearly in sequence; the (m+1)th composite layer includes the (m+1)th groove and m+1 material regions, and the (m+1)th material region to the 1st material region are arranged linearly in sequence; m is a positive integer less than or equal to n;

[0017] Repeat step A n times to form the nth composite layer; n is an integer greater than 1, and m is a positive integer less than n;

[0018] Step B: Ion implantation is performed on the surface of the j-th composite layer to form the (n-j+1)-th ion-doped well region at the location of the j-th groove in the substrate; j is a positive integer less than or equal to n;

[0019] Step C: Remove the j-th material region in the j-th composite layer to form the (j-1)-th composite layer; or remove the first composite layer to expose the substrate;

[0020] Repeat steps B and C n times to form an edge ring structure; the edge ring structure includes n ion-doped well regions; n is a natural number greater than 1; the i-th ion-doped well region is located in the (i+1)-th ion-doped well region; i is a positive integer less than n;

[0021] Step D: A metal layer is formed on the upper surface of the substrate; the metal layer covers the substrate and exposes the edge ring structure.

[0022] In one embodiment, when step A is performed for the first time, step A includes: forming a first composite layer on the substrate;

[0023] When step A is not performed for the first time, step A includes: forming a (m+1)th composite layer on the mth composite layer.

[0024] In one embodiment, forming the first composite layer on the substrate includes:

[0025] A first barrier layer is formed on the substrate;

[0026] The first composite layer is formed by imaging the first barrier layer.

[0027] The formation of the (m+1)th composite layer on the mth composite layer includes:

[0028] The (m+1)th barrier layer is formed on the mth composite layer;

[0029] Remove the upper surface of the (m+1)th barrier layer and retain the (m+1)th barrier layer on the sidewall of the mth composite layer to form the (m+1)th composite layer.

[0030] In one embodiment, when step C is performed for the last time, step C includes: removing the first composite layer to expose the substrate;

[0031] When step C is not performed for the last time, step C includes: removing the j-th material region in the j-th composite layer to form the (j-1)-th composite layer.

[0032] In one embodiment, the materials of the various material regions are different.

[0033] This application also provides an electronic device, characterized in that the electronic device includes the structure of the gold semiconductor contact device described above.

[0034] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: since the metal layer covers the substrate and exposes the edge ring structure, and the edge ring structure includes n ion-doped well regions; the i-th ion-doped well region is located in the (i+1)-th ion-doped well region; the edge of the metal layer forms a gradually weakening electric field distribution due to the nested ion-doped well regions, which improves the maximum reverse bias voltage of the device and the reliability of the device. Attached Figure Description

[0035] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A three-dimensional structural diagram of a prior art gold-semiconductor contact device;

[0037] Figure 2 A schematic diagram of another three-dimensional structure of the existing gold-semiconductor contact device;

[0038] Figure 3 A three-dimensional structural schematic diagram of a gold-semiconductor contact device provided in an embodiment of this application;

[0039] Figure 4 A schematic diagram of forming a first barrier layer in a method for manufacturing a gold-semiconductor contact device provided in an embodiment of this application;

[0040] Figure 5 A schematic diagram of forming the first composite layer in a method for manufacturing a gold-semiconductor contact device provided in an embodiment of this application;

[0041] Figure 6 A schematic diagram of forming a second barrier layer in a method for manufacturing a gold-semiconductor contact device according to an embodiment of this application;

[0042] Figure 7 A schematic diagram of forming the second composite layer in a method for manufacturing a gold-semiconductor contact device provided in an embodiment of this application;

[0043] Figure 8 A schematic diagram of forming a third barrier layer in a method for manufacturing a gold-semiconductor contact device according to an embodiment of this application;

[0044] Figure 9 A schematic diagram of forming the third composite layer in a method for manufacturing a gold-semiconductor contact device provided in an embodiment of this application;

[0045] Figure 10 This is a schematic diagram of the formation of a first ion-doped trap region in the manufacturing method of the gold semiconductor contact device provided in the embodiments of this application;

[0046] Figure 11 A schematic diagram of the formation of the second composite layer in the manufacturing method of the gold semiconductor contact device provided in the embodiments of this application;

[0047] Figure 12 This is a schematic diagram illustrating the formation of a second ion-doped trap region in a method for manufacturing a gold semiconductor contact device according to an embodiment of this application.

[0048] Figure 13 A schematic diagram of the formation of the first composite layer in the manufacturing method of the gold semiconductor contact device provided in the embodiments of this application;

[0049] Figure 14 This is a schematic diagram illustrating the formation of a third ion-doped trap region in a method for manufacturing a gold semiconductor contact device according to an embodiment of this application.

[0050] Figure 15 A schematic diagram showing the substrate in a method for manufacturing a gold semiconductor contact device provided in an embodiment of this application;

[0051] Figure 16 This is a schematic diagram of the formation of a metal layer in a method for manufacturing a gold-semiconductor contact device provided in an embodiment of this application. Detailed Implementation

[0052] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0053] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0054] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0056] Figure 3 The modular structure of the gold semiconductor contact device provided in the embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below:

[0057] The structure of the aforementioned gold-semiconductor contact device includes a substrate 90, an edge ring structure 10, and a metal layer 20.

[0058] The edge ring structure 10 is located in the substrate 90; the metal layer 20 covers the substrate 90 and exposes the edge ring structure 10; wherein the edge ring structure 10 includes n ion-doped well regions; n is a natural number greater than 1; the i-th ion-doped well region is located in the (i+1)-th ion-doped well region; i is a positive integer less than n.

[0059] As an example and not a limitation, substrate 90 is an N-type region and edge ring structure 10 is a P-type region.

[0060] As an example and not a limitation, substrate 90 is a P-type region and edge ring structure 10 is an N-type region.

[0061] It should be noted that the majority carrier concentration in the i-th ion-doped well region is greater than that in the (i+1)-th ion-doped well region.

[0062] There is a concentration difference in majority carrier concentration between ion-doped well regions, resulting in a band difference in the ion-doped well regions. This gradually reduces the electric field and prevents the maximum reverse voltage from being limited or even burning out the device due to abrupt changes in the electric field.

[0063] In a specific implementation, in the vertical direction, the edge of the edge ring structure 10 and the edge of the metal layer 20 are located on the same plane.

[0064] This results in a gradually weakening electric field distribution at the edge of the metal layer due to the nested ion-doped trap regions, which improves the maximum reverse bias voltage and the reliability of the device.

[0065] Corresponding to an embodiment of a gold semiconductor contact device, the present invention also provides an embodiment of a method for manufacturing a gold semiconductor contact device.

[0066] A method for manufacturing a gold semiconductor contact device, the method comprising steps 301 to 305.

[0067] In step 301, a (m+1)th composite layer is formed on the substrate or the m-th composite layer; wherein the m-th composite layer includes an m-th groove and m material regions, with the m-th material region to the 1st material region arranged linearly in sequence; the (m+1)-th composite layer includes an (m+1)-th groove and m+1 material regions, with the (m+1)-th material region to the 1st material region arranged linearly in sequence. m is a positive integer less than or equal to n.

[0068] In practice, step 301 can be divided into two cases:

[0069] In the first case, when step A is performed for the first time, step 301 includes: forming a first composite layer on the substrate; at this time, step 301 includes steps 301-1a and 301-2a.

[0070] In step 301-1a, a first barrier layer is formed on the substrate. The first barrier layer is formed on the substrate by vapor deposition or sputtering.

[0071] In steps 301-2a, the first barrier layer is formed into the first composite layer by imaging. Imaging includes an etching process.

[0072] In the second case, when step A is not being performed for the first time, step A includes: forming the (m+1)th composite layer on the m-th composite layer. In this case, step 301 includes steps 301-1b and 301-2b.

[0073] In step 301-1b, the (m+1)th barrier layer is formed on the m-th composite layer. The (m+1)th barrier layer is formed on the m-th composite layer by vapor deposition or sputtering.

[0074] In step 301-2b, the upper surface of the (m+1)th barrier layer is removed while the (m+1)th barrier layer on the sidewall of the mth composite layer is retained to form the (m+1)th composite layer.

[0075] In a specific implementation, the upper surface of the (m+1)th barrier layer is removed by maskless etching while retaining the (m+1)th barrier layer on the sidewall of the mth composite layer to form the (m+1)th composite layer.

[0076] Repeat step 301 n times to form the nth composite layer; n is an integer greater than 1, and m is a positive integer less than n.

[0077] In step 302, ion implantation is performed on the surface of the j-th composite layer to form the (n-j+1)-th ion-doped well region at the location of the j-th groove in the substrate. j is a positive integer less than or equal to n.

[0078] Since ion implantation is performed once on the surface of each composite layer, the first ion-doped well region undergoes n ion implantations, the first ion-doped well region undergoes n-1 ion implantations, and so on, with the nth ion-doped well region undergoing 1 ion implantation. As a result, the majority carrier concentration of the i-th ion-doped well region is greater than that of the (i+1)-th ion-doped well region.

[0079] In step 303, the j-th material region in the j-th composite layer is removed to form the (j-1)-th composite layer; or the first composite layer is removed to expose the substrate.

[0080] Step 303 has two possible scenarios:

[0081] In the first case, when step C is not being performed for the last time, step C includes: removing the j-th material region in the j-th composite layer to form the (j-1)-th composite layer.

[0082] In practice, the j-th material region in the j-th composite layer is removed by maskless etching to form the j-1-th composite layer.

[0083] In the second case, when step C is performed for the last time, step C includes: removing the first composite layer to expose the substrate.

[0084] In practice, the first composite layer is removed by maskless etching to expose the substrate.

[0085] Repeat steps 302 and 303 n times to form an edge ring structure; the edge ring structure includes n ion-doped well regions; n is a natural number greater than 1; the i-th ion-doped well region is located in the (i+1)-th ion-doped well region; i is a positive integer less than n.

[0086] In step 304, a metal layer is formed on the upper surface of the substrate; the metal layer substrate exposes the edge ring structure.

[0087] In summary, the entire manufacturing method of gold semiconductor contact devices only uses imaging technology and a mask in step 301-2a, thus saving the manufacturing cost of gold semiconductor contact devices.

[0088] It is important to emphasize that the first barrier layer and the first material region have the same material; the second barrier layer and the second material region have the same material; and so on, with the nth barrier layer and the nth material region having the same material. However, the materials of each material region are different. The materials of each material region include silicon dioxide, silicon nitride, and amorphous carbon (AC).

[0089] The following example, with n=3, provides an embodiment of a manufacturing method for a gold-plated semiconductor contact device, which includes steps 401 to 416.

[0090] In step 401, as Figure 4 As shown, a first barrier layer 30 is formed on the substrate 90.

[0091] In step 402, as Figure 5 As shown, the first barrier layer 30 is formed into the first composite layer 31 by imaging.

[0092] In step 403, as Figure 6 As shown, a second barrier layer 40 is formed on the first composite layer 31.

[0093] In step 404, as Figure 7 As shown, the upper surface of the second barrier layer 40 is removed while the second barrier layer on the sidewall of the first composite layer 31 is retained to form the second composite layer 41.

[0094] In step 408, as Figure 8 As shown, a third barrier layer 50 is formed on the second composite layer 41.

[0095] In step 409, as Figure 9 As shown, the upper surface of the third barrier layer 50 is removed while the third barrier layer on the sidewall of the second composite layer 41 is retained to form the third composite layer 51.

[0096] In step 410, as Figure 10 As shown, ion implantation is performed on the surface of the third composite layer 51 to form the first ion-doped well region 11 at the location of the third groove in the substrate.

[0097] In step 411, as Figure 11 As shown, the third material region in the third composite layer 51 is removed to form the second composite layer 41.

[0098] In step 412, as Figure 12As shown, ion implantation is performed on the surface of the second composite layer 41 to form a second ion-doped well region 12 at the location of the second groove in the substrate.

[0099] In step 413, as Figure 13 As shown, the second material region in the second composite layer 41 is removed to form the first composite layer 31.

[0100] In step 414, as Figure 14 As shown, ion implantation is performed on the surface of the first composite layer 31 to form a third ion-doped well region 11 at the location of the first groove in the substrate.

[0101] In step 415, as Figure 15 As shown, the first composite layer 31 is removed to expose the substrate 90.

[0102] In step 416, as Figure 16 As shown, a metal layer 20 is formed on the upper surface of the substrate 90; the metal layer 20 covers the substrate 90 and exposes the edge ring structure 10.

[0103] This invention includes a substrate, an edge ring structure, and a metal layer. The edge ring structure is located within the substrate. The metal layer covers the substrate and exposes the edge ring structure. The edge ring structure comprises n ion-doped well regions, where n is a natural number greater than 1. The i-th ion-doped well region is located within the (i+1)-th ion-doped well region, where i is a positive integer less than n. Because the metal layer covers the substrate and exposes the edge ring structure, and because the edge ring structure comprises n ion-doped well regions, with the i-th ion-doped well region located within the (i+1)-th ion-doped well region, the edge of the metal layer forms a gradually weakening electric field distribution due to the nested ion-doped well regions, thereby improving the maximum reverse bias voltage and the reliability of the device.

[0104] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0105] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for manufacturing a gold semiconductor contact device, characterized in that, The manufacturing method includes: Step A: Form the (m+1)th composite layer on the substrate or the mth composite layer; wherein the mth composite layer includes the mth groove and m material regions, and the mth material region to the 1st material region are arranged linearly in sequence; the (m+1)th composite layer includes the (m+1)th groove and m+1 material regions, and the (m+1)th material region to the 1st material region are arranged linearly in sequence; m is a positive integer less than or equal to n; Repeat step A n times to form the nth composite layer; n is an integer greater than 1. Step B: Ion implantation is performed on the surface of the j-th composite layer to form the (n-j+1)-th ion-doped well region at the location of the j-th groove in the substrate; j is a positive integer less than or equal to n; Step C: Remove the j-th material region in the j-th composite layer to form the (j-1)-th composite layer; or remove the first composite layer to expose the substrate; Repeat steps B and C n times to form an edge ring structure; the edge ring structure includes n ion-doped well regions; n is a natural number greater than 1; the i-th ion-doped well region is located in the (i+1)-th ion-doped well region; i is a positive integer less than n; Step D: A metal layer is formed on the upper surface of the substrate; the metal layer covers the substrate and exposes the edge ring structure.

2. The method for manufacturing the gold semiconductor contact device according to claim 1, characterized in that, When step A is performed for the first time, step A includes: forming a first composite layer on the substrate; When step A is not performed for the first time, step A includes: forming a (m+1)th composite layer on the mth composite layer.

3. The method for manufacturing a gold semiconductor contact device according to claim 2, characterized in that, The formation of the first composite layer on the substrate includes: A first barrier layer is formed on the substrate; The first barrier layer is formed into the first composite layer by imaging; The formation of the (m+1)th composite layer on the mth composite layer includes: The (m+1)th barrier layer is formed on the mth composite layer; Remove the upper surface of the (m+1)th barrier layer and retain the (m+1)th barrier layer on the sidewall of the mth composite layer to form the (m+1)th composite layer.

4. The method for manufacturing the gold semiconductor contact device according to claim 1, characterized in that, When step C is performed for the last time, step C includes: removing the first composite layer to expose the substrate; When step C is not performed for the last time, step C includes: removing the j-th material region in the j-th composite layer to form the (j-1)-th composite layer.

5. The method for manufacturing a gold semiconductor contact device according to claim 1, characterized in that, The materials in each material area are different.

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