Visual-based wafer notch position measurement

Abstract

The present invention relates to visual based wafer notch position measurement. A wafer alignment system includes an image capture device that captures an image of a wafer positioned on a pedestal. An image analysis module analyzes the image to detect an edge of the wafer with a notch formed at the edge of the wafer and calculates a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch. An offset calculation module calculates an angular offset of the wafer based on the first edge position and the second edge position. A system control module controls a transfer of the wafer from the pedestal to a processing unit based on the angular offset.

Description

[0001] This application is a continuation of Chinese Patent Application No. 201610613778.9, filed on July 29, 2016, entitled "Position Measurement of Wafer Notch Based on Vision", with the applicant "Lam Research Corporation".

[0002] Cross Reference to Related Applications

[0003] This application is related to U.S. Patent Application No. 14 / 813,895, Attorney Docket No. 3645-1US, filed on July 30, 2015. The entire disclosure of the above-referenced application is incorporated herein by reference. TECHNICAL FIELD

[0004] The present invention relates to substrate processing systems, and more particularly, to systems and methods for positioning semiconductor wafers in substrate processing systems. BACKGROUND

[0005] The purpose of the background provided herein is to present in general the context of the disclosure. The work of the inventors, to the extent it is described in this background section and in some aspects of the description, neither constitutes an admission that the work is prior art merely by its inclusion in the section, that it is entirely combined with any other passage, or that it alone, or in combination with other passages, teaches or discloses insights, concepts, ideas, or methodologies.

[0006] Substrate processing systems can be used to perform etching and / or other processing of substrates, such as semiconductor wafers. Exemplary processes that can be performed on substrates include, but are not limited to, plasma enhanced chemical vapor deposition (PECVD) processes, chemical enhanced plasma vapor deposition (CEPVD) processes, physical sputter vapor deposition (PVD) processes, ion implantation processes, and / or other etching (e.g., chemical etching, plasma etching, reactive ion etching, etc.), deposition, and cleaning processes. Substrates can be disposed on wafer processing pedestals, such as pedestals in a processing chamber of a substrate processing system. For example only, during etching, a gas mixture including one or more precursors is introduced into the processing chamber, and a plasma is excited to etch the substrate.

[0007] A load lock (e.g., an inbound load lock or an outbound load lock) or other transfer tool can be used to transfer a semiconductor wafer from an atmospheric environment to a vacuum environment (i.e., from outside a processing chamber to inside a processing chamber), and vice versa. The load lock itself can include a vacuum chamber containing a pedestal. The wafer is disposed on the pedestal (and transferred to and from the pedestal). For example, the wafer can be transferred from the pedestal to a plating processing unit or other processing unit of a processing chamber in a substrate processing system for deposition, etching, etc. The pedestal lifts the wafer onto an end effector of a robot (e.g., a robot) and away from the robot, which is used to transfer the wafer between the load lock and the processing unit. SUMMARY

[0008] A wafer alignment system includes an image capture device that captures an image of a wafer positioned on a pedestal. An image analysis module analyzes the image to detect an edge of the wafer and a notch formed at the edge of the wafer and computes a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch. An offset computation module computes an angular offset of the wafer based on the first edge position and the second edge position. A system control module controls a transfer of the wafer from the pedestal to a processing unit based on the angular offset.

[0009] A wafer alignment method includes capturing an image of a wafer positioned on a pedestal, analyzing the image to detect an edge of the wafer and a notch formed at the edge of the wafer, computing a first and a second edge position corresponding to the edge of the wafer based on a position of the notch, computing an angular offset of the wafer based on the first position and the second edge position, and controlling a transfer of the wafer from the pedestal to a processing unit based on the angular offset.

[0010] In particular, some aspects of the present application can be set out as follows:

[0011] 1. A wafer alignment system comprising:

[0012] an image capture device that captures an image of a wafer positioned on a pedestal;

[0013] an image analysis module that analyzes the image to detect an edge of the wafer and a notch formed at the edge of the wafer and computes a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch;

[0014] an offset computation module that computes an angular offset of the wafer based on the first edge position and the second edge position; and

[0015] a system control module that controls a transfer of the wafer from the pedestal to a processing unit based on the angular offset.

[0016] 2. The wafer alignment system of clause 1, wherein the first edge position and the second edge position are a predetermined distance from the position of the notch.

[0017] 3. The wafer alignment system of clause 1, wherein, to compute the angular offset, the offset computation module compares the first edge position and the second edge position to a third edge position and a fourth edge position.

[0018] 4. The wafer alignment system of clause 3, wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

[0019] 5. The wafer alignment system of clause 3, wherein the third edge position and the fourth edge position correspond to edges of a test wafer.

[0020] 6. The wafer alignment system of clause 5, wherein the image analysis module calculates the third edge position and the fourth edge position using an image taken when the test wafer is disposed at a reference position on the pedestal.

[0021] 7. The wafer alignment system of clause 5, wherein the first edge position, the second edge position, the third edge position, and the fourth edge position each correspond to a coordinate within a field of view of the image capture device.

[0022] 8. The wafer alignment system of clause 5, further comprising a light source disposed on a side of the wafer opposite the image capture device, wherein the light source is arranged to project light through the wafer toward the image capture device.

[0023] 9. The wafer alignment system of clause 8, wherein the light source is arranged to illuminate a field of view of the image capture device.

[0024] 10. A wafer alignment method comprising:

[0025] capturing an image of a wafer positioned on a pedestal;

[0026] analyzing the image to detect an edge of the wafer and a notch formed at the edge of the wafer;

[0027] calculating a first edge position and a second edge position corresponding to the edge of the wafer based on a position of the notch;

[0028] calculating an angular offset of the wafer based on the first edge position and the second edge position; and

[0029] controlling a transfer of the wafer from the pedestal to a processing unit based on the angular offset.

[0030] 12. The wafer alignment method of clause 11, wherein the first edge position and the second edge position are a predetermined distance from the position of the notch.

[0031] 13. The wafer alignment method of clause 11, wherein calculating the angular offset comprises comparing the first edge position and the second edge position to a third edge position and a fourth edge position.

[0032] 14. The wafer alignment method of clause 13, wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

[0033] 15. The wafer alignment method of clause 13, wherein the third edge position and the fourth edge position correspond to edges of a test wafer.

[0034] 16. The wafer alignment method of clause 15, further comprising calculating the third edge position and the fourth edge position using an image taken when the test wafer is disposed at a reference position on the pedestal.

[0035] 17. The wafer alignment method of clause 15, wherein the first edge position, the second edge position, the third edge position, and the fourth edge position each correspond to a coordinate within a field of view of the image capture device.

[0036] 18. The wafer alignment method of clause 15, further comprising projecting light through the wafer toward the image capture device using a light source disposed on an opposite side of the wafer from the image capture device.

[0037] 19. The wafer alignment method of clause 18, wherein the light source is disposed to illuminate a field of view of the image capture device.

[0038] 20. The wafer alignment method of clause 11, further comprising adjusting a load position of the processing unit based on the angular offset prior to the wafer being transferred to the processing unit.

[0039] Further scope of the applicability of the present application will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the application. BRIEF DESCRIPTION OF DRAWINGS

[0040] The present application will be more fully understood from the detailed description and the drawings, in which:

[0041] Figure 1 is a functional block diagram of an exemplary substrate processing system in accordance with the principles of the present application;

[0042] Figure 2A is a functional block diagram of an example of a substrate processing tool in accordance with the principles of the present application;

[0043] Figure 2B is an exemplary load lock;

[0044] Figure 3A is an exemplary load lock and camera according to the principles of the present invention;

[0045] Figure 3B is another view of an exemplary load lock and camera according to the principles of the present invention;

[0046] Figure 3C is an exemplary image of a wafer captured according to the principles of the present invention;

[0047] Figure 4 shows steps of an exemplary wafer alignment method according to the principles of the present invention;

[0048] Figure 5 is a functional block diagram of an exemplary wafer alignment system according to the principles of the present invention;

[0049] Figure 6A is an exemplary calibration image of a test wafer according to the principles of the present invention;

[0050] Figure 6B is an exemplary image of a misaligned wafer according to the principles of the present invention; and

[0051] Figure 6C is an exemplary comparison of an image of a misaligned wafer to a calibration image according to the principles of the present invention;

[0052] In these drawings, reference numerals can be repeated between the figures for like and / or similar elements. DETAILED DESCRIPTION

[0053] A semiconductor wafer (e.g., a 300 mm wafer) is positioned on a susceptor of a load lock for transfer into and out of a processing chamber. The wafer is aligned on the susceptor so that it can be accurately captured and / or transferred using a robot or other tool. The alignment of the wafer is accomplished using a notch formed in the outer edge of the wafer. As the wafer is rotated (e.g., using a rotary chuck that includes the susceptor), various types of wafer aligners can be used to detect the position of the notch relative to the susceptor. For example, as the wafer is slowly rotated using the chuck, a sensor can detect the notch. The notch position and wafer offset are calculated based on the detected notch and provided to the robot.

[0054] In accordance with the principles of the present application, a system and method of wafer alignment provides an image capture device (e.g., a camera) to capture an image of a fixed wafer on a pedestal. In particular, the camera captures an image of an edge of the wafer that includes a notch. An image analysis module analyzes the captured image to locate a position of the notch and an edge position of the wafer relative to the notch. An offset calculation module calculates an angular offset of the wafer relative to a desired position using the position of the notch and the edge position of the wafer. For example, the desired position can correspond to a calibrated reference position.

[0055] Referring now to the drawings Figure 1 One example of a substrate processing system 100 for etching using RF plasma is shown. The substrate processing system 100 includes a process chamber 102 that encloses other components of the substrate processing chamber 102 and contains an RF plasma. The substrate processing chamber 102 includes an upper electrode 104 and a pedestal 106 that includes a lower electrode 107. An edge-coupled ring 103 is supported by the pedestal 106 and is disposed around a substrate 108. One or more actuators 105 can be used to move the edge-coupled ring 103. During operation, the substrate 108 is disposed on the pedestal 106 between the upper electrode 104 and the lower electrode 107.

[0056] By way of example only, the upper electrode 104 can include a showerhead 109 that introduces and distributes a process gas. The showerhead 109 can include a stem portion that includes one end that is connected to a top surface of the process chamber. A base portion is generally cylindrical and extends radially outward from another end of the stem portion at a location that is spaced apart from the top surface of the process chamber. A surface or faceplate of the base portion of the showerhead that faces the substrate includes a plurality of holes through which the process gas or a purge gas flows. Alternatively, the upper electrode 104 can include a conductive plate and the process gas can be introduced in another manner. The lower electrode 107 can be disposed in a non-conductive pedestal. Alternatively, the pedestal 106 can include an electrostatic chuck that includes a conductive plate that acts as the lower electrode 107.

[0057] An RF generation system 110 generates and outputs an RF voltage to one of the upper electrode 104 and the lower electrode 107. The other of the upper electrode 104 and the lower electrode 107 can be direct current grounded, alternating current grounded, or floating. By way of example only, the RF generation system 110 can include an RF voltage generator that generates an RF voltage that is supplied to the upper electrode 104 and the lower electrode 107 by a matching and distribution network 112. In other examples, the plasma can be inductively or remotely generated.

[0058] The gas delivery system 130 includes one or more gas sources 132-1, 132-2,..., and 132-N (collectively, gas sources 132), where N is an integer greater than zero. The gas sources supply one or more precursors and mixtures thereof. The gas sources can also provide a purge gas. Vaporized precursors can also be used. The gas sources 132 are connected to a manifold 140 through valves 134-1, 134-2,..., and 134-N (collectively, valves 134) and mass flow controllers 136-1, 136-2,..., and 136-N (collectively, mass flow controllers 136). The output of the manifold 140 is fed to the processing chamber 102. By way of example only, the output of the manifold 140 is fed to the showerhead 109.

[0059] A heater 142 can be connected to a heater coil (not shown) disposed in the susceptor 106. The heater 142 can be used to control the temperature of the susceptor 106 and the substrate 108. A valve 150 and a pump 152 can be used to evacuate reactants from the processing chamber 102. A controller 160 can be used to control the components of the substrate processing system 100. The controller 160 can also be used to control the actuator 105 to adjust the position of one or more portions of the edge coupling ring 103.

[0060] A robot 170 can be used to transport substrates onto the susceptor 106 and away from the susceptor 106. For example, the robot 170 can transfer substrates between the susceptor 106 and a load lock 172 in accordance with the principles of the present application.

[0061] Reference is now made to Figure 2A , a non-limiting exemplary substrate processing tool 200 (e.g., as provided within the substrate processing system 100) includes a transfer handling chamber 220 and a plurality of reactors, each having one or more substrate processing chambers. Substrates 225 enter the substrate processing tool 200 from a cassette and / or box 223, such as from a front opening unified pod (FOUP). A robot 224 includes one or more end effectors to handle the substrates 225. The pressure of the transfer processing chamber 220 can be at atmospheric pressure. Alternatively, the transfer handling chamber 220 can be at vacuum pressure (with ports that act as slot valves).

[0062] The robot 224 moves the substrate 225 from the box and / or cassette to the load lock 230. For example, the substrate 225 enters the load lock 230 through the port 232 (or an isolation valve) and is placed on a load lock pedestal 233. The port 232 to the transfer handling chamber 220 is closed and the load lock 230 is pumped down to the appropriate pressure for transfer. Then, the port 234 is opened and another robot 236 (also having one or more end effectors) of the process handling chamber 235 places the substrate through one of the ports 237-1, 237-2, 237-3 (collectively, ports 237) corresponding to a selected reactor 240-1, 240-2, and 240-3 (collectively, reactors 240). Although the load lock 230 is shown as having multiple pedestals and associated ports, in some embodiments, the load lock 230 can include only a single pedestal and corresponding port. By way of example only, another exemplary load lock configuration is shown in Figure 2B

[0063] A substrate indexing mechanism 242 can be used to further position the substrate relative to the substrate processing chambers. In some examples, the indexing mechanism 242 includes a turntable 244 and a thermal plate 246.

[0064] In some examples, at least one of the processing chambers or stations of the reactors 240 is capable of performing a semiconductor processing operation, such as material deposition or etching, sequentially or simultaneously with the other stations. In some examples, at least one or more of the stations can perform a radio frequency based semiconductor processing operation.

[0065] The substrate is moved from one station to the next in the reactor 240 using the substrate indexing mechanism 242. By way of example only, depending on the particular implementation of the substrate processing tool 200, one or more of the stations of the reactor 240 can perform RF plasma deposition, etching, or other process steps. During use, a substrate is moved into one or more of the reactors 240, processed, and then returned. As can be appreciated, reducing the handling time for each substrate will improve production efficiency and throughput.

[0066] In accordance with the principles of the present application, the robots 224 and 236 transfer substrates to and from the load lock 230 under the direction of a controller (e.g., the controller 160 as shown in Figure 1 In particular, each substrate (i.e., wafer) includes a notch to facilitate determining the position (e.g., alignment) of the wafer relative to the pedestal 233 of the load lock 230. Accurate determination of the wafer position in turn facilitates accurate capture, retrieval, and transfer of the wafer (e.g., capture of the wafer by the robot 236 for transfer from the load lock 230 to the reactor 240).

[0067] Reference is now made to Figure 3A 3B ​​and 3C, exemplary load lock 300 and camera 304 are arranged to detect the position of wafer 308, in accordance with the principles of the present application. Although the structure of load lock 300 corresponds to that of the exemplary load lock shown in Figure 2B FIG. 3A, load lock 300 can have a structure similar to that of load lock 230 of Figure 2A FIG. 2B or any other structure. Wafer 308 is disposed on a pedestal 312 (e.g., a cold pedestal) within load lock 300 (e.g., as placed by a robot or other suitable tool). Camera 304 is positioned (e.g., with the lens of upward-facing camera 304) to capture an image of a portion of wafer 308. For example, camera 304 captures an image of an edge 314 of wafer 308 (e.g., through an aperture including a quartz or other type of window 316). The edge of wafer 308 can be backlit (e.g., using an LED or other light source 320 that projects light through the edge of wafer 308 and downward toward camera 304 through another window 324) to illuminate the field of view 328 of camera 304, as shown in Figure 3C

[0068] As shown in Figure 3C FIG. 3B, exemplary image 332 captured by camera 304 includes edge 314 of wafer 308 within field of view 328 of camera 304. Camera 304 (and / or controller 160 as shown in Figure 1 FIG. 3C, or other device or module as described in more detail below) analyzes captured image 332 to locate edge 314 of wafer 308 and notch 336 formed on edge 314 of wafer 308. For example, camera 304 can be configured to identify and locate notch 336 by detecting the curvature (i.e., notch profile) of notch 336.

[0069] ​The field of view 328 of the camera 304 can be fixed (i.e., constant) with respect to a coordinate system. For example, the coordinate system can correspond to a plurality of X, Y positions within the field of view 328, with a 0, 0 position 340 corresponding to a center point of the field of view 328. The camera 304 positions the target locator box 344 according to the detected position of the notch 336. For example, the target locator box 344 can be calibrated to lock in at the X, Y position centered on the detected notch 336 (e.g., according to the detected notch profile). The edge locator boxes 348 and 352 are positioned at XI, Yl and X2, Y2, respectively, relative to the X, Y position of the target locator box 344. In other words, based on the X, Y position of the target locator box 344 and the known curvature of the wafer 308 (e.g., based on the known diameter of the wafer 308), the positions XI, Yl and X2, Y2 are positioned along the edge 314 of the wafer 308 (in opposite directions) at a fixed distance from the X, Y position of the target locator box 344. By way of example only, the edge locator boxes 348 and 352 can be positioned as far away from the target locator box 344 as possible while still being within the field of view 328 to maximize accuracy.

[0070] For example, during initial calibration using a test wafer that is optimally (e.g., within a desired tolerance) positioned, the target locator box 344 can be drawn around the notch of the test wafer. In other words, the test wafer is positioned such that the position of the notch of the test wafer corresponds as closely as possible to the 0, 0 position of the field of view 328 of the camera 304. In this manner, during calibration, the X, Y position of the target locator box 344 directly corresponds to the position of the notch of the test wafer. When the target locator box 344 is positioned accordingly, the X3, Y3 and X4, Y4 positions of the edge locator boxes 348 and 352 are selected to be a fixed distance along the edge of the test wafer from the X, Y position and within the field of view 328 of the camera 304. For example, for the test wafer, X3, Y3 can correspond to (X-A), (Y+B), and X4, Y4 can correspond to (X+C), (Y-D).

[0071] With the target positioner frame 344 applied to the notch 336 of the wafer 308, the camera 304 positions the edge positioner frames 348 and 352 at the same distance from the target positioner frame 344 as the positions (X-A), (Y+B) and (X+C), (Y-D) from the target positioner frame 344 for the test wafer. However, the positions of the edge positioner frames 348 and 352 can be adjusted to position along the edge 314 of the wafer 308. In other words, misalignment (e.g., lateral shift and / or angular shift) of the wafer 308 can cause the edge 314 of the wafer 308 to follow a different path than the edge of the test wafer. Thus, when the edge positioner frames 348 and 352 are positioned at the same distance from the target positioner frame 344, the actual corresponding X1, Y1 and X2, Y2 positions of the wafer 308 can be shifted relative to the X3, Y3 and X4, Y4 positions of the test wafer.

[0072] The X1, Y1 and X2, Y2 positions of the wafer 308 can be calculated based on the known distance from the X, Y positions detected by the camera 304 and the edge 314 of the wafer 308. The camera 304 compares the X1, Y1 and X2, Y2 positions to the X3, Y3 and X4, Y4 positions, respectively, and thus calculates the lateral shift and angular shift of the wafer 308 compared to the test wafer. Correction values are calculated based on the lateral shift and angular shift and used to adjust the position of the wafer 308 accordingly.

[0073] Referring now to Figure 4 , an exemplary wafer alignment method 400 in accordance with the principles of the present application begins at 404. The method 400 is implemented using various components of the Figures 1-3C as described below. At 408, a wafer is positioned on a load lock (e.g., the load lock 300 of the Figure 3A ). The wafer can be transferred to the load lock using the robot 224 under control of the controller 160. For example, the wafer is positioned on a cooled pedestal in an elevated (upward) position. At 412, a controller or control module (e.g., the controller 160) provides instructions to a camera (e.g., the camera 304 of the Figure 3B ) to take measurements of the position of the wafer. For example, the controller 160 can implement system software or firmware that generates and sends a message to the camera 304. By way of example only, the message can correspond to an Ethernet message.

[0074] At 416, the camera 304 captures an image of the wafer (e.g., the edge of the wafer including the notch), as described above Figure 3CThe camera 304 processes and analyzes the image to detect and locate the notch and the edge of the wafer, including implementing the target locator box 344 and the edge locator boxes 348 and 352, at 420. The camera 304 calculates the angular and / or lateral offsets of the wafer (e.g., based on the locations of the target locator box 344 and the edge locator boxes 348 and 352), at 424. The camera 304 provides the calculated angular and / or lateral offsets to the controller 160 (e.g., via Ethernet messages), at 428.

[0075] While described as being performed by the camera 304, one or more of 420, 424, and 428 can be performed by the controller 160 or other component. For example, the camera 304 can capture the image, but then provide the image to the controller 160 for analysis and calculation of the offsets, or the camera can capture and analyze the image and provide the locations of the target locator box 344 and the edge locator boxes 348 and 352 to the controller 160 for calculation of the offsets.

[0076] At 432, a plating robot (e.g., the robot 236) retrieves the wafer from the load lock 300. For example, the cooled pedestal of the load lock 300 can be lowered prior to the robot 236 retrieving the wafer. The loading position of the processing unit (e.g., a plating unit of the destination chamber of the wafer) is adjusted based on the calculated angular and / or lateral offsets, at 436. For example, the controller 160 controls (e.g., implements system software / firmware) the loading position of the processing unit to compensate for the expected angular offsets calculated by the camera 304 or the controller 160. The robot 236 transports the wafer to the processing unit, at 440. The method 400 ends at 444.

[0077] Reference is now made to Figure 5 FIG. 5, which shows a simplified exemplary wafer alignment system 500, in accordance with the principles of the application. The wafer alignment system includes a camera 504 and a controller 508 (corresponding to the camera 304 and the controller 160, by way of example only). The camera 504 includes an image capture module 512 and optionally an image analysis module 516 and an offset calculation module 520. The image capture module 512 controls the capture of an image of a wafer (e.g., the edge and notch of the wafer), as described in Figures 1-4 For example, when a wafer is placed on a load lock, the image capture module 512 responds to a command from the controller 508 to initiate the capture of an image of the wafer.

[0078] The image capture module 512 provides the captured image to an image analysis module 516. As shown, the image analysis module 516 can be located in the camera 504, the controller 508, or another controller or module of the system 500. The image analysis module 516 analyzes the image to detect the edge and notch of the wafer and calculates the positions of the target positioner frame 344 and the edge positioner frames 348 and 352. The image analysis module 516 provides the calculated positions to an offset calculation module 520, which uses the calculated positions and the calculated reference positions (i.e., the calibration positions) to calculate the angular offset (and / or lateral offset). As shown, the offset calculation module 520 can be located in the camera 504, the controller 508, or another controller or module of the system 500.

[0079] The calculated offset (or offsets) are provided to a system control module 524 of the controller 508. While shown as a single module, the system control module 524 can represent one or more modules related to the control of the substrate processing system, such as the control of a plating robot, the control of a processing cell load position, etc. For the purposes of this embodiment, the system control module 524 controls a plating robot to retrieve the wafer from the load lock, adjust the load position of the processing cell (i.e., the rotational orientation) according to the calculated offset, and control the robot to place the wafer on the processing cell. In implementations, additional aligners or other components (e.g., of a front end module) can be controlled to align the notch prior to the wafer being placed in the load lock.

[0080] Referring now to Figure 6A , 6B , and 6C, exemplary calibration images of a test wafer, exemplary images of a misaligned wafer, and an exemplary comparison of the calibration image and the image of the misaligned wafer are shown, respectively. Figure 6A A test wafer 600 having a notch 604 is shown. The notch 604 is aligned with an axis 608 (e.g., relative to a center point of the test wafer 600, which for a calibrated test wafer can correspond to a center point 612 of a susceptor). The image includes calculated positions A and B (i.e., calibration positions) that correspond to, for example, X2, Y2 and X3, Y3, as described in the above embodiments.

[0081] In contrast, an image of a wafer 620 as shown in Figure 6B has a notch 624 aligned with an axis 628 (e.g., relative to a center point 632 of the wafer 620). The wafer 620 is not properly aligned on a susceptor, and thus the axis 628 is rotated relative to the axis 608 of the test wafer 600. The image includes calculated positions C and D that correspond to, for example, X1, Y1 and X2, Y2, as described in the above embodiments.

[0082] Figure 6C An image of wafer 620 overlaid on the image of calibrated test wafer 600 is shown, showing an angular offset a3 between axes 608 and 628. As described above in Figures 1-5 The system and method of the present application, based on the comparison between the calibrated positions A and B of test wafer 600 and the calculated positions C and D of wafer 620, calculates the angular offset a3.

[0083] The foregoing description is merely illustrative in nature and is not intended to limit the disclosure, its application or uses in any way. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical A OR B OR C using the inclusive OR (OR), and it should be interpreted in the alternative (A or B or C), but not both. It will be understood that one or more steps within a method, or methods, can be executed in different order (or concurrently) and that some steps may

[0084] In this application, including the definitions below, the term "controller" can be replaced with the term "circuit." The term "controller" can refer to a device, part of a device, or includes a device that is: an Application Specific Integrated Circuit (ASIC); a digital, analog, or mixed analog / digital discrete circuit; a digital, analog, or mixed analog / digital integrated circuit; a combinational logic circuit; a field programmable gate array (FPGA); a processor circuit (shared, dedicated, or group) that executes code; a memory circuit (shared, dedicated, or group) that stores code for execution by the processor circuit; other suitable hardware components that provide the described functionality; or a combination of some or all of the above, such as in a system-on-chip.

[0085] A controller can include one or more interface circuits. In some examples, the interface circuits can include wired or wireless interfaces that are connected to a local area network (LAN), the Internet, a wide area network (WAN), or combinations thereof. The functionality of any given controller of the present application can be divided among multiple controllers connected via interface circuits. For example, a plurality of controllers can allow load balancing. In a further example, a server (also referred to as a remote, or cloud) controller can perform certain functions on behalf of a client controller.

[0086] The term code, as used in this document, can include software, firmware, and / or microcode, and can refer to programs, routines, functions, classes, data structures, and / or objects. The term shared processor circuitry includes a single processor circuitry executing code from multiple controllers. The term combined processor circuitry includes a processor circuitry executing some or all code from one or more controllers in combination with another processor circuitry. References to multiple processor circuitries include multiple processor circuitries on discrete dies, multiple processor circuitries on a single die, multiple cores of a single processor circuitry, multiple threads of a single processor circuitry, or a combination of the preceding. The term shared memory circuitry includes a single memory circuitry storing code from multiple controllers. The term combined memory circuitry includes a memory circuitry storing some or all code from one or more controllers in combination with another memory circuitry.

[0087] The term memory circuitry is a subset of the term computer readable medium. The term computer readable medium, as used in this document, does not encompass transitory

[0088] The apparatus and methods described in this application can be partially or entirely implemented by a special purpose computer created by configuring a general purpose computer to execute one or more particular functions embodied in the computer program. The functions described above and the flowchart elements can be implemented as software codes that are stored in a non-transitory, tangible computer-readable medium, which is read and executed by a processor.

[0089] The computer program can include a basic input / output system (BIOS), device drivers, one or more operating systems, and / or application software. The computer program can also include or rely on storage of data by a data storage medium such as a hard drive, a flash drive, a volatile memory, a non-volatile memory, a cache, etc. The computer program can include: a software application, an applet, an app, or other computer program from which a user can interact with the computer.

[0090] The computer programs can include: (i) a description text to be parsed, such as HTML (HyperText Markup Language) or XML (Extensible Markup Language), (ii) assembly code, (iii) object code generated by a compiler from source code, (iv) source code for execution by an interpreter, (v) source code for editing and execution by an immediate compiler, and so on. By way of example only, the source code can be written using the syntax of a language chosen from a group of languages including: C, C++, C#, Objective-C, Haskell, Go, SQL, R, Lisp, Java®, Visual Basic®, Visual C++®, Fortran, Perl, Pascal, Curl, OCaml, HTML5, Ada, ASP (Active Server Pages), PHP, Scala, Eiffel, Smalltalk, Erlang, Ruby, Flash®, and Fortran, Perl, Pascal, Curl, OCaml, HTML5, Ada, ASP (Active Server Pages), PHP, Scala, Eiffel, Smalltalk, Erlang, Ruby, Visual Lua, and

[0091] The elements in the claims are not intended to recite means-plus-function elements covered by 35 U.S.C. § 112(f) unless the phrase "means for" is expressly recited in the claim.

[0092] In some implementations, a controller is part of a system, which can be part of the above-described examples. Such systems can include semiconductor processing equipment, including one or more of a processing tool, chamber, a platform for processing, and / or a specific processing assembly (wafer pedestal, gas flow system, etc.). These systems can be integrated with electronics for controlling the operations of the systems before, during, and after processing of a semiconductor wafer or substrate. The electronics can be referred to as the “controller,” which can control various elements or subparts of the system or systems. The controller, depending on the processing requirements and / or types of systems, can be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., of heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfer into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0093] Broadly speaking, the controller can be defined as an electronic device or set of devices that receives instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like using various integrated circuits, logic, memory, and / or software. The integrated circuits can include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be transmitted to the controller in various forms, including as one or more sets of instructions in various separate packages (or program files) that define operations for performing a particular process on or for a semiconductor wafer or system. In some embodiments, the operation parameters can be part of a recipe defined by process engineers to perform one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0094] In some implementations, the controller can be part of or coupled to a computer that is integrated with, coupled to the system, or otherwise in communication with the system, or a combination thereof. For example, the controller can be in the "cloud" or all or a part of a fab host computer system, which can allow for remote access of wafer processing. Computer can enable remote access to the system to monitor current process operations, inspect a history of past manufacturing operations, inspect trends or performance metrics from a plurality of manufacturing operations, alter parameters of current processing, set processing steps to follow a current process, or begin a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to a system over a network, which can include a local network or the Internet. The remote computer can include a user interface that enables a user to input or retrieve data and / or to set parameters that are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data that specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters can be specific to a type of process to be performed and a type of tool that the controller is configured to interface with or control.

[0095] Without limitation, example systems can include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that can be associated in a cluster tool or used in fabrication and / or manufacturing semiconductors.

[0096] As described above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a host computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

Claims

1. A wafer alignment system comprising: an image capture module configured to capture an image of a wafer positioned on a support surface; an image analysis module configured to (i) analyze the captured image to identify an edge of the wafer and a notch formed in the wafer, and (ii) calculate a first edge position and a second edge position along the edge of the wafer based on a location of the notch and a curvature of the wafer, wherein the first edge position and the second edge position are positioned at a predetermined distance along the edge of the wafer in opposite directions from the location of the notch; an offset calculation module configured to calculate an angular offset of the wafer based on at least one of the first edge position and the second edge position; and a system control module configured to adjust a rotation direction of the wafer based on the angular offset. To calculate the angular offset, the offset calculation module is configured to compare the first edge position and the second edge position to a third edge position and a fourth edge position.

2. The wafer alignment system of claim 1, wherein, 3. The wafer alignment system of claim 2, wherein the angular offset corresponds to a difference between the first edge position and the third edge position and a difference between the second edge position and the fourth edge position.

4. The wafer alignment system of claim 2, wherein the third edge position and the fourth edge position correspond to an edge of a test wafer.

5. The wafer alignment system of claim 4, wherein the image analysis module calculates the third edge position and the fourth edge position using an image taken when the test wafer is disposed on the support surface at a reference position. Each of the first edge position, the second edge position, the third edge position, and the fourth edge position corresponds to a coordinate within a field of view of the image capture module.

6. The wafer alignment system of claim 4, wherein, The light source is arranged to project light through the wafer toward the image capture module.

7. The wafer alignment system of claim 4, further comprising a light source disposed on a side of the wafer opposite the image capture module, wherein, 8. The wafer alignment system of claim 7, wherein the light source is arranged to illuminate a field of view of the image capture module.

9. The wafer alignment system of claim 1, wherein the system control module is configured to adjust a load position of a processing unit based on the angular offset and control transfer of the wafer to the processing unit.

10. A wafer alignment method comprising: capturing an image of a wafer positioned on a support surface; analyzing the captured image to identify an edge of the wafer and a notch formed in the wafer; calculating a first edge position and a second edge position along the edge of the wafer based on a location of the notch and a curvature of the wafer, wherein the first edge position and the second edge position are positioned at a predetermined distance along the edge of the wafer in opposite directions from the location of the notch; calculating an angular offset of the wafer based on at least one of the first edge position and the second edge position; and adjusting a rotation direction of the wafer based on the angular offset. ​ ​ 11. The wafer alignment method of claim 10, wherein, Computing the angular offset includes comparing the first and second edge positions to third and fourth edge positions.

12. The wafer alignment method of claim 11, wherein the angular offset corresponds to a difference between the first and third edge positions and a difference between the second and fourth edge positions.

13. The wafer alignment method of claim 11, wherein the third and fourth edge positions correspond to edges of a test wafer.

14. The wafer alignment method of claim 13, further comprising computing the third and fourth edge positions using an image taken when the test wafer is disposed on the support surface at a reference position.

15. The wafer alignment method of claim 13, wherein, The first, second, third, and fourth edge positions each correspond to a coordinate within a field of view of an image capture module.

16. The wafer alignment method of claim 13, further comprising projecting light through the wafer toward the image capture module using a light source disposed on an opposite side of the wafer from the image capture module.

17. The wafer alignment method of claim 16, wherein the light source is disposed to illuminate a field of view of the image capture module.

18. The wafer alignment method of claim 10, further comprising adjusting a load position of a processing unit based on the angular offset and transferring the wafer to the processing unit.

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