A three-dimensional chip integration structure and a processing method thereof

Abstract

The present invention relates to the field of semiconductor technology, and particularly to a three-dimensional chip integration structure and a processing method thereof. The three-dimensional chip integration structure includes a packaging layer, a first silicon chip, a bonding layer, a second silicon chip, and a heat sink structure that are vertically stacked in sequence from top to bottom; a plurality of through-silicon vias and a plurality of horizontal channels are provided on both the first silicon chip and the second silicon chip; the heat sink structure is composed of microchannels; the through-silicon vias are interconnected with the horizontal channels and the microchannels; low-melting-point metal is filled in the through-silicon vias, the horizontal channels, and the microchannels. The three-dimensional chip integration structure has good heat dissipation performance; the processing method of the three-dimensional chip integration structure is simple and fast.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a three-dimensional chip integration structure and a processing method thereof. Background Art

[0002] With the rapid development of semiconductor technology, the demand for IC performance is constantly increasing, such as enhanced functions, reduced size, lower power consumption and cost. Three-dimensional integration technology is the key technology for microelectronic products to develop towards miniaturization, high performance, high integration, and low cost. Through-Silicon Via (TSV) is a new technology solution for interconnecting stacked chips in three-dimensional integrated circuits.

[0003] However, chip stacking brings a series of new thermal management challenges, such as a multiple increase in power density, uneven chip temperature distribution, and increased thermal stress. The thermal problems of three-dimensional integrated circuits mainly have the following two aspects: ① Multiple active chips are stacked vertically, resulting in a substantial increase in transistor density, thus causing a sharp increase in power density; ② The heat inside the three-dimensional integrated circuit must pass through adjacent chip layers and bonding layers to conduct to the heat sinks or thermal sinks on the upper and lower surface, and the thermal conductivity of the bonding layer material is much smaller than that of silicon and copper [for example, at room temperature, the thermal conductivity of silicon dioxide is 1.4 W / (m·K), which is much smaller than the thermal conductivity of silicon 150 W / (m·K) and copper 401 W / (m·K)], resulting in a substantial decrease in the thermal conduction ability between the upper and lower chips. At the same time, due to the reduction of the chip area, the heat dissipation ability of the three-dimensional integrated circuit drops sharply. Therefore, an efficient heat dissipation technology solution has become a technical bottleneck for further development.

[0004] The main chip enhanced heat dissipation solutions are mainly of two types; one is an external cooling system, such as an inserted heat sink, a bottom microchannel heat sink, etc., but the thickness of the three-dimensional chip will increase accordingly; the other is interlayer cooling, such as setting thermal vias that do not transmit electrical signals but only transfer heat or etching internal microchannels between layers for convective enhanced cooling, but the increase in thermal vias will bring difficulties in layout and planning, and the etching of microchannels increases the manufacturing difficulty and reduces the reliability of the chip. The above methods are all based on passive heat dissipation, that is, achieving heat dissipation by means of external additional means, which goes against the original intention of reducing the chip scale of three-dimensional chips. Thermal analysis of 3D ICs has shown that through-holes between planes can enhance heat dissipation in addition to transmitting signals, providing potential for active heat dissipation of three-dimensional chip structures. Therefore, enhancing the active heat dissipation ability of chips through through-silicon vias is a new thinking direction for facing the severe chip thermal management problem.

[0005] In view of this, the present invention is specifically proposed. Summary of the Invention

[0006] The object of the present invention is to provide a three-dimensional chip integration structure with good heat dissipation performance; another object of the present invention is to provide a processing method for the three-dimensional chip integration structure, which is simple and fast.

[0007] Specifically, the present invention provides the following technical solutions:

[0008] The present invention provides a three-dimensional chip integration structure, including a packaging layer, a first silicon chip, a bonding layer, a second silicon chip, and a heat sink structure, which are vertically stacked in sequence from top to bottom;

[0009] A plurality of through-silicon vias and a plurality of horizontal channels are provided on both the first silicon chip and the second silicon chip; the heat sink structure is composed of microchannels; the through-silicon vias are connected to the horizontal channels and the microchannels;

[0010] Low melting point metal is filled in the through-silicon vias, the horizontal channels, and the microchannels.

[0011] The present invention discovers that by using the above-mentioned through-silicon vias, horizontal channels, and microchannels to realize a three-dimensional structure of chip interconnection in the horizontal and vertical directions, and using low melting point metal as the perfusion medium, it can not only realize electrical connection by its conductivity, but also use its high conductivity to achieve convective heat dissipation to alleviate the high heat flux density of integrated circuits; that is to say, by using the flow characteristics of low melting point metal inside the three-dimensional chip, convective heat transfer is realized in the microchannels to enhance heat dissipation, thereby prolonging the service life of the chip.

[0012] In the present invention, the low melting point metal flows in the connected channels, is collected by the microchannel heat sink, and flows out of the three-dimensional chip.

[0013] As a preference of the above technical solution, insulating layers are deposited on the inner surfaces of the through-silicon vias and the horizontal channels.

[0014] As a preference of the above technical solution, the insulating layer is silicon dioxide.

[0015] As a preference of the above technical solution, the packaging layer, the bonding layer, and the heat sink structure are respectively aligned and bonded with the first silicon chip and the second silicon chip, and are interconnected through channels.

[0016] As a preference of the above technical solution, the low melting point metal is an alloy composed of one or more of gallium, indium, tin, and bismuth.

[0017] For the three-dimensional chip integration structure of the present invention, when the filled low melting point metal is one or more of gallium, indium, tin, and bismuth, the heat dissipation performance is better.

[0018] As a preference of the above technical solution, the width of the microchannel is 100 - 300 μm, and the depth is 100 - 300 μm.

[0019] The present invention also provides a processing method for the above three-dimensional chip integration structure, comprising the following steps:

[0020] (1) Etch a plurality of through-silicon vias and a plurality of horizontal channels on the first silicon chip and the second silicon chip, and deposit an insulating layer on the inner surfaces of the through-silicon vias and the horizontal channels;

[0021] (2) Perform plasma treatment on the lower surface of the encapsulation layer and align and bond it with the upper surface of the first silicon chip; perform plasma treatment on the upper surface of the bonding layer and align and bond it with the lower surface of the first silicon chip; perform plasma treatment on the lower surface of the bonding layer and align and bond it with the upper surface of the second silicon chip; perform plasma treatment on the upper surface of the heat sink structure and align and bond it with the lower surface of the second silicon chip;

[0022] (3) Inject a low-melting-point metal.

[0023] In the above technical solution, the through-silicon vias and the horizontal channels are etched by photolithography or dry etching; the plasma treatment is completed by a plasma processor; the low-melting-point metal is injected by a small electromagnetic pump.

[0024] As a preference of the above technical solution, the insulating layer is silicon dioxide.

[0025] As a preference of the above technical solution, the encapsulation layer, the bonding layer and the heat sink structure are all made of epoxy resin material.

[0026] As a preference of the above technical solution, the low-melting-point metal is one or several of gallium, indium, tin, and bismuth.

[0027] The beneficial effects of the present invention are as follows:

[0028] (1) Higher heat dissipation performance: While the horizontal and vertical channels are interconnected for electrical signals, the flowing low-melting-point metal also takes away the heat inside the chip by convection. In addition, the heat sink structure composed of micro-channels arranged at the bottom of the chip plays a role in enhancing heat dissipation and maintaining the normal operating temperature of the chip.

[0029] (2) Simpler preparation method: First, the chips are interconnected with each other by the low-melting-point metal in the micro-channels; second, there is no need to deposit a dielectric layer and a seed layer in the through-silicon vias and then fill them with a conductive material, and the low-melting-point metal can be directly poured. Description of the Drawings

[0030] Figure 1 It is a schematic diagram of the three-dimensional chip integration structure provided by the present invention;

[0031] Figure 2Schematic diagram of the processing of the three-dimensional chip integration structure provided by the present invention;

[0032] Figure 3 Planar schematic diagram of the first silicon chip of the three-dimensional chip integration structure provided by the present invention;

[0033] Figure 4 Planar schematic diagram of the heat sink structure of the three-dimensional chip integration structure provided by the present invention;

[0034] Figure 5 Flow chart of the fabrication of the three-dimensional chip integration structure provided by the present invention;

[0035] In the figure: 101, through-silicon via; 102, encapsulation layer; 103, first silicon chip; 104, bonding layer; 105, second silicon chip; 106, heat sink structure; 201, horizontal channel on the first silicon chip; 202, microchannel. Detailed implementation manners

[0036] The following embodiments are used to illustrate the present invention, but are not used to limit the scope of the present invention.

[0037] In the embodiments, unless otherwise specified, the test means and equipment used are all conventional means and equipment in the art.

[0038] Embodiment 1

[0039] This embodiment provides a three-dimensional chip integration structure, as Figure 1 , Figure 3 , Figure 4 shown, the three-dimensional chip integration structure includes an encapsulation layer 102, a first silicon chip 103, a bonding layer 104, a second silicon chip 105, and a heat sink structure 106 that are vertically stacked in sequence from top to bottom;

[0040] A plurality of through-silicon vias and a plurality of horizontal channels are provided on both the first silicon chip 103 and the second silicon chip 105; the heat sink structure 106 is composed of microchannels 202; the through-silicon vias are connected to the horizontal channels and the microchannels 202; low-melting-point metal is filled in the through-silicon vias, the horizontal channels, and the microchannels 202;

[0041] Insulating layers are deposited on the inner surfaces of the through-silicon vias and the horizontal channels, and the insulating layers are silicon dioxide;

[0042] The encapsulation layer 102, the bonding layer 104, and the heat sink structure 106 are respectively aligned and bonded to the first silicon chip 103 and the second silicon chip 105, and are interconnected through channels;

[0043] The low-melting-point metal is an alloy composed of one or more of gallium, indium, tin, and bismuth; the width of the microchannel is 100 - 300 μm, and the depth is 100 - 300 μm.

[0044] Example 2

[0045] This embodiment provides a processing method for a three-dimensional chip integration structure, as Figure 2 、 Figure 5 shown, including the following steps:

[0046] (1) Through deep reactive ion etching, a number of silicon vias and a number of horizontal channels are formed on the first silicon chip 103 and the second silicon chip 105, and an insulating layer is deposited on the inner surfaces of the silicon vias and the horizontal channels through an oxidation process. The material of the insulating layer is silicon dioxide;

[0047] (2) An encapsulation layer 102, a bonding layer 104, and a heat sink structure 106 are prepared using an epoxy resin material; the horizontal channels 201 or microchannels 202 on the first silicon chip are designed into a mask through software, and the structure on the mask is formed into the wafer silicon through a photoresist using a soft lithography method, and then the epoxy resin material is formulated and cured into shape;

[0048] (3) The lower surface of the encapsulation layer 102 is subjected to plasma treatment and aligned and bonded to the upper surface of the first silicon chip 103; the upper surface of the bonding layer 104 is subjected to plasma treatment and aligned and bonded to the lower surface of the first silicon chip 103; the lower surface of the bonding layer 104 is subjected to plasma treatment and aligned and bonded to the upper surface of the second silicon chip 105; the upper surface of the heat sink structure 106 is subjected to plasma treatment and aligned and bonded to the lower surface of the second silicon chip 105 to achieve three-dimensional chip vertical stacking;

[0049] (3) Inject a low-melting-point metal using a small electromagnetic pump. The low-melting-point metal is an alloy composed of one or more of gallium, indium, tin, and bismuth.

[0050] Although the present invention has been described in detail above with general descriptions, specific embodiments, and experiments, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the scope of protection required by the present invention.

Claims

1. A three-dimensional chip integration structure, characterized in that, It includes a packaging layer, a first silicon chip, a bonding layer, a second silicon chip, and a heat sink structure that are vertically stacked in sequence from top to bottom; A plurality of through-silicon vias and a plurality of horizontal channels are provided on both the first silicon chip and the second silicon chip; the heat sink structure is composed of microchannels; the through-silicon vias are interconnected with the horizontal channels and the microchannels; A low-melting-point metal is filled in the through-silicon vias, the horizontal channels, and the microchannels; the low-melting-point metal is used as a perfusion medium to achieve electrical connection.

2. The three-dimensional chip integration structure according to claim 1, characterized in that Insulating layers are deposited on the inner surfaces of the through-silicon vias and the horizontal channels.

3. The three-dimensional chip integration structure according to claim 2, wherein The insulating layer is silicon dioxide.

4. The three-dimensional chip integration structure according to any one of claims 1 to 3, characterized in that, The packaging layer, the bonding layer, and the heat sink structure are respectively aligned and bonded with the first silicon chip and the second silicon chip, and are interconnected through channels.

5. The three-dimensional chip integration structure according to claim 1, wherein, The low-melting-point metal is one or more of gallium, indium, tin, and bismuth.

6. The three-dimensional chip integration structure according to claim 1, characterized in that, The width of the microchannels is 100 - 300 μm, and the depth is 100 - 300 μm.

7. The processing method of the three-dimensional chip integration structure according to any one of claims 1 to 6, characterized in that, It includes the following steps: (1) Etch a plurality of through-silicon vias and a plurality of horizontal channels on the first silicon chip and the second silicon chip, and deposit insulating layers on the inner surfaces of the through-silicon vias and the horizontal channels; (2) Perform plasma treatment on the lower surface of the packaging layer and align and bond it with the upper surface of the first silicon chip; Perform plasma treatment on the upper surface of the bonding layer and align and bond it with the lower surface of the first silicon chip; Perform plasma treatment on the lower surface of the bonding layer and align and bond it with the upper surface of the second silicon chip; Perform plasma treatment on the upper surface of the heat sink structure and align and bond it with the lower surface of the second silicon chip; (3) Inject a low-melting-point metal.

8. The processing method according to claim 7, characterized in that, The insulating layer is silicon dioxide.

9. The processing method according to claim 7, characterized in that, The packaging layer, the bonding layer, and the heat sink structure are all made of epoxy resin materials.

10. The processing method according to claim 7, wherein, The low-melting-point metal is one or more of gallium, indium, tin, and bismuth.

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