A short-circuit shutdown capability test circuit and test method for power semiconductor devices

Abstract

The present invention provides a power semiconductor device short-circuit turn-off capability test circuit and test method, the circuit comprising: one end of the power supply is respectively connected to one end of the first switch circuit and one end of the second switch circuit, the other end of the power supply is respectively connected to the other end of the power semiconductor device to be tested and the other end of the fourth switch circuit; the other end of the second switch circuit is respectively connected to one end of the auxiliary circuit, one end of the freewheeling circuit and one end of the third switch circuit; the other end of the first switch circuit is respectively connected to the other end of the auxiliary circuit, the other end of the freewheeling circuit, the other end of the buffer circuit and one end of the power semiconductor device to be tested; the other end of the third switch circuit is respectively connected to one end of the fourth switch circuit and one end of the buffer circuit. By implementing the present invention, the Class II and Class III short-circuit capability tests can be realized on the basis of the Class I short-circuit test at the IGBT device level.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a short-circuit turn-off capability test circuit and a test method for a power semiconductor device. Background Art

[0002] With the vigorous development of power electronics technology and high-voltage direct current transmission technology, power electronics equipment with high-power IGBT as the core has become an important technical means to build new power systems.

[0003] When the IGBT is in short-circuit conduction, the large short-circuit current and the energy generated during the short-circuit process will weaken the device's shutdown capability, making the device very easy to burn out due to dynamic avalanche, dynamic latching, excessive power consumption, etc. In addition, during the short-circuit shutdown process, due to the influence of the loop load inductance or stray inductance, it is very easy to induce an overshoot voltage at both ends of the device that exceeds the maximum withstand voltage of the device and causes thermal breakdown. Therefore, the short-circuit capability of the IGBT is an important measure to determine the reliability of IGBT products. Accurately testing the short-circuit capability of the IGBT will provide an important technical reference for the iterative optimization design of IGBT devices. The short-circuit modes of IGBT devices can be mainly divided into three types: Class I short circuit, Class II short circuit, and Class III short circuit. The short-circuit capability assessment of IGBT usually only performs Class I short-circuit tests at the device level, and three types of short-circuit tests at the device level. However, for newly developed IGBT devices, there are problems such as long cycle from research and development to short-circuit test verification at the device level, and easy explosion after device failure. It is urgent to conduct comprehensive short-circuit capability tests at the device level to quickly evaluate the IGBT to ensure that the device can successfully pass the device-level test verification. Summary of the invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defect in the prior art that it is difficult to perform a comprehensive short-circuit capability test on the IGBT at the device level, thereby providing a short-circuit shutdown capability test circuit and test method for a power semiconductor device.

[0005] The technical solution proposed by the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a short-circuit shutdown capability test circuit for a power semiconductor device, comprising: a power supply, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, an auxiliary circuit, a freewheeling circuit and a buffer circuit, wherein one end of the power supply is respectively connected to one end of the first switch circuit and one end of the second switch circuit, and the other end of the power supply is respectively connected to the other end of the power semiconductor device under test and the other end of the fourth switch circuit; the other end of the second switch circuit is respectively connected to one end of the auxiliary circuit, one end of the freewheeling circuit and one end of the third switch circuit; the other end of the first switch circuit is respectively connected to the other end of the auxiliary circuit, the other end of the freewheeling circuit, the other end of the buffer circuit and one end of the power semiconductor device under test; the other end of the third switch circuit is respectively connected to one end of the fourth switch circuit and one end of the buffer circuit;

[0007] When performing a Class I short-circuit capability test, the first switch circuit is controlled to be turned on, triggering the power semiconductor device under test to be turned on, and the power semiconductor device under test enters a Class I short-circuit capability test condition;

[0008] When performing a Class II short-circuit capability test, the second switch circuit and the third switch circuit are controlled to be turned on, triggering the power semiconductor device under test to be turned on, and the power supply, the buffer circuit, and the power semiconductor device under test to form a flow, and when the current flowing through the power semiconductor device under test reaches a first set current, the auxiliary circuit is triggered to be turned on, and the power semiconductor device under test enters a Class II short-circuit condition;

[0009] When performing a Class III short-circuit capability test, the second switch circuit and the fourth switch circuit are controlled to be turned on, the auxiliary circuit is triggered to be turned on, and a current is formed between the power supply, the auxiliary circuit, and the buffer circuit. When the current flowing through the buffer circuit reaches a second set current, the auxiliary circuit is triggered to be turned off, and the buffer circuit and the freewheeling circuit form a freewheeling loop. After a first preset time, the auxiliary circuit and the power semiconductor device under test are triggered to be turned on, the freewheeling circuit enters a reverse recovery stage, and the power semiconductor device under test enters a Class III short-circuit condition.

[0010] Optionally, the short-circuit shutdown capability test circuit of the power semiconductor device further includes: a gate test power supply, a collector test power supply, a fifth switch and a sixth switch, wherein one end of the gate test power supply is connected to the gate of the power semiconductor device under test through the fifth switch, and the other end of the gate test circuit is connected to the other end of the power supply; one end of the collector test power supply is connected to the collector of the power semiconductor device under test through the sixth switch, and the other end of the collector test circuit is connected to the other end of the power supply.

[0011] Optionally, the short-circuit shutdown capability test circuit of the power semiconductor device also includes: a gate leakage current sampling sensor and a collector leakage current sampling sensor, wherein one end of the gate leakage current sampling sensor is connected to the gate of the power semiconductor device under test, and the other end of the gate leakage current sampling sensor is connected to an external controller; one end of the collector leakage current sampling sensor is connected to the collector of the power semiconductor device under test, and the other end of the collector leakage current sampling sensor is connected to an external controller.

[0012] Optionally, the power supply includes: a high-voltage charging power supply, a seventh switch and a DC bus capacitor, wherein one end of the high-voltage charging power supply is connected to one end of the DC bus capacitor through the seventh switch, and the other end of the high-voltage charging power supply is connected to the other end of the DC bus capacitor through the seventh switch.

[0013] Optionally, the power semiconductor device short-circuit shutdown capability test circuit also includes: a protection circuit, one end of the protection circuit is connected to one end of the power supply, and the other end of the protection circuit is respectively connected to one end of the first switch circuit and one end of the second switch circuit.

[0014] Optionally, the power semiconductor device under test is an IGBT.

[0015] In a second aspect, an embodiment of the present invention provides a method for testing the short-circuit shutdown capability of a power semiconductor device. Based on the short-circuit shutdown capability testing circuit of a power semiconductor device described in the first aspect of the embodiment of the present invention, the method for testing the short-circuit shutdown capability of a power semiconductor device comprises:

[0016] Controlling the first switch circuit to turn on, triggering the power semiconductor device under test to turn on, and the power semiconductor device under test to enter a Class I short-circuit capability test condition;

[0017] Controlling the second switch circuit and the third switch circuit to be turned on, triggering the power semiconductor device under test to be turned on, so that the power supply, the buffer circuit, and the power semiconductor device under test form a flow, and when the current flowing through the power semiconductor device under test reaches a first set current, triggering the auxiliary circuit to be turned on, the power semiconductor device under test enters a Class II short-circuit condition;

[0018] Control the second switch circuit and the fourth switch circuit to be turned on, trigger the auxiliary circuit to be turned on, trigger the auxiliary circuit to be turned on, the power supply and the auxiliary circuit and the buffer circuit form a flow, when the current flowing through the buffer circuit reaches the second set current, trigger the auxiliary circuit to be turned off, the buffer circuit and the freewheeling circuit form a freewheeling loop, after a first preset time, trigger the auxiliary circuit and the power semiconductor device under test to be turned on, the freewheeling circuit enters the reverse recovery stage, and the power semiconductor device under test enters Class III short-circuit operation.

[0019] Optionally, the method for testing the short-circuit shutdown capability of a power semiconductor device further includes: shutting down the power semiconductor device under test after the short-circuit time reaches a second preset time.

[0020] Optionally, the short-circuit shutdown capability testing method of a power semiconductor device further includes: after completing the short-circuit capability test of the power device under test and shutting down the power semiconductor device under test, determining whether the power device under test has failed based on the gate leakage current collected by the gate leakage current sampling sensor and the collector cutoff current collected by the collector leakage current sampling sensor.

[0021] Optionally, before performing the shutdown capability test of the power semiconductor device, the method further includes: closing the seventh switch and charging the DC bus capacitor to a set voltage by using a high-voltage charging power supply.

[0022] The technical solution of the present invention has the following advantages:

[0023] The present invention provides a power semiconductor device short-circuit turn-off capability test circuit, comprising: a power supply, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, an auxiliary circuit, a freewheeling circuit and a buffer circuit, wherein one end of the power supply is respectively connected to one end of the first switch circuit and one end of the second switch circuit, and the other end of the power supply is respectively connected to the other end of the power semiconductor device under test and the other end of the fourth switch circuit; the other end of the second switch circuit is respectively connected to one end of the auxiliary circuit, one end of the freewheeling circuit and one end of the third switch circuit; the other end of the first switch circuit is respectively connected to the other end of the auxiliary circuit, the other end of the freewheeling circuit, the other end of the buffer circuit and one end of the power semiconductor device under test; the other end of the third switch circuit is respectively connected to one end of the fourth switch circuit and one end of the buffer circuit. The auxiliary circuit, the freewheeling circuit and the buffer circuit are used to simulate the Class II and Class III short circuit test conditions, and then the Class II and Class III short circuit capability tests are realized on the basis of the Class I short circuit test at the IGBT device level.

[0024] The short-circuit shutdown capability testing method of a power semiconductor device provided by the present invention realizes three short-circuit capability tests of IGBT devices, namely, Class I short circuit, Class II short circuit, and Class III short circuit, by performing sequential logic control on a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit in the shutdown capability test of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A principle block diagram of a short-circuit shutdown capability test circuit for a power semiconductor device according to an embodiment of the present invention;

[0027] Figure 2 Another principle block diagram of a short-circuit shutdown capability test circuit for a power semiconductor device according to an embodiment of the present invention;

[0028] Figure 3 A circuit diagram for testing the short-circuit shutdown capability of a power semiconductor device according to a specific example of an embodiment of the present invention

[0029] Figure 4 The flowchart is a specific example of a method for testing the short-circuit shutdown capability of a power semiconductor device in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] The embodiment of the present invention provides a short-circuit shutdown capability test circuit for a power semiconductor device, such as Figure 1 As shown, it includes: a first switch circuit 1, a second switch circuit 2, a third switch circuit 3, a fourth switch circuit 4, a power supply 5, an auxiliary circuit 6, a freewheeling circuit 7 and a buffer circuit 8.

[0035] Among them, one end of the power supply 5 is respectively connected to one end of the first switch circuit 1 and one end of the second switch circuit 2, and the other end of the power supply 5 is respectively connected to the other end of the power semiconductor device under test and the other end of the fourth switch circuit 4; the other end of the second switch circuit 2 is respectively connected to one end of the auxiliary circuit 6, one end of the freewheeling circuit 7 and one end of the third switch circuit 3; the other end of the first switch circuit 1 is respectively connected to the other end of the auxiliary circuit 6, the other end of the freewheeling circuit 7, the other end of the buffer circuit 8 and one end of the power semiconductor device under test; the other end of the third switch circuit 3 is respectively connected to one end of the fourth switch circuit 4 and one end of the buffer circuit 8.

[0036] In a specific embodiment, when performing a Class I short-circuit capability test, the first switch circuit 1 is controlled to be turned on, triggering the power semiconductor device under test to be turned on, and the power semiconductor device under test enters a Class I short-circuit capability test condition. Specifically, the first switch circuit 1 is turned on, the power semiconductor device under test is directly connected to the power supply 5, and a Class I short-circuit capability test is performed on the power semiconductor device under test.

[0037] When performing a Class II short-circuit capability test, the second switch circuit 2 and the third switch circuit 3 are controlled to be turned on, triggering the power semiconductor device under test to be turned on, and the power supply 5 forms a flow with the buffer circuit 8 and the power semiconductor device under test. When the current flowing through the power semiconductor device under test reaches the first set current, the auxiliary circuit 6 is triggered to be turned on, and the power semiconductor device under test enters a Class II short-circuit condition. Specifically, the second switch circuit 2 and the third switch circuit 3 are turned on, the power supply 5 forms a flow with the buffer circuit 8 and the power semiconductor device under test, and the current flowing through the power semiconductor device under test rises in a ramp. When the current flowing through the power semiconductor device under test reaches the first set current, the auxiliary circuit 6 is triggered to be turned on, and the power semiconductor device under test is subjected to a Class II short-circuit capability test. In an embodiment of the present invention, the first set current is determined according to actual needs.

[0038] When performing a Class III short-circuit capability test, the second switch circuit 2 and the fourth switch circuit 4 are controlled to be turned on, the auxiliary circuit 6 is triggered to be turned on, the power supply 5 forms a flow with the auxiliary circuit 6 and the buffer circuit 8, and the current flowing through the buffer circuit 8 rises in a ramp. When the current flowing through the buffer circuit 8 reaches the second set current, the auxiliary circuit 6 is triggered to be turned off, and the buffer circuit 8 forms a freewheeling loop with the freewheeling circuit 7. After the first preset time, the auxiliary circuit 6 and the power semiconductor device under test are triggered to be turned on, and the freewheeling circuit 7 enters the reverse recovery stage, and the power semiconductor device under test enters a Class III short-circuit condition. In the embodiment of the present invention, the second set current and the first preset time are determined according to actual needs.

[0039] The present invention provides a power semiconductor device short-circuit turn-off capability test circuit, comprising: a power supply, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, an auxiliary circuit, a freewheeling circuit and a buffer circuit, wherein one end of the power supply is respectively connected to one end of the first switch circuit and one end of the second switch circuit, and the other end of the power supply is respectively connected to the other end of the power semiconductor device under test and the other end of the fourth switch circuit; the other end of the second switch circuit is respectively connected to one end of the auxiliary circuit, one end of the freewheeling circuit and one end of the third switch circuit; the other end of the first switch circuit is respectively connected to the other end of the auxiliary circuit, the other end of the freewheeling circuit, the other end of the buffer circuit and one end of the power semiconductor device under test; the other end of the third switch circuit is respectively connected to one end of the fourth switch circuit and one end of the buffer circuit. The auxiliary circuit, the freewheeling circuit and the buffer circuit are used to simulate the Class II and Class III short circuit test conditions, and then the Class II and Class III short circuit capability tests are realized on the basis of the Class I short circuit test at the IGBT device level.

[0040] In one embodiment, if Figure 2As shown, the first switch circuit 1 includes a switch S1, the second switch circuit 2 includes a switch S2, the third switch circuit 3 includes a switch S3, and the fourth switch circuit 4 includes a switch S4. The auxiliary circuit 6 includes Figure 2 The auxiliary IGBT shown in FIG. 7 includes the following: Figure 2 The buffer circuit 8 includes the following: Figure 2 The reactor shown in the figure. The power semiconductor device under test is an IGBT. A freewheeling diode can be connected in anti-parallel to the IGBT under test to prevent the overshoot voltage at both ends of the device from exceeding the maximum withstand voltage of the device and causing breakdown.

[0041] In one embodiment, if Figure 3 As shown, the short-circuit shutdown capability test circuit of the power semiconductor device also includes: a gate test power supply, a collector test power supply, a fifth switch S5 and a sixth switch S6, wherein one end of the gate test power supply is connected to the gate of the power semiconductor device under test through the fifth switch S5, and the other end of the gate test circuit is connected to the other end of the power supply 5; one end of the collector test power supply is connected to the collector of the power semiconductor device under test through the sixth switch S6, and the other end of the collector test circuit is connected to the other end of the power supply 5.

[0042] In a specific embodiment, the short-circuit shutdown capability test circuit of a power semiconductor device also includes: a gate leakage current sampling sensor and a collector leakage current sampling sensor, wherein one end of the gate leakage current sampling sensor is connected to the gate of the power semiconductor device under test, and the other end of the gate leakage current sampling sensor is connected to an external controller; one end of the collector leakage current sampling sensor is connected to the collector of the power semiconductor device under test, and the other end of the collector leakage current sampling sensor is connected to the external controller.

[0043] In an embodiment of the present invention, after each short-circuit turn-off capability test, the gate leakage current and collector cut-off current of the IGBT device under test are tested using a gate test power supply and a collector test power supply, so as to evaluate whether the IGBT device under test has passed the short-circuit turn-off capability test assessment. Specifically, after each short-circuit turn-off capability test, the fifth switch S5 is closed, a gate test power supply is applied between the gate and emitter of the IGBT under test, and the gate leakage current is detected. Subsequently, the fifth switch S5 is opened, the sixth switch S6 is closed, a collector test power supply is applied between the collector and emitter of the IGBT under test, and the collector cut-off current is detected. Then, whether the IGBT under test fails is determined based on the gate leakage current and the collector cut-off current.

[0044] After the short-circuit test of the IGBT under test, the short-circuit shutdown capability test circuit of the power semiconductor device can also test the gate leakage current and collector cut-off current of the IGBT under test, so as to simply and intuitively judge whether the IGBT under test has passed the short-circuit shutdown capability test assessment.

[0045] In one embodiment, if Figure 3 As shown, the power supply 5 includes: a high-voltage charging power supply, a seventh switch S and a DC bus capacitor, wherein one end of the high-voltage charging power supply is connected to one end of the DC bus capacitor through the seventh switch S, and the other end of the high-voltage charging power supply is connected to the other end of the DC bus capacitor through the seventh switch S.

[0046] In a specific embodiment, the seventh switch S is closed, and the high-voltage charging power source charges the DC bus capacitor to a set voltage. When the power semiconductor device shutdown capability test is performed, the seventh switch S is opened, and the first switch S1 is closed to provide working power for the power semiconductor device short-circuit shutdown capability test circuit.

[0047] In one embodiment, if Figure 1 As shown, the short-circuit shutdown capability test circuit of the power semiconductor device also includes: a protection circuit 9, one end of the protection circuit 9 is connected to one end of the power supply 5, and the other end of the protection circuit 9 is respectively connected to one end of the first switch circuit 1 and one end of the second switch circuit 2.

[0048] In a specific embodiment, if Figure 3 As shown, the protection circuit 9 includes a protection switch. The protection switch is composed of an IGBT device, which can be quickly disconnected when a circuit fails.

[0049] The embodiment of the present invention further provides a method for testing the short-circuit shutdown capability of a power semiconductor device. Based on the above-mentioned short-circuit shutdown capability testing circuit of the power semiconductor device, the method for testing the short-circuit shutdown capability of the power semiconductor device is as follows: Figure 4 As shown, the following steps are included:

[0050] Step S11: controlling the first switch circuit to be turned on, triggering the power semiconductor device under test to be turned on, and the power semiconductor device under test enters a Class I short-circuit capability test condition.

[0051] In a specific embodiment, the Class I short-circuit capability test method is as follows: ① Close the seventh switch S, and the high-voltage charging power supply charges the DC bus capacitor to a set voltage. ② Open the seventh switch S, close the first switch S1, trigger the IGBT device under test to turn on and enter the Class I short-circuit capability test condition, and turn off the IGBT device under test after the short-circuit time reaches the second preset time. In the embodiment of the present invention, the second preset time is determined according to actual needs.

[0052] Step S12: Control the second switch circuit and the third switch circuit to be turned on, trigger the power semiconductor device under test to be turned on, and form a flow through the power supply, the buffer circuit, and the power semiconductor device under test. When the current flowing through the power semiconductor device under test reaches a first set current, the auxiliary circuit is triggered to be turned on, and the power semiconductor device under test enters a Class II short-circuit condition.

[0053] In a specific embodiment, the method for testing the Class II short-circuit capability is as follows: ① Close the seventh switch S, and the high-voltage charging power supply charges the DC bus capacitor to a set voltage. ② Open the seventh switch S, close the second switch S2 and the third switch S3, trigger the IGBT under test to turn on, and the DC bus capacitor, the reactor, and the IGBT under test form a flow until the current of the IGBT under test reaches the first set current. ③ Trigger the auxiliary IGBT to turn on so that the IGBT under test enters the Class II short-circuit condition, and turn off the IGBT under test after the short-circuit time reaches the second preset time.

[0054] Step S13: Control the second switch circuit and the fourth switch circuit to be turned on, trigger the auxiliary circuit to be turned on, and the power supply, the auxiliary circuit and the buffer circuit form a flow. When the current flowing through the buffer circuit reaches the second set current, the auxiliary circuit is triggered to be turned off, and the buffer circuit and the freewheeling circuit form a freewheeling loop. After the first preset time, the auxiliary circuit and the power semiconductor device under test are triggered to be turned on, the freewheeling circuit enters the reverse recovery stage, and the power semiconductor device under test enters Class III short-circuit operation.

[0055] In a specific embodiment, the method for testing the Class III short-circuit capability is as follows: ① Close the seventh switch S, and the high-voltage charging power supply charges the DC bus capacitor to a set voltage. ② Open the seventh switch S, close the second switch S2 and the fourth switch S4, trigger the auxiliary IGBT to turn on, and the DC bus capacitor, the auxiliary IGBT, and the reactor form a current-carrying loop until the reactor current reaches the second set current. ③ Turn off the auxiliary IGBT, and the reactor and the diode form a freewheeling loop. ④ After the first preset time, trigger the auxiliary IGBT and the IGBT under test to turn on, the diode enters the reverse recovery stage, and the IGBT under test enters the Class III short-circuit condition. After the short-circuit time reaches the second preset time, turn off the IGBT under test.

[0056] The short-circuit shutdown capability testing method of a power semiconductor device provided by the present invention realizes three short-circuit capability tests of IGBT devices, namely, Class I short circuit, Class II short circuit, and Class III short circuit, by performing sequential logic control on a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit in the shutdown capability test of the power semiconductor device.

[0057] In one embodiment, the short-circuit shutdown capability testing method of a power semiconductor device also includes: after completing the short-circuit capability test of the power device under test and shutting down the power semiconductor device under test, determining whether the power device under test has failed based on the gate leakage current collected by the gate leakage current sampling sensor and the collector cutoff current collected by the collector leakage current sampling sensor.

[0058] In a specific embodiment, after the Class I short-circuit capability test of the IGBT under test is completed and the IGBT under test is turned off, the first switch S1 is opened, the fifth switch S5 is closed, a gate test power supply is applied between the gate and emitter of the IGBT under test, and the gate leakage current is detected. Subsequently, the fifth switch S5 is opened, the sixth switch S6 is closed, a collector test power supply is applied between the collector and emitter of the IGBT under test, and the collector cut-off current is detected. Then, whether the IGBT under test is failed is determined based on the gate leakage current and the collector cut-off current.

[0059] Furthermore, after completing the Class II short-circuit capability test of the IGBT under test and turning off the IGBT under test, open the second switch S2 and the third switch S3, close the fifth switch S5, apply a gate test power supply between the gate and emitter of the IGBT under test, and detect the gate leakage current. Then open the fifth switch S5, close the sixth switch S6, apply a collector test power supply between the collector and emitter of the IGBT under test, and detect the collector cut-off current. Then, determine whether the IGBT under test is failed based on the gate leakage current and the collector cut-off current.

[0060] Furthermore, after completing the Class III short-circuit capability test of the IGBT under test and turning off the IGBT under test, open the second switch S2 and the fourth switch S4, close the fifth switch S5, apply a gate test power supply between the gate and emitter of the IGBT under test, and detect the gate leakage current. Then open the fifth switch S5, close the sixth switch S6, apply a collector test power supply between the collector and emitter of the IGBT under test, and detect the collector cut-off current. Then, determine whether the IGBT under test is failed based on the gate leakage current and the collector cut-off current.

[0061] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A power semiconductor device short-circuit shutdown capability test circuit, characterized in that: include: A power supply, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, an auxiliary circuit, a freewheeling circuit and a buffer circuit, wherein: One end of the power supply is respectively connected to one end of the first switch circuit and one end of the second switch circuit, and the other end of the power supply is respectively connected to the other end of the power semiconductor device under test and the other end of the fourth switch circuit; The other end of the second switch circuit is respectively connected to one end of the auxiliary circuit, one end of the freewheeling circuit and one end of the third switch circuit; The other end of the first switch circuit is respectively connected to the other end of the auxiliary circuit, the other end of the freewheeling circuit, the other end of the buffer circuit and one end of the power semiconductor device under test; The other end of the third switch circuit is connected to one end of the fourth switch circuit and one end of the buffer circuit respectively; When performing a Class I short-circuit capability test, the first switch circuit is controlled to be turned on, triggering the power semiconductor device under test to be turned on, and the power semiconductor device under test enters a Class I short-circuit capability test condition; When performing a Class II short-circuit capability test, the second switch circuit and the third switch circuit are controlled to be turned on, triggering the power semiconductor device under test to be turned on, and the power supply, the buffer circuit, and the power semiconductor device under test to form a flow, and when the current flowing through the power semiconductor device under test reaches a first set current, the auxiliary circuit is triggered to be turned on, and the power semiconductor device under test enters a Class II short-circuit condition; When performing a Class III short-circuit capability test, the second switch circuit and the fourth switch circuit are controlled to be turned on, the auxiliary circuit is triggered to be turned on, and the power supply forms a flow with the auxiliary circuit and the buffer circuit. When the current flowing through the buffer circuit reaches a second set current, the auxiliary circuit is triggered to be turned off, and the buffer circuit and the freewheeling circuit form a freewheeling loop. After a first preset time, the auxiliary circuit and the power semiconductor device under test are triggered to be turned on, the freewheeling circuit enters a reverse recovery stage, and the power semiconductor device under test enters a Class III short-circuit condition; The auxiliary circuit is an auxiliary IGBT.

2. The power semiconductor device short-circuit shutdown capability test circuit according to claim 1, characterized in that: Also includes: A gate test power supply, a collector test power supply, a fifth switch and a sixth switch, wherein: One end of the gate test power supply is connected to the gate of the power semiconductor device under test through the fifth switch, and the other end of the gate test power supply is connected to the other end of the power supply; One end of the collector test power supply is connected to the collector of the power semiconductor device under test through the sixth switch, and the other end of the collector test power supply is connected to the other end of the power supply.

3. The power semiconductor device short-circuit shutdown capability test circuit according to claim 2, characterized in that: It also includes: a gate leakage current sampling sensor and a collector leakage current sampling sensor, wherein: One end of the gate leakage current sampling sensor is connected to the gate of the power semiconductor device under test, and the other end of the gate leakage current sampling sensor is connected to an external controller; One end of the collector leakage current sampling sensor is connected to the collector of the power semiconductor device under test, and the other end of the collector leakage current sampling sensor is connected to an external controller.

4. The power semiconductor device short-circuit shutdown capability test circuit according to claim 1, characterized in that: The power supply includes: a high-voltage charging power supply, a seventh switch and a DC bus capacitor, wherein: One end of the high-voltage charging power supply is connected to one end of the DC bus capacitor through the seventh switch, and the other end of the high-voltage charging power supply is connected to the other end of the DC bus capacitor through the seventh switch.

5. The power semiconductor device short-circuit shutdown capability test circuit according to claim 1, characterized in that: Also includes: A protection circuit, one end of the protection circuit is connected to one end of the power supply, and the other end of the protection circuit is respectively connected to one end of the first switch circuit and one end of the second switch circuit.

6. The power semiconductor device short-circuit shutdown capability test circuit according to claim 1, characterized in that: The power semiconductor device under test is IGBT.

7. A method for testing the short-circuit shutdown capability of a power semiconductor device, characterized in that: Based on the power semiconductor device short-circuit shutdown capability test circuit according to any one of claims 1 to 6, the power semiconductor device short-circuit shutdown capability test method comprises: Controlling the first switch circuit to turn on, triggering the power semiconductor device under test to turn on, and the power semiconductor device under test to enter a Class I short-circuit capability test condition; Controlling the second switch circuit and the third switch circuit to be turned on, triggering the power semiconductor device under test to be turned on, so that the power supply, the buffer circuit, and the power semiconductor device under test form a flow, and when the current flowing through the power semiconductor device under test reaches a first set current, triggering the auxiliary circuit to be turned on, the power semiconductor device under test enters a Class II short-circuit condition; The second switch circuit and the fourth switch circuit are controlled to be turned on, the auxiliary circuit is triggered to be turned on, and the power supply, the auxiliary circuit and the buffer circuit form a flow. When the current flowing through the buffer circuit reaches the second set current, the auxiliary circuit is triggered to be turned off, and the buffer circuit and the freewheeling circuit form a freewheeling loop. After a first preset time, the auxiliary circuit and the power semiconductor device under test are triggered to be turned on, the freewheeling circuit enters the reverse recovery stage, and the power semiconductor device under test enters a Class III short-circuit operation.

8. The method for testing the short-circuit shutdown capability of a power semiconductor device according to claim 7, characterized in that: Also includes: After the short-circuit time reaches a second preset time, the power semiconductor device under test is turned off.

9. The method for testing the short-circuit shutdown capability of a power semiconductor device according to claim 8, characterized in that: Also includes: After completing the short-circuit capability test of the power device under test and shutting down the power semiconductor device under test, determine whether the power device under test has failed based on the gate leakage current collected by the gate leakage current sampling sensor and the collector cut-off current collected by the collector leakage current sampling sensor.

10. The method for testing the short-circuit shutdown capability of a power semiconductor device according to claim 7, characterized in that: Before the power semiconductor device shutdown capability test is performed, the method also includes: closing the seventh switch and charging the DC bus capacitor to a set voltage using a high-voltage charging power supply.

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