Method for characterizing timing features of combinational logic units, storage medium

Abstract

The application discloses a kind of characterization methods of the timing characteristics of full voltage domain combination logic unit, storage medium.Therein characterization method includes: setting the working environment of combination logic unit, parameter;Select output load loadmin, and change input transition time, carry out a small amount of Monte Carlo simulation to establish the relationship model of delay standard deviation and input transition time;In subthreshold region or superthreshold region, the input transition time of step situation is selected, the output load is changed, and a small amount of Monte Carlo simulation is carried out to establish the relationship model of corresponding delay standard deviation and output load;In subthreshold region or superthreshold region, the input transition time of value is slow input, the output load is changed, and a small amount of Monte Carlo simulation is carried out to establish the relationship model of corresponding delay standard deviation and output load;All relationship models obtained are integrated, and the characterization model of full voltage domain timing characteristics is obtained.The application can quickly obtain the characterization parameter of corresponding timing characteristics with less simulation times.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to a method for characterizing the timing characteristics of a combinational logic cell applicable to all voltage domains. BACKGROUND

[0002] In the process of circuit operation, the delay generated by each cell is not constant, but has a certain volatility, and the size of the volatility is usually measured by the standard deviation σ as a timing statistical parameter. The lookup table type timing analysis method has always been the core of EDA (Electronic design automation) tools. With the shrinking of process nodes, in order to more accurately calculate the statistical delay, a series of methods have been proposed in turn: OCV (on-chip variation), AOCV (advanced on-chip variation), POCV (parameter on-chip variation), and LVF (library variation format).

[0003] Among them, OCV is based on the timing library of the cell delay, and the influence of delay fluctuation on the cell and the path is represented by multiplying a fixed coefficient, and this coefficient is obtained by inverter chain simulation. Although this method ensures the timing convergence of the circuit to a certain extent, it cannot accurately obtain the delay information, especially in the case of advanced process nodes where the fluctuation has a greater impact, which will bring greater pessimism. AOCV changes the fixed coefficient to a coefficient that changes with the length of the stage, which further reduces the error, but increases the simulation overhead in the process of obtaining the coefficient. POCV features a cell under a fixed input transmission time and load, and gives a delay fluctuation sensitivity to represent local fluctuation. This method has further improved the accuracy, but due to the same cell having only one characteristic environment, it still leads to a large error. LVF is based on the shortcomings of POCV and combines the characteristics of lookup table to establish a lookup table format containing mean and variance with input transition time and output load as index. Compared with POCV, although the LVF characterization time increases with the increase of the number of lookup table values, due to its more detailed table, the accuracy is further improved.

[0004] The above methods are based on the library, that is, discrete PVT and lookup table composed of input transmission time and output load. Their advantages are that the extraction of characteristic parameters can be performed in advance, and the accuracy is high, but the disadvantages are also obvious. In the process of building a library, a large amount of time is consumed for obtaining the characteristic parameters. In the case of ensuring accuracy, for example, the LVF library, each cell needs to perform 7*7 times of Monte Carlo analysis under a certain PVT, and the simulation overhead required for different drive strengths and different types of cells will be huge.

[0005] Therefore, how to provide a characterization method of timing characteristics of a circuit with less simulation overhead is an urgent technical problem in the industry. SUMMARY

[0006] In order to solve the technical problem of large simulation overhead in obtaining the timing characteristics of a circuit in the prior art, the application provides a characterization method of timing characteristics of a combinational logic unit and a storage medium.

[0007] The characterization method of timing characteristics of a combinational logic unit provided by the application comprises:

[0008] Setting the working environment and working parameters of the combinational logic unit to be characterized;

[0009] Selecting an output load load min under the working environment, the output load load min is a preset minimum load, and changing the input slew time to perform a preset number of Monte Carlo simulations to establish a relationship model of delay standard deviation and input slew time, and obtaining the value of the input slew time at the fast-slow input boundary from the relationship model of delay standard deviation and input slew time;

[0010] Determining whether the combinational logic unit works in a sub-threshold region or a super-threshold region;

[0011] In the working environment, selecting an input slew time with a step value in the sub-threshold region or the super-threshold region, and changing the output load to establish a relationship model of delay standard deviation and output load under fast input in the sub-threshold region or the super-threshold region by performing a preset number of Monte Carlo simulations;

[0012] In the working environment, selecting an input slew time with a slow input value in the sub-threshold region or the super-threshold region, and changing the output load to establish a relationship model of delay standard deviation and output load under slow input in the sub-threshold region or the super-threshold region by performing a preset number of Monte Carlo simulations; the value of the input slew time with the slow input value is greater than the value of the input slew time at the fast-slow input boundary;

[0013] Integrating all the relationship models of the sub-threshold region or the super-threshold region to obtain a characterization model of the timing characteristics of the combinational logic unit.

[0014] Further, the relationship model of delay standard deviation and input slew time, and the value of the input slew time at the fast-slow input boundary are obtained by the following steps:

[0015] Selecting an output load load min and an input slew time with a step value slew to perform a preset number of Monte Carlo simulations to obtain a delay standard deviation σ0;

[0016] Randomly select two groups of input slew1, slew2, select output load load min , respectively, a predetermined number of Monte Carlo simulation, get two input slew1, slew2 corresponding to two delay standard deviation σ1, σ2;

[0017] Two input slew1, slew2 as the independent variable, two delay standard deviation σ1, σ2 as the dependent variable, through two delay standard deviation σ1, σ2 straight line L1, get the expression of straight line L1, and delay standard deviation σ0 value into the expression of straight line L1, get the input slew1, slew2 value at the fast and slow input boundary;

[0018] Output with input slew, output load load min Index delay standard deviation σ0; output with input slew1, output load load min Index delay standard deviation σ1; output with input slew2, output load load min Index delay standard deviation σ2, through the output of three groups of data to establish the relationship between the slow input delay standard deviation and input slew, and the input slew1, slew2 value at the fast and slow input boundary.

[0019] Further, the method for establishing the relationship between the delay standard deviation and the output load under the fast input in the subthreshold region or the superthreshold region comprises:

[0020] Select the input slew and change the output load load a , the output load load a The value range is [0.5*maximum output load, maximum output load], corresponding to a predetermined number of Monte Carlo simulation, get the corresponding delay standard deviation σ a ;

[0021] Output with input slew, output load load min , output load load a As the independent variable, delay standard deviation σ0, σ a As the dependent variable, through two delay standard deviation σ0, σ a Straight line L2, get the expression of straight line L2, and the slope k0 of straight line L2;

[0022] Output with input slew, output load load min Index delay standard deviation σ0; output with input slew, output load load a Index delay standard deviation σ a ;

[0023] The relationship model of the delay standard deviation and the output load in the sub-threshold region or the super-threshold region is established by the two groups of output data.

[0024] Further, the relationship model of the delay standard deviation and the output load in the sub-threshold region comprises:

[0025] randomly selecting the input slew rate slew b ; b , the output load load min , and the corresponding delay standard deviation

[0026] The delay standard deviation is substituted into the expression of the straight line L2 to obtain the value of the output load load at the boundary of the large output load;

[0027] The relationship model of the delay standard deviation and the output load in the sub-threshold region is established.

[0028] Further, the relationship model of the delay standard deviation and the output load in the super-threshold region comprises:

[0029] randomly selecting the input slew rate slew c ;

[0030] Based on the expression of the straight line L1, the input slew rate slew c , the output load load min , and the corresponding delay standard deviation

[0031] The input slew rate slew c , the output load load c , and the output load load c are selected, the value range of the output load load c is [0.5*maximum output load, maximum output load], and the delay standard deviation σ c is obtained by performing Monte Carlo simulation for a preset number of times;

[0032] The delay standard deviation σ c is taken as the independent variable, and a straight line L3 with a slope k0 is drawn;

[0033] The delay standard deviation σ is substituted into the straight line L3 to obtain the value of the output load load as the independent variable, and the output load load is taken as the input slew rate slew cThe minimum load boundary;

[0034] Select input conversion time as slew c Output load d The output load d The value range is [output load] min Output load Perform a preset number of Monte Carlo simulations to obtain the delay standard deviation σ. d ;

[0035] Output load min load d As the independent variable, after time delay, the standard deviation σ d Draw line L4, and calculate the output load at the intersection of line L3 and line L4 as the independent variable. The value of the output load As input conversion time slew c Maximum load boundary;

[0036] Calculate input conversion time slew c intermediate load boundary

[0037] The output load is obtained through the expression of line L4. Delay standard deviation at The value of is obtained by using the expression for line L3 to obtain the output load. standard deviation of delay The value;

[0038] slew during input conversion time c Under the condition of output load As the independent variable, with time delay standard deviation The dependent variable is the standard deviation after time delay. Draw line L5 to obtain the expression for line L5;

[0039] The output is slew of the input conversion time. c Output load min Standard deviation of index latency The output is slew of the input conversion time. c Output load d The standard deviation of the delay for the index σ d The output is slew of the input conversion time. c Output load c The standard deviation of the delay for the index σ c ;

[0040] Slew rate of input transition time is established by output data c Corresponding delay standard deviation and output load relationship model

[0041] Select input transition time slew under arbitrary slow input e , input transition time slew e Substitute into the expression of straight line L1, get input transition time slew e , output load load min Corresponding delay standard deviation

[0042] In the case of output load is output load load min , calculate input transition time slew e The difference Δ of delay standard deviation of input transition time slew c , make straight line L3`, where L3` = L3 + Δ / 2; make straight line L4`, where L4` = L4 + Δ;

[0043] Select input transition time slew e , delay standard deviation The value of is brought into the expression of straight line L3`, get the value of output load As the minimum load boundary of input transition time slew e ;

[0044] And calculate the intersection of straight line L3` and straight line L4` output load The value of is the maximum load boundary of input transition time slew e ;

[0045] Select input transition time slew e , intermediate load boundary The value of delay standard deviation At output load Is obtained by the expression of straight line L4`, the value of delay standard deviation At output load Is obtained by the expression of straight line L3`;

[0046] Select input transition time slew e , output load As the independent variable, delay standard deviation As the dependent variable, delay standard deviation Make straight line L5`, get the expression of straight line L5`;

[0047] Establish the relationship model of delay standard deviation and output load in the case of super threshold region and slow input.

[0048] Further, the working parameters include at least one of a type, a size, a temperature, a process angle and a working voltage of the combinational logic cell.

[0049] Further, the preset minimum output load is 0.1 fF.

[0050] Further, the preset number of times in the sub-threshold region is greater than or equal to 4.

[0051] Further, the preset number of times in the super-threshold region is greater than or equal to 6.

[0052] The computer readable storage medium provided by the present application is used for storing a computer program, and the computer program runs to execute the characterization method of the timing characteristics of the full-voltage-domain combinational logic cell.

[0053] The present application obtains the relationship model of the input slew time, the output load and the delay standard deviation of the full-voltage-domain combinational logic cell by using a small amount of Monte Carlo simulation under different conditions, so as to obtain the timing statistical parameters of the delay fluctuation indexed by the input slew time slew and the output load load, so as to solve the technical problem that a large amount of simulation overhead is required in the traditional timing statistical characteristic library building process. Compared with the prior art, the present application has the following advantages:

[0054] 1. The present application has good applicability for obtaining timing statistical parameters of different types of combinational logic cells, and is still applicable under different driving intensities, different voltages, different temperatures and different process angles;

[0055] 2. In the sub-threshold case, the voltage node selected by the present application can obtain the relationship model of the delay standard deviation sigma and the input slew time slew and the output load load under this voltage node through only 4 times of Monte Carlo simulation, thereby effectively reducing the simulation overhead, and the average error is less than 10%;

[0056] 3. In the super-threshold case, the voltage node selected by the present application can obtain the relationship model of the delay standard deviation sigma and the input slew time slew and the output load load under this voltage node through only 6 times of Monte Carlo simulation, thereby effectively reducing the simulation overhead, and the average error is less than 10%. BRIEF DESCRIPTION OF DRAWINGS

[0057] The present application will be described in detail below in combination with embodiments and drawings, in which:

[0058] Figure 1 is the overall flowchart of the present application.

[0059] Figure 2 is a flow chart of the present application for establishing a relationship model of delay standard deviation and input transition time.

[0060] Figure 3 is a flow chart of the present application for establishing a relationship model of delay standard deviation and output load in the case of fast input in the sub-threshold region.

[0061] Figure 4 is a flow chart of the present application for establishing a relationship model of delay standard deviation and output load in the case of slow input in the sub-threshold region.

[0062] Figure 5 is a flow chart of the present application for establishing a relationship model of delay standard deviation and output load in the case of fast input in the super-threshold region.

[0063] Figure 6 is a flow chart of the present application for establishing a relationship model of delay standard deviation and output load in the case of slow input in the super-threshold region. DETAILED DESCRIPTION

[0064] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects more clear, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0065] Therefore, one feature described in the specification will be used to explain one feature of one embodiment of the present application, and it is not implied that each embodiment of the present application must have the described feature. In addition, it should be noted that the present specification describes many features. Although certain features can be combined together to show possible system designs, these features can also be used in other combinations that are not explicitly described. Therefore, unless otherwise stated, the described combinations are not intended to be limiting.

[0066] The characterization method of the timing characteristics of the combinational logic unit proposed in the present application mainly includes the following steps.

[0067] The working environment and working parameters of the combinational logic unit to be characterized are set. In one embodiment, the working parameters include at least one of the type, size, temperature, process angle and working voltage of the combinational logic unit.

[0068] The output load load min is selected under the set working environment, and the input transition time is changed to perform a predetermined number of Monte Carlo simulations to establish a relationship model of delay standard deviation and input transition time, and the value of the input transition time at the fast / slow input boundary is obtained from the relationship model of delay standard deviation and input transition time; the output load load minTo preset a minimum load.

[0069] determine whether the combinational logic unit works in a sub-threshold region or a super-threshold region;

[0070] If the combinational logic unit works in the sub-threshold region, input transition time with a step case is selected in the sub-threshold region under a set working environment, and output load is changed, a relationship model of delay standard deviation under fast input in the sub-threshold region and output load is established by performing a preset number of Monte Carlo simulations; if the combinational logic unit works in the super-threshold region, input transition time with a step case is selected in the super-threshold region under a set working environment, and output load is changed, a relationship model of delay standard deviation under fast input in the super-threshold region and output load is established by performing a preset number of Monte Carlo simulations.

[0071] The relationship model of delay standard deviation under slow input and output load is also established according to different cases under different voltages, input transition time with slow input is selected in the sub-threshold region or the super-threshold region under a set working environment, and output load is changed, a relationship model of delay standard deviation under slow input in the sub-threshold region or the super-threshold region and output load is established by performing a preset number of Monte Carlo simulations; the value of input transition time with slow input is greater than the value of input transition time at the boundary of fast and slow inputs;

[0072] All the relationship models of the sub-threshold region or the super-threshold region are integrated to obtain a characterization model of timing characteristics of the combinational logic unit, and the characterization model can be applied to circuits in a full voltage domain.

[0073] The application will be further described below Figure 1 The overall flow of the application is further described.

[0074] In step 101, a working environment of the combinational logic unit is set, the type, size, temperature and process angle of the combinational logic unit which needs to be quickly characterized are selected, and working voltage V is set;

[0075] In step 102, the minimum output load is selected under the selected working environment, that is, output load load min In a specific embodiment, the value of the minimum output load is 0.1fF, which is an example of the application and is not the only value of the minimum output load, and the value of the minimum output load can be appropriately selected by those skilled in the art according to the situation.

[0076] The input transition time slew is changed, the relationship model of delay standard deviation σ and input transition time slew is established by performing a small number of Monte Carlo simulations on the unit, and the input transition time slew at the boundary of fast and slow inputs is obtained from the relationship model

[0077] Step 103, judging whether the current working voltage V is greater than the threshold voltage V th If the current working voltage V is less than the threshold voltage V th , it is considered that the unit works in the sub-threshold region, and step 104 is entered; otherwise, if the current working voltage V is greater than the threshold voltage V th , it is considered that the unit works in the super-threshold region, and step 106 is entered.

[0078] Step 104, at this time, the combinational logic unit works in the sub-threshold region, under this condition, the input transition time is selected as the step case, that is, slew=0ps, the output load load is changed, and the relationship model of the delay standard deviation σ changing with the output load load is established by performing a small amount of Monte Carlo simulation on the unit.

[0079] Step 105, at this time, the combinational logic unit works in the sub-threshold region, under this condition, the input transition time is selected as the slow input case, that is, the output load load is changed, and the relationship model of the delay standard deviation σ corresponding to the input transition time of the slow input changing with the output load load is established by performing a small amount of Monte Carlo simulation on the unit.

[0080] Step 106, at this time, the unit works in the super-threshold region, under this condition, the input transition time is selected as the step case, that is, slew=0ps, the output load load is changed, and the relationship model of the delay standard deviation σ changing with the output load load is established by performing a small amount of Monte Carlo simulation on the combinational logic unit.

[0081] Step 107, at this time, the unit works in the super-threshold region, under this condition, the input transition time is selected as the slow input case, that is, the output load load is changed, and the relationship model of the delay standard deviation σ changing with the output load load is established by performing a small amount of Monte Carlo simulation on the unit.

[0082] Step 108, the voltage nodes required in the sub-threshold region and the super-threshold region are integrated, that is, the fast representation model of the timing statistical characteristics of the combinational logic unit in the full voltage domain under the selected environment is obtained, so that the timing statistical parameters of the delay fluctuation indexed by the input transition time slew and the output load load are quickly obtained.

[0083] In one embodiment, under the selected working environment, the output load load min is selected, the input transition time is changed, a preset number of Monte Carlo simulations are performed to establish the relationship model of the delay standard deviation and the input transition time, and the value of the input transition time at the fast-slow input boundary is obtained from the relationship model of the delay standard deviation and the input transition time; the output load loadmin The preset minimum load specifically comprises the following detailed steps.

[0084] First, select the output load load min and the input slew value as a step case, and perform a preset number of Monte Carlo simulations to obtain a delay standard deviation σ0;

[0085] Randomly select two groups of input slew values slew1 and slew2 as slow inputs, select the output load load min , and perform a preset number of Monte Carlo simulations, respectively, to obtain two delay standard deviations σ1 and σ2 corresponding to the two groups of input slew slew1 and slew2;

[0086] With the two groups of input slew slew1 and slew2 as independent variables, and the two delay standard deviations σ1 and σ2 as dependent variables, a straight line L1 is drawn through the two delay standard deviations σ1 and σ2, an expression of the straight line L1 is obtained, and the value of the delay standard deviation σ0 is substituted into the expression of the straight line L1 to obtain the value of the input slew at the fast-slow input boundary;

[0087] Output the delay standard deviation σ0 indexed by the input slew slew and the output load load min ; output the delay standard deviation σ1 indexed by the input slew slew1 and the output load load min ; and output the delay standard deviation σ2 indexed by the input slew slew2 and the output load load min , and establish a relationship model of the delay standard deviation of the slow input and the input slew, and the value of the input slew at the fast-slow input boundary through the three groups of output data.

[0088] The above-described detailed process of the relationship model of the delay standard deviation of the slow input and the input slew of the present application will be described below. Figure 2

[0089] Step 201: In the selected working environment, the input slew is selected as a step case, i.e. slew=0ps, and hspice simulation is performed under the output load load min =0.1fF, wherein the number of Monte Carlo is K, and the delay standard deviation σ0 under this condition is obtained, and the simulation overhead i=K;

[0090] Step 202: In the selected working environment, two groups of input slew slew1 and slew2 are selected as slow inputs, wherein the values of the input events slew1 and slew2 can be selected as any value in the range of 0.5*maximum input slew~maximum input slew, and the output load load min ​=0.1fF under hspice simulation, wherein the Monte Carlo number is K, the delay standard deviation σ1, σ2 corresponding to the input slew1, slew2 is obtained, and the simulation overhead i=2K;

[0091] Step 203, under the selected working environment, taking the input slew1, slew2 as the independent variable, and the delay standard deviation σ1, σ2 as the dependent variable, making a straight line L1 of the delay standard deviation σ1, σ2, obtaining the expression of the straight line L1, and substituting the value of the delay standard deviation σ0 into the expression of L1 to obtain the value of the input slew at the fast and slow input boundary ;

[0092] Step 204, under the selected working environment, under the condition of the output load load min =0.1fF, when the input slew is fast input, and the delay standard deviation σ=L1(slew) under the condition of the input slew is slow input, wherein L1 is the expression of the straight line L1, and slew is the independent variable;

[0093] Step 205, outputting the delay standard deviation σ0 indexed by the input slew slew=0 and the output load load min ; outputting the delay standard deviation σ1 indexed by the input slew slew1 and the output load load min ; and outputting the delay standard deviation σ2 indexed by the input slew slew2 and the output load load min , so as to establish the relationship model of the delay standard deviation σ and the input slew slew under the condition of slow input and the value of the input slew at the fast and slow input boundary under the selected working environment.

[0094] The process of establishing the relationship model of the delay standard deviation and the output load under the condition of fast input in the sub-threshold region or the super-threshold region is the same, and the process of establishing the relationship model of the delay standard deviation and the output load under the condition of fast input in the sub-threshold region or the super-threshold region specifically includes the following steps.

[0095] Selecting the input slew slew, and changing the output load load a , the value range of the output load load a is [0.5*maximum output load, maximum output load], and the corresponding delay standard deviation σ a is obtained by performing the Monte Carlo simulation for a preset number of times;

[0096] The output load loadmin , output load load a is the independent variable, and the delay standard deviation σ0, σ a is the dependent variable, and the delay standard deviation σ0, σ a is a straight line L2, and the expression of the straight line L2 is obtained, and the slope k0 of the straight line L2 is obtained;

[0097] output conversion time slew, output load load min is the index of the delay standard deviation σ0; output conversion time slew, output load load a is the index of the delay standard deviation σ a ;

[0098] The relationship model of the delay standard deviation and the output load in the sub-threshold region or the super-threshold region fast input is established by the two groups of output data.

[0099] The relationship model of the delay standard deviation and the output load in the full voltage domain fast input is established by the following Figure 3 and Figure 5 The relationship model of the delay standard deviation and the output load in the full voltage domain fast input is established by the following

[0100] As shown in Figure 3 , the relationship model of the delay standard deviation and the output load in the sub-threshold region fast input specifically includes the following steps.

[0101] Step 301, in the selected working environment, the input conversion time is selected as a step, that is, slew=0 ps, and a group of larger output load load a is selected, wherein the value of the output load load a may be selected as any value in the range of 0.5*maximum output load~maximum output load, hspice simulation is performed, wherein the Monte Carlo number is K, and the corresponding delay standard deviation σ a is obtained, and the simulation overhead i=K;

[0102] Step 302, in the selected working environment, the output load load min , load a is the independent variable, and the delay standard deviation σ0, σ a is the dependent variable, and the delay standard deviation σ0, σ a is a straight line L2, and the expression of the straight line L2 is obtained, and the slope k0 of the straight line L2 is obtained;

[0103] Step 303, in the selected working environment, in the fast input condition, that is, the value of the input conversion time is less than the delay standard deviation σ=L2(load), wherein L2 is the expression of the straight line L2, and the output load load is the independent variable;

[0104] Step 304, output the delay standard deviation σ0 indexed by the slew rate slew = 0 and the output load load min Step 304, output the delay standard deviation σ0 indexed by the slew rate slew = 0 and the output load load a Step 304, output the delay standard deviation σ0 indexed by the slew rate slew = 0 and the output load load a The relationship model of the delay standard deviation σ and the output load load in the fast input condition in the sub-threshold region under the selected working environment can be established by the output data.

[0105] As shown in Figure 5 , the relationship model of the delay standard deviation and the output load in the fast input condition in the super-threshold region specifically includes the following steps.

[0106] Step 501, in the selected working environment, select the step condition, i.e., the input transition time slew = 0 ps, and select a group of larger output loads load a , wherein the value of load a may be selected as any value in the range of 0.5*maximum output load~maximum output load, and hspice simulation is performed, wherein the Monte Carlo number is K, and the corresponding delay standard deviation σ a is obtained. The simulation overhead i = K in this step.

[0107] Step 502, in the selected working environment, take the output loads load min and load a as independent variables, and take the delay standard deviations σ0 and σ a as dependent variables, draw a straight line L2 through the delay standard deviations σ0 and σ a , and obtain the expression of the straight line L2, wherein the slope of the straight line L2 is k0.

[0108] Step 503, in the selected working environment, in the fast input condition, the delay standard deviation σ = L2(load), wherein L2 is the expression of the straight line L2, and the output load load is the independent variable.

[0109] Step 504, output the delay standard deviation σ0 indexed by the slew rate slew = 0 and the minimum output load load min Step 304, output the delay standard deviation σ0 indexed by the slew rate slew = 0 and the output load load a Step 304, output the delay standard deviation σ0 indexed by the slew rate slew = 0 and the output load load a The relationship model of the delay standard deviation σ and the output load load in the fast input condition in the super-threshold region under the selected working environment can be established by the output data.

[0110] The relationship model of the delay standard deviation and the output load in the slow input condition in the sub-threshold region specifically includes the following steps.

[0111] slew b , based on the expression of the straight line L1, the input slew slew b , the output load load min , the corresponding delay standard deviation

[0112] The delay standard deviation is substituted into the expression of the straight line L2 to obtain the value of the output load at the boundary of the large output load .

[0113] The relationship model of the delay standard deviation and the output load under the slow input in the sub-threshold region is established.

[0114] The detailed process of establishing the relationship model of the delay standard deviation and the output load under the slow input in the sub-threshold region by the application will be described below. Figure 4 The detailed process of establishing the relationship model of the delay standard deviation and the output load under the slow input in the sub-threshold region by the application will be described below.

[0115] Step 401, under the selected working environment, the input slew slew at the boundary of the fast and slow inputs can be obtained in step 203. b , that is, the input slew slew , the expression of the straight line L1 obtained in step 204 is substituted into the value of the selected input slew slew b , so that the delay standard deviation b , the output load load min under the input slew slew slew b and the output load load

[0116] Step 402, under the selected working environment, the value of is substituted into the expression of the straight line L2 to obtain the value of the output load at the boundary of the small and large output loads, that is, the output load at the boundary of the large and small output loads .

[0117] Step 403, under the selected working environment, when the output load load , the delay standard deviation , when , σ=L2(load), wherein L2 is the expression of the straight line L2, and load is the independent variable; by this method, the relationship model of the delay standard deviation σ and the output load load under the selected working environment, the slow input and the sub-threshold region can be established.

[0118] The establishment of a model relating delay standard deviation to output load under slow input conditions in the over-threshold region includes the following steps.

[0119] The input transition time slew is randomly selected as the value of the slow input. c ;

[0120] Based on the expression for line L1, the input transition time slew is obtained. c Output load min Corresponding delay standard deviation

[0121] Select input conversion time slew c Output load c Output load c The value range is [0.5 * maximum output load, maximum output load]. A preset number of Monte Carlo simulations are performed to obtain the delay standard deviation σ. c ;

[0122] Output load c As the independent variable, after time delay, the standard deviation σ c Draw a straight line L3 with slope k0;

[0123] Delay standard deviation Substituting into line L3, we obtain the output load as the independent variable. The value of the output load As input conversion time slew c The minimum load boundary;

[0124] Select input conversion time as slew c Output load d Output load d The value range is [output load] min Output load Perform a preset number of Monte Carlo simulations to obtain the delay standard deviation σ. d ;

[0125] Output load min load d As the independent variable, after time delay, the standard deviation σ d Draw line L4, and calculate the output load at the intersection of line L3 and line L4 as the independent variable. The value of the output load As input conversion time slew c Maximum load boundary;

[0126] Calculate input conversion time slew cintermediate load boundary

[0127] The output load is obtained through the expression of line L4. Delay standard deviation at The value of is obtained by using the expression for line L3 to obtain the output load. standard deviation of delay The value;

[0128] slew during input conversion time c Under the condition of output load As the independent variable, with time delay standard deviation The dependent variable is the standard deviation after time delay. Draw line L5 to obtain the expression for line L5;

[0129] The output is slew of the input conversion time. c Output load min Standard deviation of index latency The output is slew of the input conversion time. c Output load d The standard deviation of the delay for the index σ d The output is slew of the input conversion time. c Output load c The standard deviation of the delay for the index σ c ;

[0130] The input-to-transition time in the over-threshold region is established using the output data. c The corresponding relationship model between delay standard deviation and output load;

[0131] Select any slow input mode input conversion time slew e slew input conversion time e Substituting into the expression for line L1, we obtain the input transition time slew. e Output load min Corresponding delay standard deviation

[0132] When the output load is the output load min In this case, calculate the input conversion time slew e With input conversion time slew c Draw a straight line L3` from the difference Δ of the delay standard deviation, where L3` = L3 + Δ / 2; draw a straight line L4` from the difference Δ, where L4` = L4 + Δ.

[0133] Input conversion time slew e The standard deviation of the delay Substituting the value into the expression for line L3', we obtain the output load. The value of slew is used as the input conversion time. e The minimum load boundary;

[0134] Calculate the output load at the intersection of lines L3' and L4'. The value of slew is used as the input conversion time. e Maximum load boundary;

[0135] Select input conversion time slew e intermediate load boundary The output load is obtained through the expression of line L4'. standard deviation of delay The value of is obtained by using the expression for the line L3' to obtain the output load. standard deviation of delay The value;

[0136] Select input conversion time slew e To output load As the independent variable, with time delay standard deviation The dependent variable is the standard deviation after time delay. Draw line L5' and obtain the expression for line L5';

[0137] Establish a relationship model between the over-threshold region, the delay standard deviation under slow input conditions, and the output load.

[0138] The following is combined with Figure 6 The specific steps for establishing a model relating the over-threshold region, the standard deviation of delay under slow input conditions, and the output load are explained in detail.

[0139] Step 601: Under the selected working environment, the input transition time at the fast and slow input boundary can be obtained in step 203. Select an input transition time slew for slow input conditions c (i.e., input conversion time) As a reference condition for the over-threshold region and slow input cases, the expression of line L1 obtained in step 204 is substituted into the selected input transition time slew. c The value of slew can be used to quickly obtain the input conversion time. c The output load is load min Corresponding delay standard deviation

[0140] Step 602: In the selected working environment, input the conversion time slew. c In this case, select a larger output load. cThe output load is... c The value can be any value within the range of 0.5 * maximum output load to maximum output load. Perform an Hspice simulation, where the Monte Carlo simulation is K, and obtain the corresponding delay standard deviation σ. c The simulation cost for this step is i = K;

[0141] Step 603: Under the selected working environment, output load. c The independent variable is the standard deviation σ due to time delay. c Draw a straight line L3 with slope k0 obtained in step 502, and obtain the expression for the straight line L3;

[0142] Step 604: In the selected working environment, input the conversion time slew. c In this case, the standard deviation of the delay will be Substituting the value into the expression for line L3, we obtain the output load of the independent variable. The value of slew is used as the input conversion time. c The minimum load boundary;

[0143] Step 605: In the selected working environment, enter the conversion time slew. c In this case, select a smaller set of output loads. d The output load is... d The value can be selected as the minimum load. min Minimum Boundary Load Perform Hspice simulations for any value within the range, where the Monte Carlo simulation is of degree K, and obtain the corresponding delay standard deviation σ. d The simulation cost for this step is i = K;

[0144] Step 606: In the selected working environment, enter the conversion time slew. c In the case of output load min load d As the independent variable, with time delay standard deviation σ d The dependent variable is the standard deviation after time delay. σ d Draw line L4 to obtain its expression, and calculate the output load of the independent variable at the intersection of lines L3 and L4. The value of slew is used as the input conversion time. c The corresponding maximum load boundary;

[0145] Step 607: In the selected working environment, enter the conversion time slew. c In this case, make intermediate load boundaries in The expression for line L4 can be quickly obtained. standard deviation of delay The value of can be quickly obtained using the expression for line L3. standard deviation of delay The value;

[0146] Step 608: In the selected working environment, input the conversion time slew. c In the case of output load As the independent variable, with time delay standard deviation The dependent variable is the standard deviation after time delay. Draw line L5 to obtain the expression for line L5;

[0147] Step 609: In the selected working environment, input the conversion time slew. c In the case of output load When the delay standard deviation σ = L4(load), where L4 is the expression for the straight line L4, and the output load load is the independent variable; when When the delay standard deviation σ = L5(load), where L5 is the expression for the straight line L5, and the output load is the independent variable; when the output load When the delay standard deviation σ = L3(load), where L3 is the expression for the straight line L3 and the output load load is the independent variable;

[0148] Step 610: Output the input conversion time slew c Minimum output load min Standard deviation of index latency The output is slew of the input conversion time. c The selected smaller output load d The standard deviation of the delay for the index σ d The output is slew of the input conversion time. c The selected larger output load c The standard deviation of the delay for the index σ c This output data can be used to establish the threshold range and input conversion time slew under the selected working environment. c The relationship model between delay standard deviation σ and output load.

[0149] Step 611: Under the selected working environment, input the conversion time slew for any slow input condition. e (i.e., input conversion time) Next, substitute the expression for line L1 obtained in step 204 into the selected slew...e The value can be used to quickly obtain the input conversion time as slew. e The output load is load min The standard deviation of delay

[0150] Step 612: Under the selected operating environment and with minimal output load, perform arbitrary slow input conditional input transition time slew. e Slew (selected slow input reference input conversion time) c The difference Δ in the standard deviation of the delay, where Draw a straight line L3', where L3' = L3 + Δ / 2; Draw a straight line L3', where L4' = L4 + Δ;

[0151] Step 613: In the selected working environment, input the conversion time slew. e In this case, the standard deviation of the delay will be Substituting the value of into the expression for line L3', we obtain the independent variable. The value of slew is used as the input conversion time. e The corresponding minimum load boundary; and calculate the independent variable at the intersection of lines L3' and L4'. The value is used as input, and the conversion time is slew. e The corresponding maximum load boundary;

[0152] Step 614: In the selected working environment, enter the conversion time slew. e In this case, make intermediate load boundaries in The expression for line L4' can be quickly obtained. standard deviation of delay The value of can be quickly obtained using the expression for line L3'. standard deviation of delay The value;

[0153] Step 615: In the selected working environment, input the conversion time slew. e In the case of output load As the independent variable, with time delay standard deviation The dependent variable is the standard deviation after time delay. Draw line L5' and obtain the expression for line L5';

[0154] Step 616: In the selected working environment, enter the conversion time slew. e In the case of output load When t = L4`(load), the delay standard deviation σ = L4`(load), wherein L4` is an expression of the straight line L4`, and load is the independent variable; when When t = L5`(load), the delay standard deviation σ = L5`(load), wherein L5` is an expression of the straight line L5`, and output load load is the independent variable; when When t = L3`(load), the delay standard deviation σ = L3`(load), wherein L3` is an expression of the straight line L3`, and load is the independent variable. By this method, the relationship model of the delay standard deviation σ and the output load load in the super-threshold region and the slow input condition under the selected working environment can be established.

[0155] The present application also protects a computer readable storage medium for storing a computer program which, when executed, performs the above-mentioned method for representing the timing characteristics of the full voltage domain combinational logic unit.

[0156] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement within the spirit and principle of the present application shall be included in the protection scope of the present application. Those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the present application. In addition, the features and embodiments can be modified to adapt to specific conditions and materials under the guidance of the present application without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the protection scope of the present application.

Claims

1. A method of characterizing timing features of a combinational logic unit, comprising: The method comprises: setting a working environment and working parameters of a combinational logic unit to be characterized; selecting an output load load under the working environment min , the output load load min is a preset minimum load, and the input conversion time is changed to perform a preset number of Monte Carlo simulations to establish a relationship model of delay standard deviation and input conversion time, and the value of the input conversion time at the fast and slow input boundary is obtained from the relationship model of delay standard deviation and input conversion time; judging whether the combinational logic unit works in a sub-threshold region or a super-threshold region; selecting an input slew time with a value of a fast input and changing an output load in the sub-threshold region or the super-threshold region to establish a relationship model of a delay standard deviation and the output load under the fast input in the sub-threshold region or the super-threshold region by performing a preset number of Monte Carlo simulations; selecting an input slew time with a value of a slow input and changing an output load in the sub-threshold region or the super-threshold region to establish a relationship model of a delay standard deviation and the output load under the slow input in the sub-threshold region or the super-threshold region by performing a preset number of Monte Carlo simulations; the value of the input slew time with the value of the slow input is greater than a value of an input slew time at a fast-slow input boundary; integrating all the relationship models of the sub-threshold region or the super-threshold region to obtain a characterization model of timing characteristics of the combinational logic unit; the relationship model of the delay standard deviation and the input slew time, and the value of the input slew time at the fast-slow input boundary are obtained by the following steps: selecting an output load load min and the input slew time slew with the value of the step case, performing the Monte Carlo simulation for a preset number of times to obtain the delay standard deviation σ0; Randomly select two groups of values as slow input slew1, slew2, select output load load min , respectively, a predetermined number of Monte Carlo simulation, get two groups of input slew1, slew2 corresponding to two delay standard deviation σ1, σ2; taking two groups of input slew times slew1 and slew2 as independent variables, taking two delay standard deviations σ1 and σ2 as dependent variables, performing a straight line L1 on the two delay standard deviations σ1 and σ2 to obtain an expression of the straight line L1, and substituting a value of a delay standard deviation σ0 into the expression of the straight line L1 to obtain the value of the input slew time at the fast-slow input boundary; Output slew, output load min Indexing delay standard deviation σ0; output slew1, output load min Indexing delay standard deviation σ1; output slew2, output load min Indexing delay standard deviation σ2, a relationship model between the slow input delay standard deviation and the input slew is established by the three sets of output data, and the value of the input slew at the boundary of the fast and slow inputs.

2. The method of claim 1, wherein: the step of establishing the relationship model of the delay standard deviation and the output load under the fast input in the sub-threshold region or the super-threshold region comprises: selecting the input slew and varying the output load load a , the output load load a is in the range [0.5*maximum output load, maximum output load], and performing a corresponding number of Monte Carlo simulations to obtain a corresponding delay standard deviation σ a ; with the output load load min , the output load load a as the independent variable, the delay standard deviation σ0, σ a as the dependent variable, a straight line L2 is drawn through two delay standard deviations σ0, σ a , the expression of the straight line L2 is obtained, and the slope k0 of the straight line L2 is obtained; Output slew, output load min Indexing delay standard deviation σ0; output slew, output load a Indexing delay standard deviation σ a ; establishing a relationship model of the delay standard deviation and the output load under the fast input in the sub-threshold region or the super-threshold region by two groups of output data.

3. The method of claim 2, wherein the step of determining the timing characteristics of the combinational logic elements comprises the steps of: determining the delay of each of the combinational logic elements; and determining the skew of each of the combinational logic elements. the step of establishing the relationship model of the delay standard deviation and the output load under the slow input in the sub-threshold region comprises: slew time of the input conversion is randomly selected as a slow input b , based on the expression of the straight line L1, the slew time of the input conversion is obtained b , the output load load min The corresponding delay standard deviation the delay standard deviation Substituting into the expression for the straight line L2 gives the value of the output load at the output load boundary of the size establishing a relationship model of the delay standard deviation and the output load under the slow input in the sub-threshold region.

4. The method of claim 2, wherein the step of determining the timing characteristics of the combinational logic elements comprises the steps of: determining the delay of each of the combinational logic elements; and determining the skew of each of the combinational logic elements. the step of establishing the relationship model of the delay standard deviation and the output load under the slow input in the super-threshold region comprises: randomly selected input transition time slew for slow input c ; Based on the expression of the straight line L1, an input slew time slew c , an output load load min a corresponding delay standard deviation Select input conversion time slew c , output load load c , the output load load c The value range is [0.5*maximum output load, maximum output load], and the corresponding preset number of Monte Carlo simulation is carried out to obtain the delay standard deviation σ c ; with the output load load c as the argument, the delay standard deviation σ c with the slope k0 as the straight line L3; Delay standard deviation Substituting into line L3, we obtain the output load as the independent variable. The value of the output load As input conversion time slew c The minimum load boundary; Select the input conversion time as slew c , the output load load d , the output load load d The value range is [output load load min , output load ] is simulated by a corresponding preset number of Monte Carlo simulation, and the delay standard deviation σ d ; Output load min load d As the independent variable, after time delay, the standard deviation σ d Draw line L4, and calculate the output load at the intersection of line L3 and line L4 as the independent variable. The value of the output load As input conversion time slew c Maximum load boundary; Computing input slew time c of intermediate load boundaries The value of the standard deviation of the delay at the output load is obtained by the expression of the straight line L3 The value of the standard deviation of the delay at the output load is obtained by the expression of the straight line L3 The value of the standard deviation of the delay at the output load Under the condition of input slew c , taking output load as the independent variable and taking delay standard deviation as the dependent variable, a straight line L5 is drawn through delay standard deviation , and an expression of the straight line L5 is obtained; output slew time to input c output load min delay standard deviation indexed by output slew time to input c output load d delay standard deviation indexed by d output slew time to input c output load c delay standard deviation indexed by c ; Slew rate of input transition time through data over threshold c Corresponding delay standard deviation and output load relationship model selecting an input slew time under any slow input e , input slew time e , input slew time e , output load min , corresponding delay standard deviation In the case where the output load is the output load load min The input slew time slew e is calculated as the difference Δ between the delay standard deviation of the input slew time slew c and the delay standard deviation of the output slew time slew , where L3` = L3 + Δ / 2; and a straight line L4` is drawn, where L4` = L4 + Δ. Select input conversion time slew e The standard deviation of the delay Substituting the value into the expression for line L3', we obtain the output load. The value of slew is used as the input conversion time. e Find the minimum load boundary; and calculate the output load at the intersection of lines L3' and L4'. The value of slew is used as the input conversion time. e Maximum load boundary; select input slew e , intermediate load boundary the value of the output load at the point where the expression of the straight line L4` is obtained the value of the standard deviation of the delay at the point where the expression of the straight line L3` is obtained the value of the output load at the point where the expression of the straight line L4` is obtained the value of the standard deviation of the delay at the point where the expression of the straight line L3` is obtained the value of the output load at the point where the expression of the straight line L4` is obtained Select input slew e , with output load , with delay standard deviation , with delay standard deviation , and obtain an expression of the straight line L5`; establishing a relationship model of the delay standard deviation and the output load under the slow input in the super-threshold region.

5. The method of characterizing the timing characteristics of a combinational logic unit according to any one of claims 1 to 4, characterized in that, the working parameters comprise at least one of a type, a size, a temperature, a process angle and a working voltage of the combinational logic unit.

6. The method of characterizing the timing characteristics of a combinational logic unit according to any one of claims 1 to 4, characterized in that, the preset minimum output load is 0.1 fF.

7. The method of claim 1, wherein: the number of times of performing the Monte Carlo simulation in the sub-threshold region is at least 4 times the preset number.

8. The method of claim 1, wherein: the number of times of performing the Monte Carlo simulation in the super-threshold region is at least 6 times the preset number.

9. A computer readable storage medium for storing a computer program, characterized in that, the computer program runs to perform the characterization method of the timing characteristics of the combinational logic unit according to any one of claims 1 to 6.

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