A method for improving the antistatic ability of fast recovery diodes

Abstract

The present invention discloses a method for improving the antistatic capability of a fast recovery diode, which belongs to the field of semiconductor manufacturing process technology. It aims to solve the defective technical problem in the prior art that after platinum doping, the effective concentration of the device will be reduced due to the compensation doping effect, resulting in an increase in the on-resistance of the base region, which is not conducive to the discharge of electrostatic current and causes a decrease in the electrostatic capability of the device. The present invention has antistatic holes in the main junction area, which can increase the perimeter of the PN junction and provide an electrostatic discharge channel. The contact hole is used to realize the interconnection between the metal connection and the PN junction, and the platinum doped area realizes minority carrier lifetime control and improves the switching speed of the device. After the anode is formed, it is subsequently connected to the packaging shell through aluminum wire, and finally the antistatic capability of the fast recovery diode is improved. Secondly, by designing the area of ​​the main junction area, it is beneficial to the heat dissipation of the device and improves the reliability; then, by adding 8 antistatic holes of a certain size, the effective PN junction is increased by about 1 times, effectively improving the electrostatic discharge capability.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing technology and relates to a method for improving the antistatic capability of a fast recovery diode. Background Art

[0002] Fast recovery diodes utilize a silicon-based epitaxial PIN structure. To increase switching speed, platinum is introduced into the device to form appropriately distributed recombination centers, effectively reducing the minority carrier lifetime. However, platinum doping reduces the effective concentration of the device due to compensatory doping, increasing the base region's on-resistance, hindering the discharge of electrostatic current and reducing the device's electrostatic capacity. Summary of the Invention

[0003] The purpose of the present invention is to solve the defective technical problem in the prior art that after platinum doping, the effective concentration of the device will be reduced due to the compensating doping effect, resulting in an increase in the base region on-resistance, which is not conducive to the discharge of electrostatic current and causes the electrostatic capacity of the device to decrease, and to provide a method for improving the anti-static ability of fast recovery diodes.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions:

[0005] The present invention proposes a method for improving the antistatic capability of a fast recovery diode, comprising the following steps:

[0006] S1. Forming an N-type epitaxial layer on an N-type silicon substrate, performing photolithography on a dielectric layer of the silicon N-type epitaxial layer, and corroding or etching the dielectric layer after photolithography to form a main junction region and a terminal region; wherein the main junction region has an antistatic hole;

[0007] S2, performing P-type ion implantation and high-temperature annealing in the main junction region and the terminal region to form a P-type doped region and a P-type dielectric layer;

[0008] S3, forming a contact hole region on the P-type dielectric layer by photolithography and etching, forming a platinum layer on the back side of the N-type silicon substrate, and annealing the platinum layer at a high temperature to form a platinum-doped region;

[0009] S4. Etch away the excess platinum layer on the back of the N-type silicon substrate, precipitate or evaporate metal on the front of the N-type silicon substrate, and form an anode through annealing after photolithography and etching; deposit on the back of the N-type silicon substrate to form a cathode, thereby obtaining a fast recovery diode with antistatic capability.

[0010] Preferably, a dielectric layer is formed on the surface of the N-type epitaxial layer by oxidation or precipitation; the dielectric layer is a SiO2 layer.

[0011] Preferably, the resistivity of the N-type silicon substrate is 0.001 Ω˙cm to 0.004 Ω˙cm.

[0012] Preferably, the resistivity of the N-type epitaxial layer is 5Ω˙cm to 6Ω˙cm.

[0013] Preferably, the main junction region has an area of ​​2900 μm×2900 μm.

[0014] Preferably, there are 8 antistatic holes, and the size of the antistatic holes is 453 μm×453 μm.

[0015] Preferably, the impurity implanted by the P-type ions is boron, the implantation energy is 50keV-90keV, and the implantation dose is 1E14-1E16 per square centimeter.

[0016] Preferably, the thickness of the evaporated platinum is 30±3 nm.

[0017] Preferably, the metal of the anode is Al.

[0018] Preferably, the metal of the cathode is Cr, Ni or Au.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention proposes a method for improving the antistatic capability of a fast recovery diode. The core of the method lies in the use of an antistatic hole design structure to increase the PN junction perimeter, providing more channels for static discharge, and the device's antistatic capability can reach over 4000V. Specifically, antistatic holes are provided in the main junction region to increase the PN junction perimeter and provide static discharge channels. Contact holes are used to interconnect metal wires with the PN junction, and platinum-doped regions control minority carrier lifetimes, increasing device switching speeds. After the anode is formed, it is subsequently connected to the packaging shell via aluminum wire, ultimately improving the antistatic capability of the fast recovery diode.

[0021] Furthermore, the resistivity of the N-type silicon substrate is set to be relatively small, set to 0.001Ω˙cm to 0.004Ω˙cm, which reduces the contact resistance and lowers the forward voltage drop.

[0022] Furthermore, the resistivity of the N-type epitaxial layer is in the range of 5Ω˙cm to 6Ω˙cm, ensuring that the device withstands a voltage of 200V to 300V.

[0023] Furthermore, according to the current capability of 3A / mm 2 According to the principle of , the main junction area is designed to be 2900μm×2900μm, which is beneficial to device heat dissipation and improve reliability.

[0024] Furthermore, the original PN junction circumference is 4x2900μm, and 8 453μm × 453μm anti-static holes are added, which increases the effective PN junction by about 1 times, effectively improving the electrostatic discharge capability.

[0025] Furthermore, the impurity of P-type ion implantation is boron, the implantation energy is 50keV-90keV, and the implantation dose is 1E14-1E16 per square centimeter, which can increase the concentration of majority carriers emitted by the main junction and utilize the large injection modulation effect of the PN junction to effectively reduce the forward voltage drop of the device.

[0026] Furthermore, the device platinum doping concentration reaches about 10 15 pieces / cm 2 The minority carrier lifetime is effectively controlled, and the platinum layer thickness cannot be too thick, otherwise excessive platinum doping will lead to increased leakage. Using aluminum as the electrode is conducive to process implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 This is a flowchart of the steps for improving the antistatic capability of the recovery diode according to the present invention.

[0029] Figure 2 The present invention is based on photolithographic patterns.

[0030] Figure 3 The present invention is based on the injection and push-through diagram.

[0031] Figure 4 This is the photolithography contact hole diagram of the present invention.

[0032] Figure 5 This is the platinum doping diagram of the present invention.

[0033] Figure 6 This is the platinum wiring photolithography pattern of the present invention.

[0034] Figure 7 The front and back metallization diagrams of the N-type silicon substrate of the present invention.

[0035] Among them: 1-terminal region; 2-main junction; 3-dielectric layer of epitaxial layer; 4-doped layer; 5-dielectric layer; 6-contact hole region; 7-platinum doped region; 8-anode; 9-cathode. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0039] In the description of the embodiments of the present invention, it should be noted that if the terms "upper," "lower," "horizontal," "inner," etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the inventive product is typically placed when in use. These terms are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0041] In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0042] The present invention is described in further detail below with reference to the accompanying drawings:

[0043] The present invention provides a method for improving the antistatic ability of a fast recovery diode, such as Figure 1 As shown, the following steps are included:

[0044] S1. Forming an N-type epitaxial layer on an N-type silicon substrate, performing photolithography on a dielectric layer 3 of the silicon N-type epitaxial layer, and corroding or etching the dielectric layer 3 after photolithography to form a main junction region 2 and a terminal region 1; wherein the main junction region 2 has an antistatic hole;

[0045] S2, performing P-type ion implantation and high-temperature annealing in the main junction region 2 and the terminal region 1 to form a P-type doped region 4 and a P-type dielectric layer 5;

[0046] S3, forming a contact hole region 6 on the P-type dielectric layer 5 by photolithography and etching; forming a platinum layer on the back side of the N-type silicon substrate, and annealing the platinum layer at a high temperature to form a platinum-doped region 7;

[0047] S4. Etch away the excess platinum layer on the back of the N-type silicon substrate, precipitate or evaporate metal on the front of the N-type silicon substrate, and form an anode 8 by annealing after photolithography and etching; deposit on the back of the N-type silicon substrate to form a cathode 9, thereby obtaining a fast recovery diode with antistatic capability.

[0048] like Figure 2-Figure 7 The specific steps are as follows:

[0049] 1) An N-type epitaxial layer is formed on an N-type silicon substrate. A dielectric layer 3 of a certain thickness is formed on the surface of the N-type epitaxial layer by oxidation or precipitation. The dielectric layer 3 of the silicon N-type epitaxial layer is photolithographically processed. The photolithographic dielectric layer 3 is then etched or corroded to form a main junction 2 and a terminal region 1. The main junction region 2 has an antistatic hole, and the dielectric layer 3 is a SiO2 layer.

[0050] The resistivity of the N-type silicon substrate is between 0.001Ω˙cm and 0.004Ω˙cm. Setting the resistivity of the N-type silicon substrate to a relatively low value, between 0.001Ω˙cm and 0.004Ω˙cm, reduces contact resistance and lowers forward voltage drop.

[0051] The resistivity of the N-type epitaxial layer is in the range of 5Ω˙cm to 6Ω˙cm, ensuring that the device withstand voltage is between 200V and 300V.

[0052] According to the current capability 3A / mm 2 According to the principle of , the area of ​​the main junction region 2 is designed to be 2900μm×2900μm, which is beneficial to the heat dissipation of the device and improves the reliability.

[0053] The original PN junction circumference is 4x2900μm, and 8 453μm × 453μm anti-static holes are added, which increases the effective PN junction by about 1 times, effectively improving the electrostatic discharge capability.

[0054] 2) Performing P-type ion implantation and high-temperature annealing in the main junction region 2 and the terminal region 1 to form a P-type doped region 4 and a P-type dielectric layer 5;

[0055] The impurity of P-type ion implantation is boron, the implantation energy is 50keV-90keV, and the implantation dose is 1E14-1E16 per square centimeter. It can increase the concentration of majority carriers emitted by the main junction and utilize the large injection modulation effect of the PN junction to effectively reduce the forward voltage drop of the device.

[0056] 3) Photolithography and etching are performed on the P-type dielectric layer 5 to form a contact hole region 6;

[0057] 4) After forming a platinum layer of a certain thickness on the back side of the N-type silicon substrate, the platinum layer is annealed at a high temperature to form a platinum-doped region 7;

[0058] The platinum doping concentration of the device reaches about 10 15 pieces / cm 2 Effectively control the minority carrier lifetime. At the same time, the thickness of the platinum layer cannot be too thick, otherwise too much platinum doping will lead to increased leakage current; among them, the thickness of the evaporated platinum is 30±3nm.

[0059] 5) Etch away the excess platinum layer on the back of the N-type silicon substrate, deposit or evaporate a certain thickness of metal on the front of the N-type silicon substrate, and form an anode 8 by annealing after photolithography and etching; deposit on the back of the N-type silicon substrate to form a cathode 9, completing the production of the fast recovery diode.

[0060] The metal of the anode 8 is Al, and the metal of the cathode 9 is Cr, Ni or Au. Using aluminum as the electrode is conducive to process implementation.

[0061] This invention proposes a method for improving the antistatic capability of fast recovery diodes. This method addresses the existing technical problem that platinum doping reduces the effective concentration of the device due to compensatory doping, resulting in an increase in base region on-resistance, hindering the discharge of static current and reducing the device's antistatic capability. By employing an antistatic hole design, the PN junction perimeter is increased, providing more channels for static discharge, and the device's antistatic capability can reach over 4000V.

[0062] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for improving the antistatic ability of a fast recovery diode, characterized in that: The following steps are involved: S1. Forming an N-type epitaxial layer on an N-type silicon substrate, performing photolithography on a dielectric layer (3) of the silicon N-type epitaxial layer, and corroding or etching the dielectric layer (3) after photolithography to form a main junction region (2) and a terminal region (1); wherein eight discrete hole-shaped regions are formed in the main junction region (2), each hole-shaped region having a size of 453 μm×453 μm and uniformly distributed in the main junction region (2); S2, performing P-type ion implantation and high-temperature annealing in the main junction region (2) and the terminal region (1) to form a P-type doped region (4); an additional PN junction is formed at the edge of the hole-shaped region due to the interface between the P-type doped region (4) and the N-type epitaxial layer, forming an antistatic hole; S3, forming a contact hole region (6), forming a platinum layer on the back side of the N-type silicon substrate, and annealing the platinum layer at a high temperature to form a platinum doped region (7); S4, etching away the excess platinum layer on the back side of the N-type silicon substrate, depositing or evaporating metal on the front side of the N-type silicon substrate, and annealing after photolithography and etching to form an anode (8); depositing on the back side of the N-type silicon substrate to form a cathode (9), thereby obtaining a fast recovery diode with antistatic capability; The impurity of the P-type ion implantation is boron, the implantation energy is 50keV-90keV, and the implantation dose is 1E14-1E16 per square centimeter.

2. The method for improving the antistatic capability of a fast recovery diode according to claim 1, wherein: A dielectric layer (3) is formed on the surface of the N-type epitaxial layer by oxidation or deposition; the dielectric layer (3) is a SiO2 layer.

3. The method for improving the antistatic capability of a fast recovery diode according to claim 1, wherein: The resistivity of the N-type silicon substrate is between 0.001Ω˙cm and 0.004Ω˙cm.

4. The method for improving the antistatic capability of a fast recovery diode according to claim 1, wherein: The resistivity of the N-type epitaxial layer is between 5Ω˙cm and 6Ω˙cm.

5. The method for improving the antistatic capability of a fast recovery diode according to claim 1, wherein: The area of ​​the main junction region (2) is 2900 μm × 2900 μm.

6. The method for improving the antistatic capability of a fast recovery diode according to claim 1, characterized in that: The thickness of the evaporated platinum is 30±3nm.

7. The method for improving the antistatic capability of a fast recovery diode according to claim 1, characterized in that: The metal of the anode (8) is Al.

8. The method for improving the antistatic capability of a fast recovery diode according to claim 1, wherein: The metal of the cathode (9) is Cr, Ni or Au.

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