A semiconductor device with controllable emission efficiency and a manufacturing method thereof

Abstract

The application provides a semiconductor device with controllable emission efficiency and a manufacturing method thereof. The semiconductor device comprises a first doped region, a second doped region and a third doped region. The first doped region is connected with a cathode and the second doped region. The third doped region is connected with an anode and the second doped region. The doping type of the first doped region is different from that of the second doped region. The doping type of the third doped region is different from that of the second doped region. The third doped region comprises a high doped layer and a low doped layer. The low doped layer is connected with the second doped region. The high doped layer is connected with the anode. The high doped layer is non-uniformly doped to form a local isolation region. The semiconductor device with controllable emission efficiency and the manufacturing method thereof can flexibly adjust the anode emission efficiency of devices such as IGCT by changing the structure of local doping.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor device with controllable emission efficiency and a manufacturing method thereof. BACKGROUND

[0002] The development of distributed energy promotes the development of direct current power grids. Compared with alternating current power grids, direct current power transmission and distribution grids have achieved technical and economic advantages in many fields. Power electronic devices, as the core components, have developed rapidly in recent years.

[0003] In many working conditions, the device needs to have a reverse blocking (i.e., reverse blocking) capability, such as the use of bidirectional pressure-bearing thyristors in H-LCC (hybrid line commutated converter) and the use of IGBT (Insulated Gate Bipolar Transistor) and diode series in circuit breakers to achieve reverse voltage resistance. Reverse blocking integrated gate commutated thyristor (RB-IGCT) is a fully controlled device with forward current and bidirectional blocking capability, which can eliminate the series diode, reduce the number of devices, save costs, and reduce losses, and has significant advantages in current source converters, bidirectional solid-state circuit breakers, and other applications.

[0004] Traditional asymmetric devices (such as IGCT) change the electric field distribution by setting a buffer layer or a field stop layer, and the structure and internal electric field distribution thereof are as shown in Figure 1 . Under the condition of ensuring the same withstand voltage, the buffer layer can make the electric field distribution shape into a trapezoidal shape, reducing the overall chip thickness and thus reducing parameters such as on-state voltage drop, which belongs to the punch-through structure.

[0005] The structure of a traditional symmetric device (such as IGCT) and its internal electric field distribution are as shown in Figure 2 . The structure on both sides is symmetrical, which can achieve bidirectional voltage resistance capability. The reverse blocking device cannot use the buffer layer structure in Figure 1 , because if the PN junction on both sides is highly doped, the electric field distribution is concentrated on both sides of the PN junction, and when the peak electric field strength exceeds the critical electric field strength, the PN junction will be avalanche breakdown at a very low voltage.

[0006] In high-voltage direct current application scenarios, the blocking voltage level of the switching device needs to be as high as possible, and the leakage current needs to be as small as possible. Smaller leakage current not only reduces the system loss, but also improves the voltage resistance capability of the device, increases the maximum junction temperature, and thus increases the current-carrying capacity of the device.

[0007] The longitudinal doping structure of the IGCT device is shown in FIG. 3(a) and FIG. 3(b). The device includes a first doped region, a second doped region, and a third doped region, and often an emitter structure in the first doped region, which can be ignored when considering the blocking of the device. The first doped region is connected to the cathode and the second doped region, and the third doped region is connected to the anode and the second doped region. If the first doped region of the device is P-type doped, the second doped region is N-type doped, and the third doped region is P-type doped, the anode of the device can withstand the voltage of the first PN junction between the first doped region and the second doped region; and the anode of the device can withstand the voltage of the second PN junction between the second doped region and the third doped region.

[0008] As shown in FIG. 3(a), the third doped region of the device structure, that is, the anode structure, is relatively thick, so that the device generally has bidirectional voltage resistance, that is, the first PN junction and the second PN junction have comparable voltage resistance, and such a device is also called a symmetric device; as shown in FIG. 3(b), the third doped region of the structure, that is, the anode structure, is relatively thin, generally less than 10 um, so that the voltage resistance of the second PN junction is much smaller than that of the first PN junction, and such a device is also called an asymmetric device.

[0009] In practical applications, high-voltage reverse blocking devices face two problems:

[0010] 1. If a symmetric structure is directly used, the base region concentration on the cathode side is limited by the blocking of the gate cathode, and the low emission efficiency on the anode side increases the voltage drop of the device and reduces the current flow capacity;

[0011] 2. If the single-side doping concentration on the anode side is increased, the forward leakage current is significantly increased, which degrades the blocking of the device.

[0012] Patent CN210956682U proposes a thyristor with anode short-circuit points, which sets anode short-circuit points and cathode short-circuit points in the thyristor structure. Both the anode short-circuit points and the cathode short-circuit points penetrate the other doped layer. As a reverse blocking device, if the anode side adds short-circuit points, the anode side electrode cannot be a whole surface, which is complex in process and affects the voltage drop and thermal resistance.

[0013] Patent application CN101047205A proposes a design method of an injection efficiency controllable gate commutated thyristor IEC-GCT. An oxide layer is attached to the anode ohmic contact, so that the n+ short-circuit region becomes a floating region, that is, the silicon wafer of the short-circuit region has no direct ohmic contact with the electrode. The short-circuit point also penetrates the other doped layer, although the injection efficiency can be controlled, but the structure and process are complex.

[0014] Therefore, there is an urgent need for a reverse blocking device which is easy to process, has low on-state voltage drop, and small leakage current. SUMMARY

[0015] To solve the above problems, the application provides a semiconductor device with controllable emission efficiency, comprising a first dopant region, a second dopant region and a third dopant region, the first dopant region being connected with a cathode and the second dopant region, the third dopant region being connected with an anode and the second dopant region, wherein the first dopant region and the second dopant region are of different doping types, and the third dopant region and the second dopant region are of different doping types, wherein,

[0016] The third dopant region comprises a high-doped layer and a low-doped layer.

[0017] The low-doped layer is connected with the second dopant region, and the high-doped layer is connected with the anode.

[0018] The high-doped layer is non-uniformly doped to form a local isolation region.

[0019] Further, the thickness of the low-doped layer is greater than or equal to that of the high-doped layer.

[0020] Further, the high-doped layer comprises a high-doped region and a non-high-doped region.

[0021] The doping concentration of the high-doped region is greater than that of the low-doped layer.

[0022] The non-high-doped region serves as an isolation region.

[0023] Further, the doping type of the isolation region is the same as or different from that of the high-doped region of the high-doped layer, and when the doping type of the isolation region is the same as that of the high-doped region of the high-doped layer, the doping concentration of the isolation region is lower than that of the high-doped region of the high-doped layer.

[0024] Further, the third dopant region comprises the high-doped layer, a first low-doped layer and a second low-doped layer connected in sequence, and the second low-doped layer is connected with the second dopant region.

[0025] The doping concentration of the first low-doped layer is lower than that of the high-doped region of the high-doped layer.

[0026] The doping concentration of the second low-doped layer is lower than that of the first low-doped layer.

[0027] Further, the thickness of the first low-doped layer is greater than that of the high-doped layer.

[0028] The thickness of the second low-doped layer is greater than that of the first low-doped layer.

[0029] Further, the isolation region is arranged on the anode side and longitudinally opposite to a gate region on the gate side.

[0030] Further, the isolation region accounts for 0% to 20% of the total surface area of the chip.

[0031] Further, the device comprises a cathode comb, and the isolation region comprises a strip-shaped isolation region, wherein,

[0032] The cathode comb is arranged in a ring array with the center of the chip as the center.

[0033] The strip-shaped isolation region is arranged in a ring array with the center of the chip as the center, and is staggered with the cathode comb.

[0034] The isolation region is located below the gate.

[0035] Further, the device comprises a plurality of cathode comb arrays, and the isolation region comprises a ring-shaped isolation region, wherein,

[0036] The ring-shaped isolation region is arranged between adjacent ring-shaped cathode comb arrays.

[0037] The isolation region is located below the gate.

[0038] Further, the isolation region comprises a ring-shaped isolation region and a strip-shaped isolation region, wherein,

[0039] The strip-shaped isolation region is arranged in a ring array.

[0040] The cathode comb is arranged between the strip-shaped isolation regions.

[0041] The isolation region is located below the gate.

[0042] Further, the anode side full-silicon wafer and the metal electrode form an ohmic contact.

[0043] The application also provides a manufacturing method of the semiconductor device with controllable emission efficiency, comprising:

[0044] The semiconductor device is generated, and one or more factors of the length, width, number, interval, and distribution position of the isolation region are controlled to control the emission efficiency.

[0045] Further, the semiconductor device is generated by one or more process methods of epitaxy, local masking, and local inversion.

[0046] The semiconductor device with controllable emission efficiency and the manufacturing method thereof can flexibly adjust the anode emission efficiency of the IGCT and other devices by changing the structure of local doping, ensure low conduction voltage drop, and effectively reduce the leakage current of the device. The structure can be used in but not limited to reverse blocking IGCT, and is also applicable to other symmetric and asymmetric power devices, such as thyristor, IGBT, etc.

[0047] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 The diagram shows a non-penetrating IGCT structure and its internal electric field distribution according to the prior art;

[0050] Figure 2 The diagram shows a through-type IGCT structure and its internal electric field distribution according to the prior art;

[0051] Figure 3(a) shows a schematic diagram of the longitudinal doped structure of a symmetric IGCT device according to an embodiment of the present invention;

[0052] Figure 3(b) shows a schematic diagram of the longitudinal doped structure of an asymmetric IGCT device according to an embodiment of the present invention;

[0053] Figure 4 A schematic diagram of the vertical dopant region distribution structure of a semiconductor device with controllable emission efficiency according to an embodiment of the present invention is shown;

[0054] Figure 5 A schematic diagram of a regional doping structure of a highly doped layer according to an embodiment of the present invention is shown;

[0055] Figure 6 A schematic diagram of the third dopant region of the three-layer structure according to an embodiment of the present invention is shown;

[0056] Figure 7 A schematic diagram of the regional doping structure of the third dopant region in a three-layer structure according to an embodiment of the present invention is shown;

[0057] Figure 8 A schematic diagram of the isolation region distribution of a ring array according to an embodiment of the present invention is shown;

[0058] Figure 9 A schematic diagram of the ring-shaped distribution of the isolation region according to an embodiment of the present invention is shown;

[0059] Figure 10A distribution diagram of an isolated region according to an embodiment of the present application is shown.

[0060] Figure 11 A process flow diagram of a manufacturing method of a semiconductor device with controllable emission efficiency in a local masking mode according to an embodiment of the present application is shown.

[0061] Figure 12 A process flow diagram of a manufacturing method of a semiconductor device with controllable emission efficiency in a local reverse mode according to an embodiment of the present application is shown.

[0062] Figure 13 A process flow diagram of a manufacturing method of a semiconductor device with controllable emission efficiency in an epitaxial mode according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0063] To make the objectives, technical solutions, and superiorities of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall into the protective scope of the present application.

[0064] The embodiments of the present application provide a semiconductor device with controllable emission efficiency, in particular, a reverse blocking semiconductor device with controllable emission efficiency. The semiconductor device of the embodiments of the present application can be an IGCT device, or other symmetric and asymmetric power devices, such as thyristor, IGBT, etc. The structure of the semiconductor device will be described in detail below taking the IGCT device as an example.

[0065] Referring to FIG. 3(a) and FIG. 3(b), the semiconductor device of the embodiments of the present application has a first dopant region, a second dopant region, and a third dopant region. The first dopant region is connected with the cathode and the second dopant region, and the third dopant region is connected with the anode and the second dopant region. The doping type of the first dopant region and the second dopant region is different, and the doping type of the third dopant region and the second dopant region is different. Exemplarily, the first dopant region is P-type doping, the second dopant region is N-type doping, and the third dopant region is P-type doping.

[0066] The structure of the third dopant region will be described in detail below. The device in the embodiments of the present application can be a symmetric device (the thickness of the first dopant region and the third dopant region is the same) or an asymmetric device (the thickness of the first dopant region and the third dopant region is different). When the device is a symmetric device, the structure of the third dopant region can also be applied to the first dopant region.

[0067] The third dopant region of the embodiment of the present application can be divided into two parts A and B in the longitudinal direction, wherein A is a high-doped layer and B is a low-doped layer, as shown in the following figure. Figure 4 The high-doped layer adopts non-uniform doping, such as local doping. The non-uniform doping refers to that the longitudinal doping structure at any position of the device (such as a chip) is not completely the same, that is, the doping layer distribution may be different when the longitudinal section at different positions is profiled, so as to form a local (non-uniform) isolation region for adjusting the emission efficiency of the device (adjusting the emission efficiency by different boron isolation structures). The high-doped layer includes a high-doped region and a non-high-doped region; wherein the high-doped region of the high-doped layer A and the low-doped layer B have the same doping type and jointly form the third dopant region; the thickness of the high-doped layer is 0-60 um (greater than 0 um), and the doping concentration of the high-doped region is exemplarily 1e16-9e19 Ω·cm; the thickness of the low-doped layer is greater than that of the high-doped layer, and the thickness is 60-120 um, and the doping concentration is lower than that of the high-doped layer, and the doping concentration is exemplarily 5e14-1e18 Ω·cm. Specifically, the isolation region is a non-high-doped region, and the doping type of the isolation region (referring to the following figure) can be the same as or different from that of the high-doped region of the high-doped layer. When the doping type of the isolation region is the same as that of the high-doped region of the high-doped layer, the doping concentration of the isolation region is lower than that of the high-doped region of the high-doped layer. Figures 8-10

[0068] Figure 5 The figure is a schematic diagram of the high-doped layer of the embodiment of the present application.

[0069] In one embodiment, the doping type of the non-high-doped region A2 is different from that of the high-doped region A1, and an additional PN junction is formed between the non-high-doped region A2 and the high-doped region A1, which can reduce the overall emission efficiency of the device. The doping layer depth of A1 and A2 can be the same or different.

[0070] In one embodiment, the doping type of the non-high-doped region A2 is the same as that of the high-doped region A1, and the doping concentration is different. Exemplarily, the doping concentration of the non-high-doped region A2 is between the doping concentration of the high-doped region A1 and the doping concentration of the low-doped layer B; if the doping concentration of A2 is equal to that of B, the high-doped layer is locally doped. The position corresponding to A2 is called an isolation region, and the emission efficiency thereof is lower than that of other parts. The device of the embodiment of the present application can be used as a reverse blocking device and can be implemented as a chip.

[0071] The leakage current of the reverse blocking device mainly includes bulk leakage current and edge leakage current. Under the same voltage level, if the same edge terminal structure is adopted, the edge leakage current of the asymmetric device and the symmetric reverse blocking device is the same, but the bulk leakage current is completely different. The bulk leakage current ​The leakage current is composed of two parts, one is the current generated by the diffusion of free carriers, and the other is the current generated in the space charge region The leakage current generated by the diffusion of free carriers is closely related to the amplification factor of the PNP transistor , and the amplification factor is affected by the emission efficiency :

[0072]

[0073] Among them, is the base transmission factor, and M is the multiplication factor.

[0074] By adjusting the isolation region, that is, the structure and area ratio of the low-emission efficiency region in each structure, the overall emission efficiency of the device can be effectively adjusted, the transistor amplification factor can be reduced, and the overall leakage current can be reduced.

[0075] The third dopant region of the emission efficiency controllable semiconductor device of the embodiment of the application is sequentially connected from the longitudinal A, B, and C three parts, as shown in Figure 6 , A is a high-doped layer, B is a first low-doped layer, and C is a second low-doped layer. Among them, the second low-doped layer C is connected with the second dopant region, and the high-doped layer A is connected with the anode. The high-doped layer A, the first low-doped layer B, and the second low-doped layer C have the same doping type and jointly form the third dopant region; for example, the thickness of the high-doped layer A is 0-30um (not including 0um), the doping concentration of the high-doped region (the high-doped layer includes the high-doped region and the non-high-doped region) is 1e16-9e19Ω·cm; the thickness of the first low-doped layer B is 0-60um (not including 0um), the doping concentration is lower than that of the high-doped layer, and the doping concentration is 1e16-1e18Ω·cm; the thickness of the second low-doped layer C is 60-120um, the doping concentration is lower than that of the first low-doped layer B, and the doping concentration is 5e14-1e16Ω·cm. The high-doped layer is non-integer surface uniform doping, such as local doping. Specifically, the isolation region is a non-high-doped region, and the doping type of the isolation region (for reference Figures 8-10 ) can be the same as or different from that of the high-doped region of the high-doped layer. When the doping type of the isolation region is the same as that of the high-doped region of the high-doped layer, the doping concentration of the isolation region is lower than that of the high-doped region of the high-doped layer.

[0076] Among them, the isolation region corresponding to the high-doped layer is a non-high-doped region, and the doping type of the isolation region can be the same as or different from that of the high-doped region; if the doping types are the same, the doping concentration of the isolation region is lower than that of the high-doped region.

[0077] Figure 7A schematic diagram of a sub-region doping structure of a third dopant region of a three-layer structure. Wherein A1 is a high-doped region, and A2 is a non-high-doped region, i.e. an isolation region without high-concentration doping.

[0078] In one embodiment, the non-high-doped region A2 is different from the high-doped region A1 in doping type, and an additional PN junction is formed between the non-high-doped region A2 and the high-doped region A1, which can reduce the overall emission efficiency of the device. The doping layer depths of A1 and A2 can be the same or different.

[0079] In one embodiment, the non-high-doped region A2 is the same as the high-doped region A1 in doping type, but different in doping concentration. Exemplarily, the doping concentration of the non-high-doped region A2 is between the doping concentration of the high-doped region A1 and the doping concentration of the low-doped layer B. The position corresponding to A2 is referred to as an isolation region, and its emission efficiency is lower than that of other parts. The device of the embodiment of the present application can be used as a reverse blocking device and can be implemented as a chip.

[0080] In the embodiment of the present application, the surface area of the isolation region accounts for 0% to 20% of the total surface area of the chip. The distribution mode of the isolation region is exemplarily described below.

[0081] Figure 8 A schematic diagram of the distribution of the isolation region in a ring array according to the embodiment of the present application is shown. As shown in the figure, the cathode comb of the semiconductor device with controllable emission efficiency is arranged in a ring array, and the strip-shaped isolation region is also arranged in a ring array and is staggered with the cathode comb, and the isolation region is located below the gate. Specifically, the strip-shaped isolation region forms one or more ring arrays (one ring array in the figure, and the center of the device is taken as the center of the ring when there are multiple ring arrays) around the center of the device, and the same ring can be separated by one or more cathode combs between different isolation regions; the spacing between each ring and the isolation regions of different rings can be different. The length and width of the isolation region can be adjusted, and the emission efficiency of the structure changes with the length, width and number of the isolation region, so that, when the semiconductor device with controllable emission efficiency is manufactured, the emission efficiency is controlled by controlling one or more factors in the distribution of the isolation region, including the length, width, number, spacing and distribution position. Further, the device can also include a ring array composed of only cathode combs, i.e. the ring array does not contain isolation regions, as shown in Figure 8 The innermost ring is a ring array of cathode combs.

[0082] Figure 9A schematic diagram of a ring-shaped isolation region distribution according to an embodiment of the present invention is shown. As shown, the device includes one or more ring-shaped isolation regions, wherein a portion of the ring-shaped isolation regions are distributed between adjacent annular cathode comb arrays, and the isolation regions are located below the gate; additionally, it also includes ring-shaped isolation regions disposed on the outer ring, and the spacing between adjacent ring-shaped isolation regions may or may not include strip-shaped isolation regions; the width of the isolation regions can be adjusted, and the emission efficiency of this structure varies with the width, position, and number of isolation regions. Therefore, when fabricating a semiconductor device with controllable emission efficiency, the emission efficiency can be controlled by controlling the distribution of the isolation regions, including one or more factors such as width, number, spacing, and distribution position.

[0083] This invention uses an IGCT as an example to illustrate the distribution of the isolation region. For thyristors, there is no cathode comb, and the entire side opposite the anode side where the isolation region is located constitutes the gate region.

[0084] Figure 10 A schematic diagram of the distribution of isolation regions in a combination of ring-shaped and array-shaped configurations according to an embodiment of the present invention is shown. As shown, ring-shaped isolation regions and strip-shaped isolation regions are combined. Exemplarily, the device includes ring-shaped isolation regions and strip-shaped isolation regions arranged in a ring array. The ring array is disposed on the periphery, cathode combs are disposed between the strip-shaped isolation regions, the ring-shaped isolation regions are disposed in the inner ring of the ring array, and the cathode combs are disposed in the inner ring of the ring-shaped isolation regions. The isolation regions are disposed below the gate electrode.

[0085] The distribution of the isolation areas in this embodiment of the invention is only illustrative and can be distributed in any location.

[0086] In this embodiment of the invention, the isolation region is arranged longitudinally opposite to the gate region on the anode side (bottom layer) and the gate side (top side). Longitudinal refers to the direction extending vertically from the gate to the cathode (or vice versa). The entire silicon wafer on the anode side and the metal electrode directly form an ohmic contact.

[0087] This invention also proposes a method for fabricating a semiconductor device with controllable emission efficiency. Exemplarily, a real-time fabrication process can be employed using partial masking, partial inversion, or epitaxy methods.

[0088] like Figure 11 As shown, taking localized doping in the third dopant region as an example, a low-doped layer B is first formed by diffusion, and then locally doped high-doped layers A1 and A2 are formed using a localized masking method. Specifically, during pre-deposition or ion implantation in the A1 region, the A2 region is locally masked, and then during pre-deposition or ion implantation in the A2 region, the A1 region is locally masked. Localized doping masking can be achieved using materials such as photoresist, silicon nitride, and silicon dioxide.

[0089] As shown in Figure 12 the first low-doped layer B is formed by diffusion, if the doping type of A1 and A2 regions is opposite, A2 is first formed by full-area doping, and then the local reverse type is formed by doping of the opposite doping type, if the doping type of A1 and A2 regions is the same, the full-area pre-deposition or ion implantation is first performed according to the lower A2 doping concentration, and then the A2 region is locally shielded during the pre-deposition or ion implantation in the A1 region.

[0090] As shown in Figure 13 the first low-doped layer B is formed by diffusion, and then the isolation region is formed by the method of alternately performing epitaxy and local shielding (for generating a device with the same doping type of A1 and A2) or alternately performing epitaxy and local reverse type (for generating a device with different doping type of A1 and A2). The advantage of this method is that the width of the isolation region is not affected by the lateral diffusion coefficient, i.e., the width can be smaller.

[0091] The third doping region with a two-layer structure is exemplarily described in the process flow, and the third doping region with a three-layer structure can be realized according to the above process flow. For example, the second low-doped layer C is first formed by diffusion, then the first low-doped layer B is formed by diffusion, and then the locally doped high-doped layers A1 and A2 are formed by local shielding. Specifically, the A2 region is locally shielded during the pre-deposition or ion implantation in the A1 region, and then the A1 region is locally shielded during the pre-deposition or ion implantation in the A2 region. The local doping shielding can be realized by photoresist, silicon nitride, silicon dioxide, etc.

[0092] Although the present application is described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions described in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent features, and these modifications or replacements do not change the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device with controllable emission efficiency, comprising: The system comprises a first dopant region, a second dopant region, and a third dopant region. The first dopant region includes an emitter structure comprising a P+ base region connected to the first dopant region, an n+ emitter formed on the P+ base region, and a cathode formed on the n+ emitter. The n+ emitter, P+ base region, first dopant region, second dopant region, and third dopant region are stacked vertically in sequence. The third dopant region is connected to the anode and the second dopant region. The first and second dopant regions have different doping types, and the third dopant region has different doping types than the second dopant region. The third dopant region includes a highly doped layer, a first low doped layer, and a second low doped layer connected in sequence, with the second low doped layer connected to the second dopant region; The doping concentration of the first low-doped layer is lower than that of the highly doped region of the high-doped layer; the doping concentration of the second low-doped layer is lower than that of the first low-doped layer. The thickness of the first low-doped layer is greater than that of the high-doped layer; the thickness of the second low-doped layer is greater than that of the first low-doped layer. The highly doped layer includes highly doped regions and non-highly doped regions; the doping concentration of the highly doped regions is greater than the doping concentration of the lowly doped layers; the non-highly doped regions serve as isolation regions. The isolation region is located on the anode side, longitudinally opposite to the gate region on the gate side.

2. The semiconductor device with controllable emission efficiency according to claim 1, characterized in that, The doping type of the isolation region may be the same as or different from that of the highly doped region of the highly doped layer. When the doping type of the isolation region is the same as that of the highly doped region of the highly doped layer, the doping concentration of the isolation region is lower than that of the highly doped region of the highly doped layer.

3. The semiconductor device with controllable emission efficiency according to any one of claims 1-2, characterized in that, The surface area of ​​the isolation region accounts for 0% to 20% of the total surface area of ​​the semiconductor device chip.

4. The semiconductor device with controllable emission efficiency according to any one of claims 1-2, characterized in that, Includes cathode comb bars, wherein the isolation region includes strip-shaped isolation regions, wherein, The cathode combs are arranged in a ring array with the chip center as the center; The strip isolation regions are arranged in a ring array centered on the chip center and are interspersed with the cathode combs; The isolation zone is located below the gate.

5. The semiconductor device with controllable emission efficiency according to any one of claims 1-2, characterized in that, It includes multiple cathode comb arrays, and the isolation region includes an annular isolation region, wherein, The annular isolation region is distributed between adjacent annular cathode comb arrays; The isolation zone is located below the gate.

6. The semiconductor device with controllable emission efficiency according to any one of claims 1-2, characterized in that, The isolation area includes: a ring-shaped isolation area and a strip-shaped isolation area, wherein, The strip-shaped isolation areas are distributed in a ring array; Cathode combs are installed between the strip-shaped isolation areas; The isolation zone is located below the gate.

7. A method for fabricating a semiconductor device with controllable emission efficiency, characterized in that, include: The semiconductor device as described in any one of claims 1-6 is formed by controlling one or more factors among the length, width, number, spacing, and distribution location of the isolation regions to control the emission efficiency.

8. The method for fabricating a semiconductor device with controllable emission efficiency according to claim 7, characterized in that, The semiconductor device is generated by one or more of the following processes: epitaxy, partial masking, and partial inversion.

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