Ferroelectric doped positive feedback field effect transistor device and preparation method thereof

Abstract

A ferroelectric doped positive feedback field effect transistor device comprises a substrate, a buried oxide layer, a channel layer and an insulating layer, a ferroelectric dielectric layer is arranged on the insulating layer, a programming gate (PG) near the drain end and a programming gate near the source end with a distance interval are arranged on the ferroelectric dielectric layer, and a pulse is applied to the programming gate to complete the ferroelectric non-volatile doping, obtain an editable semiconductor channel band structure, construct a positive feedback mechanism, realize ultra-steep subthreshold characteristics, and have both data storage and computing functions; wherein the programming gate near the drain end and the drain electrode are shielded by a side wall near the drain end, and the programming gate near the source end and the source electrode are shielded by a side wall near the source end; the present invention also provides a method for preparing the device. Based on the present invention, ultra-steep subthreshold characteristics and storage and computing functions can be obtained simultaneously, thereby breaking through the energy consumption performance bottleneck caused by working voltage and data transmission.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a ferroelectric doped positive feedback field effect transistor device and a preparation method thereof. Background Art

[0002] The silicon-based integrated circuit industry has achieved rapid development for nearly half a century following "Moore's Law", leading human society into the information society. At present, the power consumption problem has become a key technical bottleneck restricting the further development of the integrated circuit industry. The fundamental reasons are: 1) The subthreshold characteristics that cannot be reduced in proportion to the feature size cause the transistor operating voltage scaling process to stagnate at 0.6~0.7 V (reference: International Roadmap for Devices and Systems, 2021 Edition—More Moore.); 2) The inevitable data transmission delay and energy loss in the von Neumann architecture (reference: 2021 Roadmap on Neuromorphic Computing and Engineering.). Summary of the invention

[0003] In order to overcome the shortcomings of the above-mentioned prior art and to address the energy efficiency bottleneck of the integrated circuit industry in the post-Moore era, the purpose of the present invention is to provide a ferroelectric-doped positive feedback field effect transistor device and a preparation method, aiming to simultaneously obtain ultra-steep subthreshold characteristics and storage and computing functions, thereby breaking through the energy consumption problem caused by operating voltage and data transmission.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is:

[0005] A ferroelectric doped positive feedback field effect transistor device comprises a substrate, a buried oxide layer, a channel layer and an insulating layer, a ferroelectric dielectric layer is arranged on the insulating layer, a programming gate near the drain end and a programming gate near the source end are arranged on the ferroelectric dielectric layer with a distance interval, and a pulse is applied to the programming gate (PG) to complete ferroelectric non-volatile doping, obtain an editable semiconductor channel band structure, construct a positive feedback mechanism, realize ultra-steep subthreshold characteristics, and have data storage and calculation functions; wherein, the programming gate near the drain end and the drain are shielded by a side wall near the drain end, and the programming gate near the source end and the source are shielded by a side wall near the source end.

[0006] In one embodiment, the present invention uses the ferroelectric dielectric layer to perform non-volatile ferroelectric doping on the semiconductor. The ferroelectric dielectric layer can be made of HfO2, HfZrO x 、HfAlO x, AlScN, PZT, SBT, BaTiO3, Cd2Nb2O7, BiFeO3 and ZnSnO3.

[0007] In one embodiment, the two ends of the channel layer are heavily doped to form a P-type region and an N-type region, which serve as a drain region and a source region respectively. The drain region is above the drain electrode, the source region is above the source electrode, and an insulating layer is arranged above the middle part of the channel layer.

[0008] In one embodiment, the positive feedback mechanism: a positive pulse voltage is applied to the programming gate near the drain end, and a non-volatile N-type inversion layer is formed in the upper surface area of ​​the channel layer where the drain region is located; a reverse pulse voltage is applied to the programming gate near the source end, and a non-volatile P-type inversion layer is formed in the upper surface area of ​​the channel layer where the source region is located, wherein the potential barrier of the N-type inversion layer needs to be high enough to hinder the movement of holes, and the potential barrier of the P-type inversion layer needs to be high enough to hinder the movement of electrons; when working, N + The terminal (i.e. source) is connected to zero potential, P + The drain terminal is connected to a high potential. + When the terminal potential barrier is reduced to a certain value, holes begin to be injected into the middle of the channel layer and + The potential well area near the end gathers and eventually flows to N + Source; gathered at N + The holes in the end potential well region will reduce the height of the electron potential barrier there. When the potential barrier is low enough, N + The electrons at the end begin to be injected into the middle of the channel layer and + The potential well area near the end gathers and eventually flows to P + drain terminal, and gather at P + The electrons in the end potential well region will reduce the height of the hole potential barrier there; thus, the injection of electrons and holes causes the potential barrier formed by the inversion layer to decrease rapidly, eventually forming a positive feedback loop, accompanied by the instantaneous opening of the transistor. When the source-drain voltage is removed, the transistor is immediately turned off.

[0009] The present invention also provides a method for preparing the ferroelectric doped positive feedback field effect transistor device, comprising the following steps:

[0010] Step 1), growing an insulating layer on the XOI (X-On-Insuator) structure, where X represents the channel layer, I represents the buried oxide layer, and the substrate is below the buried oxide layer;

[0011] Step 2), depositing a ferroelectric layer on the insulating layer;

[0012] Step 3), growing a programming gate close to the drain end and a programming gate close to the source end with a distance between them on the ferroelectric dielectric layer;

[0013] Step 4), growing Si3N4 on the global upper surface;

[0014] Step 5), etching to form a side wall near the drain end and a side wall near the source end;

[0015] Step 6), performing ion implantation in the channel layer to form a source region and a drain region;

[0016] Step 7), a source electrode is grown on the source region, and a drain electrode is grown on the drain region.

[0017] In one embodiment, in step 1), a 1-2 nm thick insulating layer is grown on the XOI structure using a dry oxygen oxidation process, wherein the insulating layer is made of SiO2, wherein the channel layer represented by X can use any one of Si, Ge, SiGe, GaAs and a two-dimensional channel material, and its thickness is 5-10 nm, and I represents a buried oxide layer, wherein the substrate thereunder can use any one of Si, Ge, SiC, GaN, sapphire and diamond materials; and in step 4), a chemical vapor deposition process is used.

[0018] In one embodiment, in step 2), a ferroelectric dielectric layer is deposited on the insulating layer using an atomic layer deposition process, that is, a corresponding precursor source is used in combination with a precursor oxygen source and a purge gas to react and deposit at a temperature of 250-400°C to form a 3-5 nm thick ferroelectric dielectric layer. The ferroelectric dielectric layer can be made of HfO2, HfZrO x 、HfAlO x , AlScN, PZT, SBT, BaTiO3, Cd2Nb2O7, BiFeO3 and ZnSnO3.

[0019] In one embodiment, in step 3), a programming gate near the drain and a programming gate near the source are grown on the ferroelectric dielectric layer by magnetron sputtering or atomic layer deposition process with a thickness of 5-50 nm, and the programming gate near the drain and the programming gate near the source are made of any one of TaN, TiN and WN; in step 6), phosphorus ions are injected into the source region to form an N-type source region, and boron ions are injected into the drain region to form a P-type drain region; in step 7), a source and a drain are grown by magnetron sputtering or atomic layer deposition process with a thickness of 10-30 nm, and the source and the drain are made of any one of Al, Ni, W and Ti.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The present invention utilizes ferroelectric non-volatile doping to obtain an editable semiconductor channel band structure, thereby constructing a positive feedback mechanism, achieving a steep subthreshold swing, and significantly reducing power consumption compared to traditional transistors.

[0022] 2. The present invention simultaneously obtains logical operation and non-volatile storage functions, and can be used to develop a high-efficiency non-volatile storage and computing integrated architecture, which is expected to break through the energy efficiency bottleneck of the integrated circuit industry in the post-Moore era. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a diagram of the traditional von Neumann architecture.

[0024] Figure 2 This is a schematic diagram of the Feng storage and computing integrated architecture.

[0025] Figure 3 It is a schematic diagram of the structure of the ferroelectric doped positive feedback field effect transistor device of the present invention.

[0026] Figure 4 This is a schematic diagram of the hysteresis loop of a ferroelectric film.

[0027] Figure 5 is with Figure 4 Schematic diagram of the corresponding ferroelectric doping effect.

[0028] Figure 6 This is a schematic diagram of the energy band of a ferroelectric doped positive feedback field effect transistor.

[0029] Figure 7 It is a schematic diagram of the ultra-steep subthreshold curve achieved by the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0031] Traditional computers use the Feng architecture, such as Figure 1 As shown, its computing and storage are separated, and there are bottlenecks of "storage wall" and "power consumption wall", which seriously limit the improvement of system energy efficiency and cannot meet the current needs of fields such as artificial intelligence.

[0032] The present invention aims at the energy efficiency bottleneck of the integrated circuit industry in the post-Moore era, and proposes a ferroelectric doped positive feedback field effect transistor device and a preparation method thereof suitable for a non-Feng storage and computing integrated architecture to meet the requirements of low power consumption and high energy efficiency. Figure 2 As shown, it uses several storage-computing integrated arrays to simultaneously perform data storage and matrix-vector multiplication calculations based on the laws of physics, which can improve the energy efficiency of processing massive data. The present invention obtains an editable semiconductor channel band structure by introducing ferroelectric non-volatile doping technology into transistors, thereby constructing a positive feedback mechanism and realizing ultra-steep subthreshold characteristics. In addition, it also has logical operation and data storage functions, and is an ideal device structure for high-efficiency storage-computing integrated technology. It can realize both calculation and non-volatile storage, so it can be used to develop high-efficiency non-volatile storage-computing integrated architecture.

[0033] To achieve the above objectives, Figure 3 The figure shows a two-dimensional structure of a ferroelectric doped positive feedback field effect transistor device of the present invention, wherein a buried oxide layer 2 is located above a substrate 1, a channel layer 3 is located above the buried oxide layer 2, both ends of the channel layer 3 are heavily doped to form a P-type region and an N-type region, which serve as a drain region 10 and a source region 11, respectively; a drain electrode 12 is located above the drain region 10, a source electrode 13 is located above the source region 11, and a stack of an insulating layer 4, a ferroelectric dielectric layer 5 and a programming gate is located above the channel layer 3.

[0034] Specifically, the substrate 1, the buried oxide layer 2, the channel layer 3 and the insulating layer 4 are the basic structures of the device, the insulating layer 4 is arranged above the middle part of the channel layer 3, the ferroelectric dielectric layer 5 is arranged on the insulating layer 4, the programming gate includes a programming gate 6 close to the drain end and a programming gate 7 close to the source end, and there is a certain distance between the two programming gates, and the programming gate 6 close to the drain end and the drain 12 are shielded by the side wall 8 close to the drain end, and the programming gate 7 close to the source end and the source 13 are shielded by the side wall 9 close to the source end.

[0035] The present invention also provides Figure 3 The method for preparing the ferroelectric doped positive feedback field effect transistor device shown mainly comprises the following steps:

[0036] Step 1: growing an insulating layer 4 on an XOI (X-On-Insuator) structure, wherein X represents a channel layer 3, I represents a buried oxide layer 2, and a substrate 1 is below the buried oxide layer.

[0037] In this step, a dry oxygen oxidation process is used to grow a 1-2 nm insulating layer 4 on the surface of the channel layer 4, and the insulating layer 4 is made of SiO2. The channel layer 3 can use any one of Si, Ge, SiGe, GaAs and two-dimensional channel materials, and its thickness is 5-10nm. The substrate 1 can use any one of Si, Ge, SiC, GaN, sapphire and diamond materials.

[0038] Step 2: depositing a ferroelectric layer 5 on the insulating layer 4.

[0039] In this step, the ferroelectric dielectric layer 5 is deposited on the insulating layer 4 by atomic layer deposition process, that is, the corresponding precursor source is matched with the precursor oxygen source and the purge gas to react and deposit at a temperature of 250-400° C. to form a 3-5 nm thick ferroelectric dielectric layer 5.

[0040] For example, the ferroelectric dielectric layer may be made of HfO2, HfZrO x 、HfAlO x , AlScN, PZT, SBT, BaTiO3, Cd2Nb2O7, BiFeO3 and ZnSnO3.

[0041] Step 3: growing a programming gate 6 close to the drain terminal and a programming gate 7 close to the source terminal with a distance therebetween on the ferroelectric dielectric layer 5.

[0042] In this step, a 5-50 nm programming gate 6 near the drain and a programming gate 7 near the source are grown on the ferroelectric dielectric layer 5 by magnetron sputtering or atomic layer deposition process. The programming gate 6 near the drain and the programming gate 7 near the source can be made of any one of TaN, TiN and WN.

[0043] Step 4, growing Si3N4 on the global upper surface.

[0044] This step can be achieved using a chemical vapor deposition process.

[0045] Step 5, forming a side wall 8 close to the drain end and a side wall 9 close to the source end.

[0046] This step can be implemented using an etching process.

[0047] Step 6: Perform ion implantation in the channel layer 3 to form a source region 11 and a drain region 10 .

[0048] In this step, phosphorus ions are implanted into the source region 11 to form an N-type source region, and boron ions are implanted into the drain region 10 to form a P-type drain region.

[0049] Step 7: growing a source electrode 13 on the source region 11 and growing a drain electrode 12 on the drain region 10 .

[0050] In this step, a source electrode 13 and a drain electrode 12 with a thickness of 10-30 nm are grown by magnetron sputtering or atomic layer deposition process. The source electrode 13 and the drain electrode 12 are made of any one of Al, Ni, W and Ti.

[0051] In addition to the above examples, the device process structure of the present invention can also be applied to three-dimensional ultra-thin channel device structures including FinFET type, Nanosheet type and Nanowire type.

[0052] Figure 4 and Figure 5 The hysteresis loop of the ferroelectric material and the effect diagram of ferroelectric electrical doping are shown. When an appropriate forward pulse voltage is applied to the programming gate (PG), the electric dipole in the ferroelectric dielectric layer is polarized downward, and the positive polarization charge is concentrated at the interface between the ferroelectric dielectric layer and the semiconductor, thereby inducing electrons in the semiconductor and realizing non-volatile N-type doping of the semiconductor; similarly, applying an appropriate reverse pulse voltage to the programming gate can realize non-volatile P-type doping of the semiconductor. After the pulse ends, the inversion layer formed by electrical doping in the semiconductor still exists, thereby obtaining an editable semiconductor channel band structure.

[0053] Based on the band structure regulated by ferroelectric doping, a positive feedback mechanism is established as follows: a positive pulse voltage is applied to the programming gate near the drain end, and a non-volatile N-type inversion layer is formed on the surface of the channel layer 3 where the drain region 10 is located; a reverse pulse voltage is applied to the programming gate near the source end, and a non-volatile P-type inversion layer is formed on the surface of the channel layer 3 where the source region 11 is located, wherein the potential barrier of the N-type inversion layer must be high enough to hinder the movement of holes, and the potential barrier of the P-type inversion layer must be high enough to hinder the movement of electrons. + The terminal (i.e. source 13) is connected to zero potential, P + The drain terminal (i.e., the drain 12) is connected to a high potential. + When the terminal potential barrier is reduced to a certain value, holes begin to be injected into the middle of the channel layer and + The potential well area near the end gathers and eventually flows to N + Source; gathered at N + The holes in the end potential well region will reduce the height of the electron potential barrier there. When the potential barrier is low enough, N + The electrons at the end begin to be injected into the middle of the channel layer and + The potential well area near the end gathers and eventually flows to P + drain terminal, and gather at P + The electrons in the end potential well region will reduce the height of the hole potential barrier there. As a result, the injection of electrons and holes causes the potential barrier formed by the inversion layer to decrease rapidly, eventually forming a positive feedback loop, accompanied by the instantaneous opening of the transistor. The energy band change effect of turning on and off the transistor is shown in the figure below. Figure 6 As shown in Figure 1, when the source-drain voltage is removed, the transistor is turned off. Figure 7 It can be clearly seen that the present invention can break through the Boltzmann thermodynamic limitation by utilizing the positive feedback mechanism, obtain an ultra-steep subthreshold swing, and significantly reduce power consumption compared to traditional transistors.

[0054] At the same time, since the potential barrier change formed by ferroelectric doping is regulated by the pulse voltage and this change is non-volatile, its state remains after the pulse ends, that is, the storage function can be realized. In view of the transistor's own computing function, the transistor can perform storage and calculation at the same time, that is, it realizes storage and computing in one.

Claims

1. A ferroelectric doped positive feedback field effect transistor device, comprising a substrate (1), a buried oxide layer (2), a channel layer (3) and an insulating layer (4), characterized in that: A ferroelectric dielectric layer (5) is arranged on the insulating layer (4); a programming gate (6) near the drain end and a programming gate (7) near the source end are arranged on the ferroelectric dielectric layer (5) with a distance therebetween; ferroelectric non-volatile doping is completed by applying pulses to the programming gates, an editable semiconductor channel band structure is obtained, a positive feedback mechanism is constructed, an ultra-steep subthreshold characteristic is achieved, and data storage and calculation functions are combined; wherein the programming gate (6) near the drain end and the drain (12) are shielded by a side wall (8) near the drain end, and the programming gate (7) near the source end and the source (13) are shielded by a side wall (9) near the source end; The positive feedback mechanism comprises: applying a positive pulse voltage to the programming gate (6) near the drain end, and forming a non-volatile N-type inversion layer on the upper surface of the channel layer (3) where the drain region (10) is located; applying a reverse pulse voltage to the programming gate (7) near the source end, and forming a non-volatile P-type inversion layer on the upper surface of the channel layer (3) where the source region (11) is located, wherein the potential barrier of the N-type inversion layer needs to be high enough to hinder the movement of holes, and the potential barrier of the P-type inversion layer needs to be high enough to hinder the movement of electrons; when working, the N + Termination zero potential, P + When the P + When the terminal potential barrier is reduced to a certain value, holes begin to be injected into the middle of the channel layer and + The potential well area near the end gathers and eventually flows to N + Source; gathered at N + The holes in the end potential well region will reduce the height of the electron potential barrier there. When the potential barrier is low enough, N + The electrons at the end begin to be injected into the middle of the channel layer and + The potential well area near the end gathers and eventually flows to P + drain terminal, and gather at P + The electrons in the end potential well region will reduce the height of the hole potential barrier there; thus, the injection of electrons and holes causes the potential barrier formed by the inversion layer to decrease rapidly, eventually forming a positive feedback loop, accompanied by the instantaneous opening of the transistor; when the source-drain voltage is removed, the transistor is immediately turned off.

2. The ferroelectric doped positive feedback field effect transistor device according to claim 1, characterized in that: The semiconductor is non-volatilely ferroelectrically doped by means of the ferroelectric dielectric layer (5).

3. The ferroelectric doped positive feedback field effect transistor device according to claim 1, characterized in that: The two ends of the channel layer (3) are heavily doped to form a P-type region and an N-type region, which serve as a drain region (10) and a source region (11), respectively; a drain electrode (12) is located above the drain region (10); a source electrode (13) is located above the source region (11); and an insulating layer (4) is arranged above the middle portion of the channel layer (3).

4. A method for preparing the ferroelectric doped positive feedback field effect transistor device according to claim 1, comprising the following steps: Step 1), growing an insulating layer (4) on the XOI structure, wherein X represents the channel layer (3), I represents the buried oxide layer (2), and below the buried oxide layer (2) is the substrate (1); Step 2), depositing a ferroelectric dielectric layer (5) on the insulating layer (4); Step 3), growing a programming gate (6) close to the drain end and a programming gate (7) close to the source end with a distance between them on the ferroelectric dielectric layer (5); Step 4), growing Si3N4 on the global upper surface; Step 5), etching to form a side wall (8) close to the drain end and a side wall (9) close to the source end; Step 6), performing ion implantation in the channel layer (3) to form a source region (11) and a drain region (10); Step 7), growing a source electrode (13) on the source region (11), and growing a drain electrode (12) on the drain region (10).

5. The method for preparing the ferroelectric doped positive feedback field effect transistor device according to claim 4, characterized in that: In the step 1), an insulating layer (4) with a thickness of 1-2 nm is grown on the XOI structure by using a dry oxygen oxidation process, wherein the insulating layer (4) is made of SiO2, wherein the channel layer (3) represented by X is made of any one of Si, Ge, SiGe, GaAs and a two-dimensional channel material, and has a thickness of 5-10 nm, and I represents a buried oxide layer (2), wherein the substrate (1) thereunder is made of any one of Si, Ge, SiC, GaN, sapphire and diamond materials; and the step 4) is made of a chemical vapor deposition process.

6. The method for preparing the ferroelectric doped positive feedback field effect transistor device according to claim 4, characterized in that: In the step 2), a ferroelectric dielectric layer (5) is deposited on the insulating layer (4) by using an atomic layer deposition process, that is, a corresponding precursor source is combined with a precursor oxygen source and a purge gas to react and deposit at a temperature of 250-400° C. to form a 3-5 nm thick ferroelectric dielectric layer (5).

7. The method for preparing the ferroelectric doped positive feedback field effect transistor device according to claim 6, characterized in that: The ferroelectric dielectric layer uses HfO2, HfZrO x 、HfAlO x , AlScN, PZT, SBT, BaTiO3, Cd2Nb2O7, BiFeO3 and ZnSnO3.

8. The method for preparing the ferroelectric doped positive feedback field effect transistor device according to claim 5, characterized in that: In the step 3, a programming gate (6) close to the drain end and a programming gate (7) close to the source end are grown on the ferroelectric dielectric layer (5) by using a magnetron sputtering or atomic layer deposition process, and the programming gate (6) close to the drain end and the programming gate (7) close to the source end are made of any one of TaN, TiN and WN; in the step 6, phosphorus ions are implanted into the source region (11) to form an N-type source region, and boron ions are implanted into the drain region (10) to form a P-type drain region; in the step 7, a source (13) and a drain (12) are grown by using a magnetron sputtering or atomic layer deposition process, and the source (13) and the drain (12) are made of any one of Al, Ni, W and Ti.

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