Common-source power device and manufacturing method thereof

Abstract

The present invention discloses a common-source power device and a manufacturing method thereof, mainly solving the problem that existing switching devices cannot achieve both bidirectional conduction and bidirectional blocking at the same time. It includes: a substrate, a transition layer, a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer. Mesa surfaces are provided on the left and right sides of the two channel layers and the two barrier layers, and left and right drain electrodes are respectively provided on these two mesa surfaces; N+ regions are provided in the middle of the second channel layer and the second barrier layer. The lower side of this N+ region is located in the second channel layer, and a groove is provided between the upper part of the N+ region and the first channel layer. An anode and a source electrode are provided in the groove; a left P-type block and a left gate electrode are provided on the second barrier layer between the left drain electrode and the source electrode; a right P-type block and a right gate electrode are provided on the second barrier layer between the right drain electrode and the source electrode. The present invention can achieve both bidirectional conduction and bidirectional blocking at the same time, reduce the turn-on voltage in the diode mode, reduce losses, improve the integration level, and can be used as a switching device.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and particularly relates to a power device, which can be used in power electronic systems. Technical Background

[0002] As an important component of power electronic systems, power devices are important tools for realizing energy conversion and control. Therefore, the performance and reliability of power devices have a decisive impact on the technical indicators and performance of the entire power electronic system. Currently, the performance of Si-based switching devices has approached its theoretical limit and cannot meet the requirements of next-generation power electronic systems for high temperature, high voltage, high frequency, high efficiency, and high power density. The third-generation wide-bandgap semiconductor materials represented by GaN have the characteristics of large bandgap width, high saturated electron drift velocity, large critical breakdown electric field, and stable chemical properties, and have shown unique advantages in preparing switching devices with lower on-resistance, faster switching speed, and higher breakdown voltage. In particular, high electron mobility devices based on GaN-based heterojunction structures, namely GaN-based high electron mobility switching devices, have broad and special application prospects in the fields of national economy and military due to their excellent power characteristics.

[0003] Traditional GaN-based enhancement-mode switching devices are based on GaN-based heterojunction structures, which include: a substrate, a transition layer, a channel layer, a barrier layer, a P-GaN gate, a drain, a source, and a gate metal; a drain is deposited on the upper left side of the barrier layer, a source is deposited on the upper right side of the barrier layer, a P-GaN gate is deposited in the middle part of the upper part of the barrier layer, and a gate metal is deposited on the upper part of the P-GaN gate, such as Figure 1As shown. However, in traditional gallium nitride-based enhancement-mode switching devices, when in the on state, the current in the device can only conduct in one direction from the drain to the source, and the power can only be transmitted from the drain to the source. That is, traditional gallium nitride-based enhancement-mode switching devices can only achieve unidirectional conduction and unidirectional blocking. In many fields such as inverters and AC-AC frequency converters, devices often need to have the ability of bidirectional conduction and bidirectional blocking. To solve the problems of bidirectional conduction and bidirectional blocking, the existing literature "99.3% Efficiency of three-phase inverter for motor drive using GaN-based Gate Injection Transistors, 2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2011, 481-484" proposed a structure of constructing a bidirectional switch by connecting two gallium nitride-based enhancement-mode switching devices in series. However, when this switch operates in the unidirectional conduction mode of the diode, for example, when device 1 is conducting and device 2 is off, device 2 forms a diode. The turn-on voltage of this diode is relatively large and equal to the threshold voltage of the device, resulting in a significant increase in the switch conduction loss when operating in this mode. Therefore, when this switch operates in the unidirectional conduction mode of the diode, a high threshold voltage Vth and a low reverse turn-on voltage V ON cannot be achieved simultaneously. This severely limits the practical application of this switch.

[0004] Therefore, it is necessary to develop high-performance gallium nitride-based enhancement-mode switching devices with simple processes, good bidirectional conduction and bidirectional blocking characteristics, and a low turn-on voltage when operating in the unidirectional conduction mode of the diode to meet the urgent needs of the power electronics system for such switching devices. Summary of the Invention

[0005] The purpose of the present invention is to provide a common-source power device and its manufacturing method for the above-mentioned deficiencies of the existing technology, so as to simultaneously achieve bidirectional conduction and bidirectional blocking characteristics, reduce the turn-on voltage when the switch operates in the unidirectional conduction mode of the diode, reduce losses, and improve the integration of the switching device.

[0006] To achieve the above purpose, the technical solution of the present invention is as follows:

[0007] 1. A common-source power device, including from bottom to top: a substrate 1, a transition layer 2, a second channel layer 5, and a second barrier layer 6, characterized in that:

[0008] A first channel layer 3 and a first barrier layer 4 are inserted between the transition layer 2 and the second channel layer 5, and the first barrier layer 4 is located above the first channel layer 3;

[0009] On both the left and right sides of the first channel layer 3, the first barrier layer 4, the second channel layer 5, and the second barrier layer 6, there are mesa 7s. The lower ends of these two mesa 7s are both located above the transition layer 2. On the left and right mesa 7s, a left drain 8 and a right drain 9 are respectively provided;

[0010] At the middle position of the second channel layer 5 and the second barrier layer 6, there is an N + region 10. The lower side of this N + region 10 is located inside the second channel layer 5;

[0011] Between the upper part of the N + region 10 and the inside of the first channel layer 3, there is a groove 11. Inside this groove, a source electrode 13 and an anode 12 are respectively provided at the upper and lower parts, and the contact surfaces of these two electrodes are located at the lower side of the N + region 10;

[0012] On the second barrier layer 6 between the left drain 8 and the source electrode 13, there are a left P-type block 14 and a left gate 16; on the second barrier layer 6 between the right drain 9 and the source electrode 13, there are a right P-type block 15 and a right gate 17.

[0013] Furthermore, the thickness S1 of the first barrier layer 4 is 2 - 60 nm, and the thickness S2 of the second barrier layer 6 is 2 - 60 nm.

[0014] Furthermore, the N + region 10 is an N-type heavily doped region, and its implantation dose is greater than 1×10 20 cm -2 .

[0015] Furthermore, the lower side of the groove 11 is located inside the first channel layer 3, and the distance between the lower side of the groove 11 and the upper surface of the first channel layer 3 is at least 5 nm.

[0016] Furthermore, the distance t between the upper side of the anode 12 and the lower side of the N + region 10 is t > 0 nm.

[0017] Furthermore, the thickness h of both the left P-type block 14 and the right P-type block 15 is 10 - 500 nm, and their doping concentrations are both 1×10 16 - 5×10 20 cm -3 .

[0018] Furthermore, the left gate 16 is located above the left P-type block 14, and the right gate 17 is located above the right P-type block 15.

[0019] Furthermore, the left drain 8 and the right drain 9 adopt the same metal combination, and both form ohmic contacts with the contacted semiconductors;

[0020] Further, the anode 12 is made of multiple layers of metal, and the bottommost layer of metal is a high work function metal, and a Schottky contact is formed between the anode 12 and the contacted semiconductor;

[0021] Further, an ohmic contact is formed between the source electrode 13 and the contacted semiconductor.

[0022] 2. A method for manufacturing the above-mentioned common-source power device, characterized by comprising the following steps:

[0023] A) Epitaxially grow a GaN-based wide bandgap semiconductor material on the substrate 1 to form a transition layer 2 with a thickness of 1 - 50 μm;

[0024] B) Fabricate the channel layer and the barrier layer:

[0025] B1) Epitaxially grow GaN material on the transition layer 2 to form a first channel layer 3 with a thickness of 10 - 200 nm;

[0026] B2) Epitaxially grow a GaN-based wide bandgap semiconductor material on the first channel layer 3 to form a first barrier layer 4 with a thickness S1 of 2 - 60 nm;

[0027] B3) Epitaxially grow GaN material on the first barrier layer 4 to form a second channel layer 5 with a thickness of 10 - 200 nm;

[0028] B4) Epitaxially grow a GaN-based wide bandgap semiconductor material on the second channel layer 5 to form a second barrier layer 6 with a thickness S2 of 2 - 60 nm;

[0029] C) Fabricate a mask for the first time on the second barrier layer 6, and use this mask to etch on both sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4, and the first channel layer 3 respectively, and etch until reaching the upper surface of the transition layer 2 to form two left and right mesa structures 7;

[0030] D) Use the mask fabricated in step C) to deposit multiple layers of metal on the two left and right mesa structures 7 respectively, and perform rapid thermal annealing to form a left drain 8 and a right drain 9, and ohmic contacts are formed between both of these drains and the contacted semiconductor;

[0031] E) Fabricate a mask for the second time on the second barrier layer 6, the left drain 8, and the right drain 9, and use this mask to perform ion implantation at the middle position between the second channel layer 5 and the second barrier layer 6 to form an N + region 10. When determining the implantation dose and energy, it is necessary to ensure that the first channel layer 3 will not be damaged;

[0032] F) Fabricate a mask for the third time on the second barrier layer 6, the left drain 8, the right drain 9, and the N + region 10, and use this mask to... +Etch the middle of region 10, the second channel layer 5, the first barrier layer 4, and the first channel layer 3 respectively to form a groove 11;

[0033] G) Using the mask fabricated in step F), deposit multiple layers of metal inside the groove 11 to form an anode 12, and a Schottky contact is formed between the anode 12 and the semiconductor material it contacts; then deposit a metal combination on the upper part of the anode 12 to form a source electrode 13, and an ohmic contact is formed between the source electrode 13 and the second channel layer 5 and the first barrier layer 4;

[0034] H) Epitaxially grow P-type semiconductor material on the second barrier layer 6, the left drain 8, the right drain 9, region 10 and the source electrode 13 to form a P-type layer; then fabricate a mask for the fourth time on the P-type layer, and use this mask to etch the P-type layer to form a left P-type block 14 and a right P-type block 15; +

[0035] I) Fabricate a mask for the fifth time on the second barrier layer 6, the left drain 8, the right drain 9, region 10, the source electrode 13, the left P-type block 14 and the right P-type block 15, and use this mask to deposit multiple layers of metal on the left P-type block 14 and the right P-type block 15 to form a left gate 16 and a right gate 17 respectively, completing the fabrication of the entire device. +

[0036]

[0037] Compared with traditional gallium nitride-based enhancement-mode switching devices, the device of the present invention has the following advantages:

[0038] First, bidirectional conduction and bidirectional blocking characteristics can be achieved.

[0039] In the device of the present invention, since the first channel layer and the first barrier layer are inserted, an electron channel is formed at the contact interface between the two. This channel and the left drain and the anode constitute a Schottky diode structure on the left side, and this channel and the right drain and the anode constitute a Schottky diode structure on the right side. Moreover, these two diodes are distributed back-to-back, enabling electrons to have a leftward current path in the left Schottky diode and a rightward current path in the right Schottky diode;

[0039] At the same time, due to the combined action of spontaneous polarization and piezoelectric polarization, a two-dimensional electron gas channel is formed at the contact interface between the second channel layer and the second barrier layer. This channel and the left drain, the source electrode, the left P-type block and the left gate constitute a left-side switching transistor, and this channel and the right drain, the source electrode, the right P-type block and the right gate constitute a right-side switching transistor. That is, the two transistors are connected by sharing the source electrode, enabling electrons to have a rightward current path in the left transistor and a leftward current path in the right transistor. Therefore, by controlling the potentials on the left gate and the right gate, the turning on and off of the left and right transistors can be changed. At the same time, by applying different voltages on the left drain and the right drain, the states of the two diodes can be controlled, and the bidirectional conduction characteristic and the bidirectional blocking characteristic of the device can be achieved simultaneously.

[0040] Second, in the device of the present invention, a vertical stacking method of a switching transistor and a Schottky diode is adopted. Compared with the traditional method of placing discrete components on the same PCB board for interconnection, it can reduce the parasitic parameters brought by interconnection and significantly improve the integration degree of the switching device.

[0041] Third, due to the active region between the drain and source of the switching transistor in the device of the present invention overlapping with the active region between the anode and drain of the Schottky diode in the vertical direction, and the drain serving as both the cathode of the diode and the drain of the switching transistor, and two back-to-back diodes sharing the anode and two transistors sharing the source, the external connections are reduced, and the area of the device in the horizontal direction is greatly reduced.

[0042] Fourth, since two embedded Schottky diodes are adopted in the device of the present invention, when the device operates in the unidirectional conduction mode of the diode, a very low turn-on voltage can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a structural diagram of a conventional gallium nitride-based enhancement-mode switching device;

[0044] Figure 2 is a structural diagram of the common-source power device of the present invention;

[0045] Figure 3 is Figure 2 a top view of

[0046] Figure 4 is a schematic diagram of the overall process for fabricating the common-source power device of the present invention;

[0047] Figure 5 is the test result of the on-state characteristics of the device of the present invention;

[0048] Figure 6 is the test result of the blocking characteristics of the device of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The embodiments of the present invention will be further described in detail below with reference to the drawings.

[0050] Referring to Figure 2 and Figure 3 the common-source power device of the present invention includes: a substrate 1, a transition layer 2, a first channel layer 3, a first barrier layer 4, a second channel layer 5, a second barrier layer 6, a mesa 7, a left drain 8, a right drain 9, an N + region 10, a groove 11, an anode 12, a source 13, a left P-type block 14, a right P-type block 15, a left gate 16 and a right gate 17. Among them:

[0051] The substrate 1 is made of silicon carbide, sapphire, silicon or other materials;

[0052] The transition layer 2 is located on the upper part of the substrate 1 and is composed of several layers of the same or different GaN-based wide-bandgap semiconductor materials, with a thickness of 1 - 50 μm;

[0053] The first channel layer 3 is located on the upper part of the transition layer 2 and is made of GaN material, with a thickness of 10 - 200 nm;

[0054] The first barrier layer 4 is located on the upper part of the first channel layer 3 and is made of GaN-based wide-bandgap semiconductor material, with a thickness S1 of 2 - 60 nm;

[0055] The second channel layer 5 is located on the upper part of the first barrier layer 4 and is made of GaN material, with a thickness of 10 - 200 nm;

[0056] The second barrier layer 6 is located on the upper part of the second channel layer 5 and is made of GaN-based wide-bandgap semiconductor material, with a thickness S2 of 2 - 60 nm;

[0057] There are two mesa 7, respectively located on the left and right sides of the first channel layer 3, the first barrier layer 4, the second channel layer 5, and the second barrier layer 6. The lower ends of these two mesa 7 are both located on the upper part of the transition layer 2;

[0058] The left drain 8 and the right drain 9 are respectively located on the upper parts of the mesa 7 on the left and right sides. They adopt the same multi-layer metal combination and form ohmic contacts with the contacted semiconductors;

[0059] The N + region 10 is located in the middle of the second channel layer 5 and the second barrier layer 6. Its lower side is located in the second channel layer 5. This N + region 10 is an N-type heavily doped region formed by ion implantation, and its implantation dose is greater than 1×10 20 cm -2 , and when selecting the implantation depth and dose, it should be ensured that it has almost no damage to the first channel layer 3;

[0060] The groove 11 is located between the upper part of the N + region 10 and the inside of the first channel layer 3. The lower side of this groove 11 is located inside the first channel layer 3, and the distance between the lower side of the groove 11 and the upper surface of the first channel layer 3 is at least 5 nm;

[0061] The anode 12 is located inside the groove 11, and the distance t between the upper part of the anode 12 and the lower part of the N + region 10 > 0 nm. The anode 12 adopts a multi-layer metal combination, and the bottom layer metal is a high work function metal. The anode 12 forms a Schottky contact with the contacted semiconductor;

[0062] The source electrode 13 is located above the anode 12, and the contact surface between the source electrode 13 and the anode 12 is located on the lower side of the N + region 10, and an ohmic contact is formed between the source electrode 13 and the contacted semiconductor;

[0063] The left P-type block 14 is located on the second barrier layer 6 between the left drain electrode 8 and the source electrode 13, and the right P-type block 15 is located on the second barrier layer 6 between the right drain electrode 9 and the source electrode 13. The thickness h of both the left P-type block 14 and the right P-type block 15 is 10 - 500 nm, and their doping concentrations are both 1×10 16 ~5×10 20 cm -3 , and when determining the thickness h of the left P-type block 14 and the right P-type block 15, it is necessary to ensure that they have almost no depletion effect on the first barrier layer 4;

[0064] The left gate electrode 16 is located above the left P-type block 14, and the right gate electrode 17 is located above the right P-type block 15.

[0065] Referring to Figure 4 , the following three embodiments are given for the common-source type power device fabricated by the present invention.

[0066] Embodiment 1: A common-source type power device is fabricated on a silicon carbide substrate, where the thicknesses of the first channel layer 3, the first barrier layer 4, the second channel layer 5, and the second barrier layer 6 are 10 nm, 2 nm, 10 nm, and 2 nm respectively, and the implantation dose of the N + region 10 is 5×10 20 cm -2 , the distance t between the lower part of the N + region 10 and the upper part of the anode 12 is 1 nm, and the thickness h of both the left P-type block 14 and the right P-type block 15 is 10 nm, with a doping concentration of 5×10 18 cm -3 .

[0067] Step 1. Epitaxially grow AlN and GaN materials on the silicon carbide substrate 1 from bottom to top to fabricate the transition layer 2, as Figure 4 a.

[0068] (1.1) Use metal organic chemical vapor deposition technology to epitaxially grow an undoped AlN material with a thickness of 100 nm on the silicon carbide substrate 1. The process conditions of metal organic chemical vapor deposition are: temperature is 1000 °C, pressure is 45 Torr, hydrogen flow rate is 4400 sccm, ammonia flow rate is 4400 sccm, and aluminum source flow rate is 5 μmol / min;

[0069] (1.2) Use metalorganic chemical vapor deposition technology to epitaxially grow GaN material with a thickness of 0.9 μm on the AlN material to complete the fabrication of the transition layer 2. The process conditions are as follows: temperature is 960 °C, pressure is 45 Torr, hydrogen flow rate is 4400 sccm, ammonia flow rate is 4400 sccm, and gallium source flow rate is 120 μmol / min.

[0070] Step 2. Fabricate the channel layer and the barrier layer on the GaN transition layer 2, as shown in Figure 4 b.

[0071] (2.1) Use metalorganic chemical vapor deposition technology to epitaxially grow GaN material on the GaN transition layer 2 to form the first channel layer 3 with a thickness of 10 nm. The process conditions for metalorganic chemical vapor deposition are as follows: temperature is 900 °C, pressure is 40 Torr, hydrogen flow rate is 4000 sccm, ammonia flow rate is 4000 sccm, and gallium source flow rate is 90 μmol / min;

[0072] (2.2) Use metalorganic chemical vapor deposition technology to epitaxially grow undoped Al 0.4 Ga 0.6 N with a thickness S1 of 2 nm and an aluminum composition of 0.4 on the first channel layer 3 to form the first barrier layer 4. The process conditions are as follows: temperature is 980 °C, pressure is 45 Torr, hydrogen flow rate is 4300 sccm, ammonia flow rate is 4300 sccm, gallium source flow rate is 35 μmol / min, and aluminum source flow rate is 7 μmol / min;

[0073] (2.3) Use metalorganic chemical vapor deposition technology to epitaxially grow GaN material on the first barrier layer 4 to form the second channel layer 5 with a thickness of 10 nm. The process conditions are as follows: temperature is 900 °C, pressure is 40 Torr, hydrogen flow rate is 4000 sccm, ammonia flow rate is 4000 sccm, and gallium source flow rate is 90 μmol / min;

[0074] (2.4) Use metalorganic chemical vapor deposition technology to epitaxially grow undoped Al 0.3 Ga 0.7 N with a thickness S2 of 2 nm and an aluminum composition of 0.3 on the second channel layer 5 to form the second barrier layer 6. The process conditions are as follows: temperature is 980 °C, pressure is 45 Torr, hydrogen flow rate is 4200 sccm, ammonia flow rate is 4200 sccm, gallium source flow rate is 39 μmol / min, and aluminum source flow rate is 5 μmol / min.

[0075] Step 3. Fabricate the mesa 7, as shown in Figure 4 c.

[0076] A mask is fabricated on the second barrier layer 6 for the first time. Using this mask, reactive ion etching technology is employed to etch both sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4, and the first channel layer 3, and the etching is stopped at the upper surface of the transition layer 2 to form two left and right mesa structures 7.

[0077] The process conditions for etching are as follows: the flow rate of Cl2 is 15 sccm, the pressure is 10 mTorr, and the power is 100 W.

[0078] Step 4. Deposit and form the left drain 8 and the right drain 9, as shown in Figure 4 d.

[0079] Using the mask fabricated in step 3, multiple layers of metals are respectively deposited on the two left and right mesa structures 7 by electron beam evaporation technology. The multiple layers of metals are Al, Ni, and Au, and their thicknesses are 0.016 μm / 0.177 μm / 0.058 μm respectively. And rapid thermal annealing is performed for 30 s in an N2 atmosphere at a temperature of 870 °C to form the left drain 8 and the right drain 9. Ohmic contacts are formed between both of these drains and the contacted semiconductors.

[0080] The process conditions for deposition are as follows: the vacuum degree is less than 1.8×10 -3 Pa, the power is 380 W, and the evaporation rate is less than

[0081] Step 5. Fabricate the N + region 10, as shown in Figure 4 e.

[0082] A mask is fabricated on the second barrier layer 6, the left drain 8, and the right drain 9 for the second time. Using this mask, ion implantation is performed at the middle position between the second channel layer 5 and the second barrier layer 6 to form the N + region 10;

[0083] The process conditions for ion implantation are as follows: the implanted N-type impurity is nitrogen ions, the implantation energy is 17 keV, and the implantation dose is 5×10 20 cm -2 .

[0084] Step 6. Etch to form the groove 11, as shown in Figure 4 f.

[0085] A mask is fabricated on the second barrier layer 6, the left drain 8, the right drain 9, and the N + region 10 for the third time. Using this mask, reactive ion etching technology is employed to etch the middle part of the N + region 10, the second channel layer 5, the first barrier layer 4, and the first channel layer 3 respectively. The etching depth is 19 nm to form the groove 11;

[0086] The process conditions for etching the groove are as follows: the flow rate of Cl2 is 15 sccm, the pressure is 10 mTorr, and the power is 100 W.

[0087] Step 7. Fabricate the anode 12 in the groove 11, as shown in Figure 4 g.

[0088] Using the mask fabricated in Step 6, deposit multiple layers of metal inside the groove 11 by electron beam evaporation technology. The deposited metal is a Ti / Au metal combination, that is, Ti in the lower layer and Au in the upper layer, with a thickness of 0.004 μm / 0.002 μm, to form the anode 12. A Schottky contact is formed between the anode 12 and the contacted semiconductor material;

[0089] The process conditions for depositing the metal are as follows: the vacuum degree is less than 1.8×10 -3 Pa, the power is 200 W, and the evaporation rate is less than

[0090] Step 8. Fabricate the source electrode 13 on the anode 12, as shown in Figure 4 h.

[0091] Using the mask fabricated in Step 6, deposit multiple layers of metal Al, Ni, and Au on the upper part of the anode 12 by electron beam evaporation technology, with thicknesses of 0.008 μm / 0.005 μm / 0.006 μm respectively, to form the source electrode 13. An ohmic contact is formed between the source electrode 13 and the second channel layer 5 and the first barrier layer 4;

[0092] The process conditions for depositing the metal are as follows: the vacuum degree is less than 1.8×10 -3 Pa, the power is 400 W, and the evaporation rate is less than

[0093] Step 9. Fabricate the left P-type block 14 and the right P-type block 15, as shown in Figure 4 i.

[0094] (9.1) Using magnetron sputtering technology, epitaxially dope NiO material with a doping concentration of 5×10 + cm 18 and a thickness of 10 nm on the second barrier layer 6, the left drain 8, the right drain 9, the N -3 region 10, and the source electrode 13 to form a P-type NiO layer;

[0095] The sputtering process conditions are as follows: the power is 110 W, the temperature is 300 °C, the Ar flow rate is 20 sccm, and the O2 flow rate is 30 sccm;

[0096] (9.2) A mask is fabricated on the P-type NiO layer for the fourth time. Using this mask, the P-type NiO layer is etched by reactive ion etching technology until reaching the upper surface of the second barrier layer 6, forming a left P-type block 14 and a right P-type block 15 respectively;

[0097] The etching process conditions are as follows: the Cl2 flow rate is 15 sccm, the pressure is 10 mTorr, and the power is 120 W.

[0098] Step 10. Fabricate a left gate 16 and a right gate 17, as Figure 4 j.

[0099] A mask is fabricated on the second barrier layer 6, left drain 8, right drain 9, N + region 10, source 13, left P-type block 14 and right P-type block 15 for the fifth time. Using this mask, a metal combination Ta / Au is deposited on the left P-type block 14 and right P-type block 15 respectively by sputtering technology, that is, Ta is the lower layer and Au is the upper layer, and their thicknesses are 0.021 μm / 0.28 μm respectively; a left gate 16 and a right gate 17 are formed respectively, completing the fabrication of the entire device.

[0100] The sputtering process conditions are as follows: the air pressure is about 0.1 Pa, the Ar flow rate is 8 sccm, the substrate temperature is fixed at 200 °C, and the target radio frequency power is 150 W.

[0101] Example 2: On a sapphire substrate, a first channel layer 3, a first barrier layer 4, a second channel layer 5, and a second barrier layer 6 with thicknesses of 200 nm, 60 nm, 200 nm, and 60 nm respectively are fabricated. The N + region 10 is implanted with a dose of 2×10 21 cm -2 , and the distance t between the lower part of the N + region 10 and the upper part of the anode 12 is 20 nm. The thicknesses h of the left P-type block 14 and the right P-type block 15 are both 500 nm, and the doping concentration is 1×10 16 cm -3 common-source power device.

[0102] Step 1. Epitaxially grow GaN material on the sapphire substrate 1 to fabricate a transition layer 2, as Figure 4 a.

[0103] Using metal organic chemical vapor deposition technology, under the process conditions of a temperature of 980 °C, a pressure of 47 Torr, a hydrogen flow rate of 4400 sccm, an ammonia flow rate of 4400 sccm, and a gallium source flow rate of 120 μmol / min, GaN material with a thickness of 50 μm is epitaxially grown on the sapphire substrate 1 to form a transition layer 2.

[0104] Step 2. Fabricate a channel layer and a barrier layer on the GaN transition layer 2, asFigure 4 b.

[0105] (2a) Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 900 °C, a pressure of 40 Torr, a hydrogen flow rate of 4000 sccm, an ammonia flow rate of 4000 sccm, and a gallium source flow rate of 90 μmol / min, GaN material is epitaxially grown on the GaN buffer layer 2 to form a first channel layer 3 with a thickness of 200 nm;

[0106] (2b) Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 980 °C, a pressure of 45 Torr, a hydrogen flow rate of 4300 sccm, an ammonia flow rate of 4300 sccm, a gallium source flow rate of 35 μmol / min, and an aluminum source flow rate of 7 μmol / min, undoped Al 0.2 Ga 0.8 N with a thickness S1 of 60 nm and an aluminum composition of 0.2 is epitaxially grown on the first channel layer 3 to form a first barrier layer 4;

[0107] (2c) Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 900 °C, a pressure of 40 Torr, a hydrogen flow rate of 4000 sccm, an ammonia flow rate of 4000 sccm, and a gallium source flow rate of 90 μmol / min, GaN material is epitaxially grown on the first barrier layer 4 to form a second channel layer 5 with a thickness of 200 nm;

[0108] (2d) Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 980 °C, a pressure of 45 Torr, a hydrogen flow rate of 4200 sccm, an ammonia flow rate of 4200 sccm, a gallium source flow rate of 39 μmol / min, and an aluminum source flow rate of 5 μmol / min, undoped Al 0.1 Ga 0.9 N with a thickness S2 of 60 nm and an aluminum composition of 0.1 is epitaxially grown on the second channel layer 5 to form a second barrier layer 6.

[0109] Step Three. Fabricate the mesa 7, as shown in Figure 4 c.

[0110] A mask is fabricated on the second barrier layer 6 for the first time. Using this mask, reactive ion etching technology is employed to etch both sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4, and the first channel layer 3 under the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W, and the etching is carried out until the upper surface of the buffer layer 2 is reached, forming two left and right mesas 7.

[0111] Step Four. Deposit and form the left drain 8 and the right drain 9, as shown in Figure 4 d.

[0112] Using the mask fabricated in Step 3, under the process conditions of a vacuum degree less than 1.8×10 -3 Pa, a power of 380 W, and an evaporation rate less than , deposit multi-layer metal combinations on the left and right platforms 7 respectively using electron beam evaporation technology. The multi-layer metal is composed of Ti, Al, Ni, and Au, with thicknesses of 0.226 μm / 0.216 μm / 0.177 μm / 0.158 μm respectively, and perform rapid thermal annealing for 30 s in an N2 atmosphere at a temperature of 870 °C to form the left drain 8 and the right drain 9. Ohmic contacts are formed between both drains and the contacted semiconductors.

[0113] Step Five. Fabricate the N + region 10, as shown in Figure 4 e.

[0114] Fabricate a mask for the second time on the second barrier layer 6, the left drain 8, and the right drain 9. Using this mask, under the process conditions of an implantation energy of 17 keV and an implantation dose of 2×10 21 cm -2 , implant N-type impurities of phosphorus ions at the middle position between the second channel layer 5 and the second barrier layer 6 to form the N + region 10.

[0115] Step Six. Etch to form the groove 11, as shown in Figure 4 f.

[0116] Fabricate a mask for the third time on the second barrier layer 6, the left drain 8, the right drain 9, and the N + region 10. Using this mask and reactive ion etching technology, under the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 100 W, etch the middle part of the N + region 10, the second channel layer 5, the first barrier layer 4, and the first channel layer 3 respectively. The etching depth is 340 nm to form the groove 11.

[0117] Step Seven. Fabricate the anode 12 in the groove 11, as shown in Figure 4 g.

[0118] Using the mask fabricated in Step Six, use electron beam evaporation technology under the process conditions of a vacuum degree less than 1.8×10 -3 Pa, a power of 200 W, and an evaporation rate less than , deposit multi-layer metal inside the groove 11. The deposited metal is a W / Au metal combination, that is, the lower layer is W and the upper layer is Au, with a thickness of 0.035 μm / 0.015 μm, to form the anode 12. A Schottky contact is formed between the anode 12 and the contacted semiconductor material.

[0119] Step VIII. Fabricate the source electrode 13 on the upper part of the anode 12, as shown in Figure 4 h.

[0120] Again, using the mask fabricated in Step VI, under the process conditions of a vacuum degree less than 1.8×10 -3 Pa, a power of 400 W, and an evaporation rate less than , deposit multiple layers of metals Ti, Al, Ni, and Au on the upper part of the anode 12 by electron beam evaporation technology, with thicknesses of 0.059 / 0.068 μm / 0.185 μm / 0.076 μm respectively, to form the source electrode 13, and an ohmic contact is formed between the source electrode 13 and the second channel layer 5 and the first barrier layer 4.

[0121] Step IX. Fabricate the left P-type block 14 and the right P-type block 15, as shown in Figure 4 i.

[0122] (9a) Using metalorganic chemical vapor deposition technology, under the process conditions of a temperature of 950 °C, a pressure of 40 Torr, a hydrogen flow rate of 4000 sccm, using high-purity Mg source as a dopant, an ammonia flow rate of 4000 sccm, and a gallium source flow rate of 100 μmol / min, epitaxially dope a p-type GaN material with a doping concentration of 1×10 + cm 16 and a thickness of 500 nm on the second barrier layer 6, the left drain 8, the right drain 9, the N -3 region 10, and the source electrode 13 to form a P-type GaN layer;

[0123] (9b) Then fabricate a mask for the fourth time on this P-type GaN layer, and use this mask to etch the P-type GaN layer by reactive ion etching technology under the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 120 W until reaching the upper surface of the second barrier layer 6, respectively forming the left P-type block 14 and the right P-type block 15.

[0124] Step X. Fabricate the left gate 16 and the right gate 17, as shown in Figure 4 j.

[0125] Fabricate a mask for the fifth time on the second barrier layer 6, the left drain 8, the right drain 9, the N + region 10, the source electrode 13, the left P-type block 14, and the right P-type block 15. Under the process conditions of a pressure of about 0.1 Pa, an Ar flow rate of 8 sccm, a substrate temperature fixed at 200 °C, and a target RF power of 150 W, use this mask to deposit a metal combination Gd / Au on the left P-type block 14 and the right P-type block 15 by sputtering technology, that is, the lower layer is Gd and the upper layer is Au, with thicknesses of 0.021 μm / 0.28 μm respectively; respectively form the left gate 16 and the right gate 17 to complete the fabrication of the entire device.

[0126] Example 3: On a silicon substrate, a first channel layer 3, a first barrier layer 4, a second channel layer 5, and a second barrier layer 6 with thicknesses of 40 nm, 35 nm, 70 nm, and 20 nm respectively are fabricated. The implantation dose of the N + region 10 is 4×10 22 cm -2 , and the distance t between the lower part of the N + region 10 and the upper part of the anode 12 is 40 nm. The thicknesses h of both the left P-type block 14 and the right P-type block 15 are 120 nm, and the doping concentration is 5×10 20 cm -3 common-source power device.

[0127] Step A. On the silicon substrate 1, an AlN and GaN material is epitaxially grown from bottom to top to fabricate the transition layer 2, as shown in Figure 5 a.

[0128] (A1) Under the process conditions of a temperature of 800 °C, a pressure of 40 Torr, a hydrogen flow rate of 4000 sccm, an ammonia flow rate of 4000 sccm, and an aluminum source flow rate of 25 μmol / min, an AlN material with a thickness of 400 nm is epitaxially grown on the silicon substrate 1 using metalorganic chemical vapor deposition technology;

[0129] (A2) Under the process conditions of a temperature of 980 °C, a pressure of 45 Torr, a hydrogen flow rate of 4000 sccm, an ammonia flow rate of 4000 sccm, and a gallium source flow rate of 120 μmol / min, a GaN material with a thickness of 5.6 μm is epitaxially grown on the AlN material using metalorganic chemical vapor deposition technology to complete the fabrication of the transition layer 2.

[0130] Step B. On the GaN transition layer 2, a channel layer and a barrier layer are fabricated, as shown in Figure 4 b.

[0131] (B1) Under the process conditions of a temperature of 900 °C, a pressure of 40 Torr, a hydrogen flow rate of 4000 sccm, an ammonia flow rate of 4000 sccm, and a gallium source flow rate of 90 μmol / min, a GaN material is epitaxially grown on the GaN transition layer 2 using metalorganic chemical vapor deposition technology to form a first channel layer 3 with a thickness of 40 nm;

[0132] (B2) Under the process conditions of a temperature of 980 °C, a pressure of 45 Torr, a hydrogen flow rate of 4300 sccm, an ammonia flow rate of 4300 sccm, a gallium source flow rate of 35 μmol / min, and an aluminum source flow rate of 7 μmol / min, an undoped Al 0.25 Ga 0.75N is used to form the first barrier layer 4;

[0133] (B3) Set the process conditions of temperature at 900 °C, pressure at 40 Torr, hydrogen flow rate at 4000 sccm, ammonia flow rate at 4000 sccm, and gallium source flow rate at 90 μmol / min. Use metalorganic chemical vapor deposition technology to epitaxially grow GaN material on the first barrier layer 4 to form the second channel layer 5 with a thickness of 70 nm;

[0134] (B4) Set the process conditions of temperature at 980 °C, pressure at 45 Torr, hydrogen flow rate at 4200 sccm, ammonia flow rate at 4200 sccm, gallium source flow rate at 39 μmol / min, and aluminum source flow rate at 5 μmol / min. Use metalorganic chemical vapor deposition technology to epitaxially grow undoped Al with an aluminum component of 0.3 and a thickness S2 of 20 nm on the second channel layer 5 0.3 Ga 0.7 N to form the second barrier layer 6.

[0135] Step C. Fabricate the mesa 7, as Figure 4 c.

[0136] Set the etching process conditions of Cl2 flow rate at 15 sccm, pressure at 10 mTorr, and power at 100 W. First, fabricate a mask on the second barrier layer 6. Using this mask, use reactive ion etching technology to etch both sides of the second barrier layer 6, the second channel layer 5, the first barrier layer 4, and the first channel layer 3, and etch until reaching the upper surface of the transition layer 2 to form two left and right mesas 7.

[0137] Step D. Deposit and form the left drain 8 and the right drain 9, as Figure 4 d.

[0138] Set the deposition process conditions with a vacuum degree less than 1.8×10 -3 Pa, power at 380 W, and evaporation rate less than . Using the mask fabricated in step C, use electron beam evaporation technology to deposit multiple layers of metal on the two left and right mesas 7 respectively. The multiple layers of metal are Ta, Ni, Au, with thicknesses of 0.016 μm / 0.177 μm / 0.058 μm respectively, and perform rapid thermal annealing for 30 s in an N2 atmosphere at a temperature of 870 °C to form the left drain 8 and the right drain 9. Ohmic contacts are formed between both of these drains and the contacted semiconductors.

[0139] Step E. Fabricate the N + region 10, as Figure 4 e.

[0140] Set the process conditions for ion implantation as follows: the implanted N-type impurity is arsenic ions, the implantation energy is 19 keV, and the implantation dose is 4×10 22 cm -2 , fabricate a mask for the second time on the second barrier layer 6, the left drain 8, and the right drain 9, and perform ion implantation at the middle position of the second barrier layer 6 using this mask to form an N + region 10.

[0141] Step F. Etch to form a groove 11, as shown in Figure 4 f.

[0142] Set the process conditions for etching as follows: the Cl2 flow rate is 15 sccm, the pressure is 10 mTorr, and the power is 100 W. Fabricate a mask for the third time on the second barrier layer 6, the left drain 8, the right drain 9, and the N + region 10, and use reactive ion etching technology with this mask to etch the middle part of the N + region 10, the second channel layer 5, the first barrier layer 4, and the first channel layer 3 respectively, with an etching depth of 150 nm to form a groove 11.

[0143] Step G. Fabricate an anode 12 in the groove 11, as shown in Figure 4 g.

[0144] Set the process conditions for metal deposition as follows: the vacuum degree is less than 1.8×10 -3 Pa, the power is 200 W, and the evaporation rate is less than Using the mask fabricated in step F, deposit multiple layers of metal inside the groove 11 by electron beam evaporation technology. The deposited metal is a Ni / Au metal combination, that is, the lower layer is Ni and the upper layer is Au, with thicknesses of 0.015 μm / 0.015 μm respectively, to form an anode 12. There is a Schottky contact between this anode 12 and the contacted semiconductor material.

[0145] Step H. Set the vacuum degree to be less than 1.8×10 -3 Pa, the power is 400 W, and the evaporation rate is less than . Using the mask fabricated in step F again, deposit multiple layers of metal Ta, Ni, and Au on the upper part of the anode 12 by electron beam evaporation technology, with thicknesses of 0.018 μm / 0.135 μm / 0.046 μm respectively, to form a source electrode 13. There is an ohmic contact between this source electrode 13 and the contacted semiconductor, as shown in Figure 4 h.

[0146] Step I. Fabricate a left P-type block 14 and a right P-type block 15, as shown in Figure 4 i.

[0147] (I1) Set the target as copper with a purity of 99.999%, high-purity argon as the sputtering gas, and high-purity oxygen of the same purity as the reaction gas. The vacuum degree of the reaction chamber before sputtering is 2.0×10 -4 Pa. During sputtering, maintain the Ar gas flow rate at 20 sccm, the O2 flow rate at 10 sccm, the pressure in the deposition chamber at 0.5 Pa, the RF power at 35 W, and the substrate temperature at 200 °C. Using magnetron sputtering technology, epitaxially dope the second barrier layer 6, left drain 8, right drain 9, N + region 10 and source electrode 13 with a doping concentration of 5×10 20 cm -3 and a thickness of 120 nm of CuO material to form a P-type CuO layer;

[0148] (I2) Set the etching process conditions as: the Cl2 flow rate is 15 sccm, the pressure is 10 mTorr, and the power is 120 W. Fabricate a mask for the fourth time on the P-type CuO layer, and use the mask to etch the P-type CuO layer using reactive ion etching technology until reaching the upper surface of the second barrier layer 6, respectively forming a left P-type block 14 and a right P-type block 15.

[0149] Step J. Fabricate a left gate 16 and a right gate 17, as shown in Figure 4 j.

[0150] Set the sputtering process conditions as: the pressure is about 0.1 Pa, the Ar flow rate is 8 sccm, the substrate temperature is fixed at 200 °C, and the target RF power is 150 W. Fabricate a mask for the fifth time on the second barrier layer 6, left drain 8, right drain 9, N + region 10, source electrode 13, left P-type block 14 and right P-type block 15. Use the mask to deposit a metal combination with Ta as the lower layer and Ni as the upper layer on the left P-type block 14 and right P-type block 15 respectively, with thicknesses of 0.021 μm / 0.28 μm; respectively form a left gate 16 and a right gate 17 to complete the fabrication of the entire device.

[0151] The effects of the present invention can be further illustrated by the following test results.

[0152] Test 1: Conduct a conduction test on the device of Embodiment 2 of the present invention, and the results are as shown in Figure 5 , where: Figure 5 (a) is the forward conduction test result, Figure 5 (b) is the reverse conduction test result. It can be seen that the device of the present invention has excellent bidirectional conduction characteristics; Figure 5

[0153] Test 2: Conduct a blocking test on the device of Embodiment 2 of the present invention, and the results are as shown in Figure 6 , and from Figure 6 it can be seen that...It can be seen that the device of the present invention can achieve bidirectional blocking, and the forward and reverse breakdown voltages in the off state are 861V and -822V respectively, indicating that the device of the present invention has excellent bidirectional conduction and bidirectional blocking characteristics.

[0154] The above description is only three specific embodiments of the present invention and does not constitute a limitation on the present invention. Obviously, for professionals in the field, after understanding the content and principle of the present invention, various corrections and changes in form and details can be made according to the method of the present invention without departing from the principle and scope of the present invention. However, these corrections and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A common-source power device, including, from bottom to top: A substrate (1), a transition layer (2), a second channel layer (5) and a second barrier layer (6), characterized in that: A first channel layer (3) and a first barrier layer (4) are inserted between the transition layer (2) and the second channel layer (5), and the first barrier layer (4) is located above the first channel layer (3); Tabletops (7) are provided on both the left and right sides of the first channel layer (3), the first barrier layer (4), the second channel layer (5) and the second barrier layer (6). The lower ends of these two tabletops (7) are both located above the transition layer (2), and a left drain (8) and a right drain (9) are respectively provided on the tabletops (7) on the left and right sides; An N+ region (10) is provided at the middle position of the second channel layer (5) and the second barrier layer (6), and the lower side of the N+ region (10) is located inside the second channel layer (5); A groove (11) is provided between the upper part of the N+ region (10) and the inside of the first channel layer (3). A source electrode (13) and an anode (12) are respectively provided in the upper and lower parts inside the groove, and the contact surfaces of these two electrodes are located on the lower side of the N+ region (10); A left P-type block (14) and a left gate (16) are provided on the second barrier layer (6) between the left drain (8) and the source electrode (13); a right P-type block (15) and a right gate (17) are provided on the second barrier layer (6) between the right drain (9) and the source electrode (13).

2. The device according to claim 1, characterized in that The thickness S1 of the first barrier layer (4) is 2 to 60 nm, and the thickness S2 of the second barrier layer (6) is 2 to 60 nm.

3. The device according to claim 1, characterized in that The N+ region (10) is an N-type heavily doped region, and its implantation dose is greater than 1×10 20 cm -2 .

4. The device according to claim 1, characterized in that, The lower side of the groove (11) is located inside the first channel layer (3), and the distance between the lower side of the groove (11) and the upper surface of the first channel layer (3) is at least 5 nm.

5. The device according to claim 1, characterized in that, The distance t between the upper side of the anode (12) and the lower side of the N+ region (10) is t > 0 nm, and this distance is not greater than the sum of the thicknesses of the first barrier layer (4) and the second channel layer (5).

6. The device according to claim 1, characterized in that, The thickness h of the left P-type block (14) and the right P-type block (15) is 10 to 500 nm, and their doping concentrations are both 1×10 16 ~5×10 20 cm -3 .

7. The device according to claim 1, characterized in that: The left gate (16) is located above the left P-type block (14); The right gate (17) is located above the right P-type block (15).

8. The device according to claim 1, characterized in that: The left drain (8) and the right drain (9) adopt the same metal combination and both form ohmic contacts with the contacted semiconductors; The anode (12) adopts a multi-layer metal, and the bottom layer metal is a high work function metal. The anode (12) forms a Schottky contact with the contacted semiconductor; The source electrode (13) forms an ohmic contact with the contacted semiconductor.

9. A method for fabricating a common-source power device, characterized in that Comprising the following steps: A) Epitaxially grow a GaN-based wide bandgap semiconductor material on the substrate (1) to form a transition layer (2) with a thickness of 1 to 50 μm; B) Fabricate the channel layer and the barrier layer: B1) Epitaxially grow GaN material on the transition layer (2) to form a first channel layer (3) with a thickness of 10 to 200 nm; B2) Epitaxially grow a GaN-based wide bandgap semiconductor material on the first channel layer (3) to form a first barrier layer (4) with a thickness S1 of 2 to 60 nm; B3) Epitaxially grow GaN material on the first barrier layer (4) to form a second channel layer (5) with a thickness of 10 - 200 nm; B4) Epitaxially grow a GaN-based wide bandgap semiconductor material on the second channel layer (5) to form a second barrier layer (6) with a thickness S2 of 2 - 60 nm; C) Fabricate a mask on the second barrier layer (6) for the first time. Using this mask, etch both sides of the second barrier layer (6), the second channel layer (5), the first barrier layer (4), and the first channel layer (3) respectively, and etch until reaching the upper surface of the transition layer (2) to form two left and right mesa structures (7); D) Using the mask fabricated in step C), deposit multiple layers of metal on the two left and right mesa structures (7) respectively, and perform rapid thermal annealing to form a left drain (8) and a right drain (9). Ohmic contacts are formed between both of these drains and the contacted semiconductors; E) Fabricate a mask on the second barrier layer (6), the left drain (8), and the right drain (9) for the second time. Using this mask, perform ion implantation at the middle position between the second channel layer (5) and the second barrier layer (6) to form an N+ region (10). When determining the implantation dose and energy, it is necessary to ensure that the first channel layer (3) will not be damaged; F) Fabricate a mask on the second barrier layer (6), the left drain (8), the right drain (9), and the N+ region (10) for the third time. Using this mask, etch the middle part of the N+ region (10), the second channel layer (5), the first barrier layer (4), and the first channel layer (3) respectively to form grooves (11); G) Using the mask fabricated in step F), deposit multiple layers of metal inside the grooves (11) to form an anode (12). Schottky contact is formed between this anode (12) and the contacted semiconductor material; then deposit a metal combination on the upper part of this anode (12) to form a source electrode (13). Ohmic contacts are formed between this source electrode (13) and the second channel layer (5) and the first barrier layer (4); H) Epitaxially grow a P-type semiconductor material on the second barrier layer (6), the left drain (8), the right drain (9), the N+ region (10), and the source electrode (13) to form a P-type layer; then fabricate a mask on the P-type layer for the fourth time. Using this mask, etch the P-type layer to form a left P-type block (14) and a right P-type block (15); I) Fabricate a mask on the second barrier layer (6), the left drain (8), the right drain (9), the N+ region (10), the source electrode (13), the left P-type block (14), and the right P-type block (15) for the fifth time. Using this mask, deposit multiple layers of metal on the left P-type block (14) and the right P-type block (15) respectively to form a left gate (16) and a right gate (17), completing the fabrication of the entire device.

10. The method according to claim 9, wherein: The epitaxial techniques used in steps A), B), and H) include: metalorganic chemical vapor deposition technique, magnetron sputtering, and molecular beam epitaxy technique; The metal deposition processes used in steps D), G), and I) include: electron beam evaporation process and sputtering process.

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