Extended shallow trench isolation for ultra-low leakage in fin-type lateral bipolar junction transistor devices

Abstract

The present disclosure relates to an extended shallow trench isolation for ultra-low leakage in fin-type lateral bipolar junction transistor devices. A lateral bipolar junction transistor (BJT) device includes an emitter region, a collector region, and a base region between and laterally separating the emitter region and the collector region, the base region including an inner base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating a lower surface of the inner base region from the semiconductor substrate.

Description

Technical Field

[0001] This disclosure generally relates to various embodiments of fin-type lateral bipolar junction transistor (BJT) devices, and various methods of manufacturing such lateral BJT devices. Background Technology

[0002] Bipolar junction transistors (BJTs) are widely used in many integrated circuit products. Typically, a BJT device includes a collector region, a base region, and an emitter region. BJT devices can be PNP or NPN. In a PNP BJT device, current flows from the emitter to the base, then through the collector and out of the device. In an NPN BJT device, current flows from the collector to the base, then through the emitter and out of the device.

[0003] Device designers have been under pressure to improve the operating speed and electrical performance of BJT devices and integrated circuits using such BJT devices. This can include, for example, reducing the leakage current, power consumption, and heat dissipation of BJT devices (e.g., due to the high base-to-body leakage current in BJTs).

[0004] A System-on-a-Chip (SoC) is an integrated circuit product that includes all the components expected in a system, such as a computer. This SoC chip may include one or more central processing units and coprocessors, graphics drivers, memory, power management circuitry, wireless communication interfaces, and other components of a fully functional system. Furthermore, because signals between the various components on a SoC are kept on-die, the power requirements of the system on the SoC can be reduced. SoC devices can be formed using BiCMOS technology, which involves simultaneously forming BJT devices and CMOS field-effect transistors (N-type and P-type) on a single chip. In BiCMOS applications, techniques for efficiently and effectively forming BJT devices and CMOS transistors are required. Summary of the Invention

[0005] The following is a simplified summary of at least one of the disclosed embodiments to provide a basic understanding of certain aspects of the subject matter disclosed herein. This summary is not an exhaustive overview of all the subject matter disclosed herein. It is not intended to identify key or essential elements of the subject matter disclosed herein or to define the scope of any claim relating to any subject matter disclosed herein. Its sole purpose is to present some concepts in a simplified form as a prelude to the specific embodiments discussed later in the application.

[0006] This disclosure generally relates to various embodiments of fin-type lateral bipolar junction transistor (BJT) devices, and various methods of forming such lateral BJT devices.

[0007] A device according to an embodiment includes: an emitter region, a collector region, and a base region, the base region being located between and laterally separating the emitter region and the collector region, the base region including an inner base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating the lower surface of the inner base region from the semiconductor substrate.

[0008] A lateral bipolar junction transistor (BJT) device according to an embodiment includes: an emitter region, a collector region, and a base region, the base region being located between and laterally separating the emitter region and the collector region, the base region including an inner base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating the lower surface of the inner base region from the semiconductor substrate, wherein the inner base region physically contacts the cavity, and wherein the bottom surface of the emitter region and the bottom surface of the collector region are located on the upper surface of the semiconductor substrate.

[0009] A method for forming a lateral bipolar junction transistor (BJT) device according to an embodiment includes: forming a cavity in a semiconductor substrate; filling the cavity with an insulating material; and forming an emitter region, a collector region, and a base region in the semiconductor substrate, the base region being located between and laterally separating the emitter region and the collector region, the forming further including forming the base region above the cavity in physical contact with the cavity, wherein the base region is physically separated from the semiconductor substrate through the cavity. Attached Figure Description

[0010] This disclosure can be understood by referring to the following description in conjunction with the accompanying drawings, in which like reference numerals denote like elements, and wherein:

[0011] Figure 1-41 Various embodiments of a fin-type lateral bipolar junction transistor (BJT) device according to embodiments of the present disclosure are shown, as well as various novel methods for forming such lateral BJT devices.

[0012] Figure 42 and 43 This is a graph illustrating the operating characteristics of a lateral BJT device according to an embodiment of the present disclosure.

[0013] Figure 44 A structure comprising a plurality of lateral BJT devices is shown according to an embodiment of the present disclosure.

[0014] While the subject matter disclosed herein is susceptible to various modifications and alternatives, specific embodiments thereof have been illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the description of specific embodiments herein is not intended to limit the invention to the specific forms disclosed, but rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. The drawings are not to scale. Detailed Implementation

[0015] Various exemplary embodiments of the present invention are described below. For clarity, not all features of actual implementations are described in this specification. It should be understood, of course, that in the development of any such actual embodiment, many implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which will differ from one implementation to another. Furthermore, it will be appreciated that such development work can be complex and time-consuming, but will still be routine work for those skilled in the art who benefit from this disclosure.

[0016] The subject matter of the invention will now be described with reference to the accompanying drawings. Various structures, systems, and devices schematically depicted in the drawings are for illustrative purposes only so as not to obscure the content of this disclosure with details known to those skilled in the art. However, the drawings are included to describe and explain exemplary examples of this disclosure. Words and phrases used herein should be understood and interpreted to have meanings consistent with the understanding of those skilled in the art. Specific definitions of terms or phrases, i.e., definitions that differ from the common and conventional meanings understood by those skilled in the art, are not intended to imply anything by the consistent use of terms or phrases herein. Where a term or phrase is intended to have a specific meaning (i.e., a meaning other than that understood by those skilled in the art), such specific definitions will be explicitly set forth in the specification in a clear manner that directly and explicitly provides for the specific definition of the term or phrase. Those skilled in the art will readily understand upon a complete reading of this application that the methods disclosed herein are applicable to a variety of products, including but not limited to logic products, memory products, etc. Various exemplary embodiments of the methods and devices disclosed herein will now be described in more detail with reference to the accompanying drawings. The various components, structures, and material layers described herein can be formed using a variety of different materials and by performing a variety of known process operations, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal growth processes, spin coating, masking, etching, etc. The thickness of these various material layers can also vary depending on the specific application.

[0017] Figure 1 This is a cross-sectional view of a fin-type lateral bipolar junction transistor (BJT) device 100 according to an embodiment of the present disclosure. Figure 2 It is along Figure 1 The image shows a cross-sectional view of the horizontal BJT device 100 taken from line AA. Figure 3 and 4 They are along Figure 1 The image shows a cross-sectional view of the BJT device 100 taken from lines BB and CC.

[0018] The lateral BJT device 100 disclosed herein can be an NPN device or a PNP device. In the embodiments described herein, the lateral BJT device 100 will be described as an NPN device. Furthermore, in the embodiments described herein, the lateral BJT device 100 can be formed in / on a fin structure. However, the subject matter disclosed herein should not be considered limited to this fin-based structure.

[0019] like Figure 1-4 As shown, the lateral BJT device 100 may include N + Doped emitter region 102, N + A doped collector region 104 and a base region 106 are formed, with the base region 106 laterally formed between the emitter region 102 and the collector region 104 and separated from them by a sidewall spacer 108 (e.g., formed of oxide). The emitter region 102, the collector region 104, and the base region 106 may be formed over a semiconductor substrate 110. The semiconductor substrate 110 may include a P-well (PW) region 112 formed over an N-doped semiconductor region 114. In some applications, the semiconductor substrate 110 may be formed of silicon or a semiconductor material other than silicon. Therefore, the terms "substrate" or "semiconductor substrate" should be understood to encompass all semiconductor materials and all forms of such materials.

[0020] The base region 106 of the lateral BJT device 100 may include a P-type base region. + P-doped outer base region 118 covered - A doped inner base region 116. A first insulating material region 120 (e.g., silicon dioxide) may be disposed in a shallow trench isolation (STI) cavity 122 formed in the PW region 112 of the semiconductor substrate 110 below the base region 106, wherein the STI cavity 122 physically and electrically isolates the base region 106 from the PW region 112 of the semiconductor substrate 110. Figure 1 As shown, according to an embodiment, the STI cavity 122 does not extend below the emitter region 102 and collector region 104 of the lateral BJT device 100. In other embodiments, the STI cavity 122 may extend partially below the emitter region 102 and collector region 104 of the lateral BJT device 100.

[0021] As described in more detail below, fin 124 can be formed in the PW region 112 of the semiconductor substrate 110. For example... Figure 2 As shown, the inner base polar region 116 can be formed in the upper part 126 of the fin 124, wherein the upper part 126 of the fin 124 is separated from the lower part 128 of the fin 124 through the STI cavity 122.

[0022] A method for forming a lateral BJT device 100 according to an embodiment will now be described.

[0023] Figure 5 and 6 This illustrates the formation of multiple fins 124 in an N-doped region 114 of a semiconductor substrate 110. For example, as shown... Figure 5 As shown, a conformal layer of first oxide 132, nitride 134 (e.g., silicon nitride) and second oxide 136 can be formed on the upper surface 114S of the N-doped region 114 of the semiconductor substrate 110. The first and second oxide layers 132 and 136 can be formed using any suitable oxide material (e.g., silicon dioxide).

[0024] Figure 6 The illustration shows the result of performing one or more etching processes (e.g., anisotropic etching processes) using a patterned fin-formed etching mask (not shown). Figure 5 The structure is configured to form a plurality of trenches 138 in the N-doped region 114 of the semiconductor substrate 110, thereby defining the fin 124. The width and height of the fin 124 can vary depending on the specific application. Furthermore, the overall dimensions, shape, and configuration of the trenches 138 and the fin 124 can vary depending on the specific application. In the example shown herein, the fin 124 is depicted as having a tapered cross-section configuration, wherein the width of the upper surface of the fin 124 is smaller than the width of the bottom of the fin 124. Furthermore, the axial length of the fin 124 can also vary depending on the specific application. Of course, the physical dimensions of the fin 124 can vary depending on the specific application and technological advancements.

[0025] Next, refer to Figure 7 It can perform deposition processes (such as atomic layer deposition (ALD)) to... Figure 6 A conformal oxide liner 140 is deposited on the exposed surface of the structure shown. The oxide liner 140 can be formed of silicon dioxide or other suitable materials. Then, as... Figure 8 As shown, one or more masking / photolithography and oxide etching processes can be performed to selectively remove the second oxide layer 136 and the oxide liner 140 formed thereon, and to selectively remove the oxide liner 140 from the lower portion 142 of each trench 138.

[0026] Now for reference Figure 9 Then you can do Figure 8The structure undergoes one or more etching processes (e.g., using an etchant such as TMAH (tetramethylammonium hydroxide)) to selectively remove the lower portion 144 of each fin 124. Figure 8 This allows for the formation of multiple STI cavities 146 within the N-doped region 114 of the semiconductor substrate 110. (Comparison) Figure 9 and Figure 2 It can be seen that STI cavity 146 corresponds to STI cavity 122, while the remaining upper portion 148 of fin 124 corresponds to the inner base region 116 of the lateral BJT device 100. This etching process removes the lower portion 144 of each fin. Figure 8 The N-doped region 114 of the semiconductor substrate 110 at () has no effect on the nitride layer 134 or the oxide liner 140. After etching, as Figure 10 As shown, trench 138 and STI cavity 146 can be filled with insulating material 120, such as silicon dioxide. This can be achieved, for example, using flowable chemical vapor deposition (FCVD) and / or other processing techniques.

[0027] It should be noted that by comparing the graphs... Figure 2 and Figure 9 It can be seen that, Figure 9 STI 146 and Figure 2 Cavity 122 (and cavity 160) Figure 18 ) and cavity 184 ( Figure 28 )) can be located at different parts of each fin 124. For example, Figure 2 The cavity 122 can be located near the midpoint of the fin 124, while Figure 9 The STI cavity 146 can be located near the bottom of the fin 124. Typically, the location of the cavities disclosed herein (e.g., STI cavities 122, 146, 160, 184) can vary depending on application, performance, and / or processing requirements, according to embodiments. Furthermore, the size and configuration of the cavities disclosed herein can vary depending on application, performance, and / or processing requirements.

[0028] Figure 11 This is shown after several additional processing steps have been performed. Figure 10 The structure. Such processing steps may include, for example, chemically mechanically polishing (CMP) the insulating material 120 downwards to the top surface 134S of the nitride layer 134, and removing the insulating material 120 in a fin exposure process up to the top surface 148S of the upper portion 148 of the fin 124 (e.g., via chemical oxide etching (COE), plasma etching (e.g., RLSA), or other suitable processes). One or more etching processes may then be performed to remove the nitride layer 134 and the first oxide layer 132, and to remove the oxide liner 140 and a portion of the insulating material 120 from the upper portion 137 of the trench 138.

[0029] Figure 12 This shows the DD cut-off along the line after several additional processes were performed. Figure 11 A cross-sectional view of the structure is shown. For example, the isolation structure 150 can be formed in the fin 124 by performing known fabrication techniques. The isolation structure 150 may include any insulating material, such as silicon dioxide. Several ion implantation processes can be performed to form PW regions 112 and PW regions 112 in the N-doped region 114 of the semiconductor substrate 110. - Doped region 152. According to an embodiment, P - Doped region 152 forms P - Doped inner base region 116 ( Figure 1 ).

[0030] A method for forming a lateral BJT device 100 according to another embodiment will now be described.

[0031] Figure 13-15 This illustrates the formation of multiple fins 124 in an N-doped region 114 of a semiconductor substrate 110. For example, as shown... Figure 13 As shown, an oxide layer 132 (e.g., silicon dioxide) and a nitride layer 134 (e.g., silicon nitride) can be formed on the upper surface 114S of the N-doped region 114 of the semiconductor substrate 110.

[0032] Figure 14 This shows the results after performing multiple processes. Figure 13 The structure. For example, one or more etching processes (e.g., anisotropic etching processes) can be performed by patterning a fin-forming etching mask (not shown) to form a plurality of trenches 138 in the N-doped region 114 of the semiconductor substrate 110, thereby defining the fins 124. After etching, also as Figure 14 As shown, trench 138 can be filled with insulating material 120, such as silicon dioxide. This can be achieved, for example, using flowable chemical vapor deposition (FCVD) and / or other processing techniques. CMP can then be performed down the insulating material 120 until the top surface 134S of the nitride layer 134. Then... Figure 14 The structure undergoes STI deglazing or other suitable processes to remove the insulating material 120 downwards down to the top surface 124S of the fin 124 and remove it from the upper portion 139 of the trench 138. The resulting structure... Figure 15 As shown in the image.

[0033] Figure 16 This is shown after several deposition processes were performed. Figure 15 The structure. The first deposition process may include in Figure 15Structurally, a conformal insulating material layer 154 (e.g., silicon dioxide) is formed within the upper portion 139 of the trench 138. A second deposition process may include forming a conformal nitride layer 156 (e.g., silicon nitride) on the conformal insulating material layer 154. Then, as... Figure 17 As shown, it is possible to... Figure 16 The structure shown performs one or more masking / photolithography, nitride etching, and oxide etching processes (e.g., reactive ion etching (RIE)) to selectively remove a portion of the conformal nitride layer 156 and the conformal insulating material layer 154 from the upper portion 139 of the trench 138.

[0034] Now for reference Figure 18 Then you can do Figure 17 The structure undergoes one or more etching processes (e.g., using an etchant such as TMAH). The etching process can be configured to selectively remove a portion 158 of each fin 124. Figure 17 This allows for the formation of multiple cavities 160 within the N-doped region 114 of the semiconductor substrate 110. After forming the cavities 160, the... Figure 18 The structure undergoes an etching process to selectively remove any remaining portions of the conformal nitride layer 156. The resulting structure is... Figure 19 As shown in the image.

[0035] After nitride etching, such as Figure 20 As shown, Figure 19 The trenches 138 and cavities 160 in the structure can be filled with an insulating material 120, such as silicon dioxide. This can be achieved, for example, using flowable chemical vapor deposition (FCVD) and / or other processing techniques.

[0036] Figure 21 This shows the result after one or more additional processing steps have been performed. Figure 20 The structure. Such processing steps may include, for example, a CMP process to remove the insulating material 120 down to the top surface 134S of the nitride layer 134. Afterwards, as... Figure 22 As shown, a portion of the insulating material 120 can be removed down to the top surface 162S of the upper portion 162 of the fin 124 during the fin exposure process (e.g., via chemical oxide etching (COE), plasma etching (e.g., RLSA), or other suitable processes). Etching can then be performed to remove the nitride layer 134 and oxide layer 132, as well as a portion of the insulating material 120, from the upper portion 139 of the trench 138.

[0037] Figure 23 This shows the EE cut-off along the line after performing several additional processes. Figure 22A cross-sectional view of the structure is shown. For example, the isolation structure 164 can be formed in the fin 124 by performing known fabrication techniques. The isolation structure 164 may include any suitable insulating material, such as silicon dioxide. Several ion implantation processes can be performed to form PW regions 112 and PW regions 112 in the N-doped region 114 of the semiconductor substrate 110. - Doped region 166. As will be described in more detail below, P - Doped inner base region 116 can be formed on P - In doped region 166. Typically, the N-type dopant in N-doped region 114 and PW regions 112 and P - The dopant concentration of the P-type dopant in doped region 166 can depend on the specific application. Furthermore, any suitable N-type and P-type dopant species can be used for N-doped region 114, PW region 112, and P-doped region 166. - Doping is performed in doped region 166.

[0038] A method for forming a lateral BJT device 100 according to another embodiment will now be described.

[0039] Figure 24-26 A plurality of fins 170 are shown formed in a semiconductor substrate 172, wherein the semiconductor substrate 172 includes an N-doped region 174 of a first semiconductor material (e.g., silicon) and a layer 176 of a second semiconductor material (e.g., silicon-germanium (SiGe)) buried in the N-doped region 174. Figure 24 As shown, an oxide layer 132 (e.g., silicon dioxide) and a nitride layer 134 (e.g., silicon nitride) can be formed on the upper surface 174S of the N-doped region 174 of the semiconductor substrate 172.

[0040] Figure 25 The illustration shows the result of performing one or more etching processes (e.g., anisotropic etching processes) using a patterned fin-formed etch mask (not shown). Figure 24 The structure is configured to form multiple trenches 178 in the N-doped region 174 of the semiconductor substrate 172 and the buried semiconductor layer 176, thereby defining the fin 170. For example... Figure 26 As shown, a conformal insulating material layer 180 (e.g., silicon dioxide) can be formed on... Figure 25 Structurally and within groove 178. Then, as... Figure 27 As shown, it is possible to... Figure 26 The structure shown performs one or more masking / photolithography and oxide etching processes to selectively remove the conformal insulating material layer 180 formed on the buried semiconductor layer 176 in the trench 178.

[0041] Now for reference Figure 28 Then you can do Figure 27The structure undergoes one or more etching processes. The etching processes are configured to selectively remove the bottom portion 182 of each fin 170. Figure 27 A buried semiconductor layer 176 is used to form a cavity 184. Then, as... Figure 29 As shown, Figure 18 The trenches 178 and cavities 184 in the structure can be filled with an insulating material 120, such as silicon dioxide. This can be achieved, for example, using flowable chemical vapor deposition (FCVD) and / or other processing techniques.

[0042] Figure 30 This is shown after several additional processing steps have been performed. Figure 29 The structure. Such processing steps may include, for example, a CMP process for removing a portion of the insulating material 120 down to the top surface 134S of the nitride layer 134. Afterwards, as... Figure 31 As shown, a portion of the insulating material 120 can be removed downwards to the top surface 170S of the fin 170 during the fin exposure process, and a portion of the insulating material 120 can be removed from the top 179 of the trench 178 (e.g., via chemical oxide etching (COE), plasma etching (e.g., RLSA), or other suitable processes). Figure 31 As further shown, one or more etching processes can then be performed to remove the nitride layer 134, oxide layer 132, and conformal insulating material layer 180 from the top 179 of the trench 178.

[0043] Figure 32 This shows the FF section taken along the line after several additional processes were performed. Figure 31 The diagram shows a cross-sectional view of the structure. For example, the isolation structure 186 can be formed in the fin 170 using known fabrication techniques. The isolation structure 186 can comprise any insulating material, such as silicon dioxide. Several ion implantation processes can then be performed to use P... + The buried semiconductor layer 176 is doped with a dopant, and a P-type doped region 114 is formed in the semiconductor substrate 110. - Doped region 188. As will be described in more detail below, P - Doped inner base region 116 ( Figure 1 ) can form in P - In doped region 188.

[0044] Now for reference Figure 33-41 The description will be used to form based on Figure 12 The lateral BJT device 100 of the embodiment shown has the following structure. Figure 1 An overview of various exemplary methods. This can be based on... Figure 24 and 32 The structure shown undergoes a similar process to form the lateral BJT device 100.

[0045] Figure 33 This shows the result after performing several process operations. Figure 12 The corresponding structure 200. In an exemplary process flow, the base region 106 of the lateral BJT device 100 can be formed by utilizing the base region formed on P - The sacrificial gate structure 202 above the doped region 152. Figure 33 The diagram also shows a gate cap 204 and sidewall spacers 206. Various process flows can be performed to form these structures. In one exemplary process flow, the materials of the sacrificial gate structure 202 and the gate cap 204 can be blanket-deposited onto the structure 200. Then, one or more masking and etching processes can be performed on these deposited materials to form the sacrificial gate structure 202 with the gate cap 204. Next, the sidewall spacers 206, as depicted simply, can be formed adjacent to the generally vertically oriented sidewalls of the sacrificial gate structure 202. In one example, the sidewall spacers 206 can be formed by performing a conformal deposition process to form a conformal layer of sidewall spacer material on the sacrificial gate structure 202. At this time, an anisotropic etching process can be performed to remove the horizontally oriented portion of the spacer material layer, thereby forming the sidewall spacers 206 located on or adjacent to the generally vertically oriented sidewalls of the sacrificial gate structure 202. In terms of materials, the sacrificial gate structure 202 may include a sacrificial gate insulating layer (not shown separately) formed on the fin 124, such as silicon dioxide, and a sacrificial gate electrode (not shown separately) formed on the sacrificial gate insulating layer, which may be made of, for example, polycrystalline silicon or amorphous silicon. The gate cap 204 may be made of a material such as silicon nitride, and the sidewall spacers 206 may be made of a low-k insulating material (e.g., a k value less than about 3.4).

[0046] Still referencing Figure 33 After forming the sidewall spacers 206, a lightly doped drain (LDD) ion implantation process can be performed to implant P - N is formed in doped region 152 + LDD injection region 208. N + The dopant concentration of the N-type dopant material in LDD injection region 208 can be varied depending on the specific application. + LDD injection region 208 can be doped with any kind of N-type dopant material.

[0047] The following will describe this in more detail; please refer to the reference below. Figure 34 It can perform various process operations to form 100 lateral BJT devices. Figure 1 The emitter polar region 102 ( Figure 1 ) and collector region 104 ( Figure 1On the opposite side of the gate structure 202, an epitaxial cavity 210 is formed in the fin 124. Each of the epitaxial cavities 210 can have the same basic configuration. Therefore, it is possible to... Figure 33 One or more etching processes (e.g., anisotropic etching processes) are performed on the structure 200 to achieve, for example, Figure 34 Multiple epitaxial cavities 210 are formed in the fin 124 shown. The epitaxial cavities 210 can extend through P. - The doped region 152 may also have a bottom surface 210X that extends into or partially extends into the N-doped region 114. The depth of the epitaxial cavity 210 may vary depending on the specific application. In the currently disclosed example, the epitaxial cavity 210 is substantially self-aligned and substantially vertically oriented relative to the sidewall spacers 206 and the isolation structure 150.

[0048] like Figure 36 As shown, it is possible to... Figure 34 (or Figure 35 Structure 200 performs an epitaxial growth process to form N in epitaxial cavity 210. + Doped epitaxial semiconductor material region 212E (hereinafter referred to as emitter region 212E) and N + The emitter region 212E and collector region 212C are doped with epitaxial semiconductor material (hereinafter referred to as collector region 212C). In an exemplary process flow, the emitter region 212E and collector region 212C can be doped in situ, i.e., dopant material can be added during the epitaxial growth process. In other applications, the emitter region 212E and collector region 212C can initially be formed as substantially undoped epitaxial semiconductor material, and then an ion implantation process can be performed to introduce dopant material into the previously undoped emitter region 212E and collector region 212C. The emitter region 212E and collector region 212C can be doped with any kind of N-type dopant material and can include any desired semiconductor material, such as N-doped silicon carbide. In some cases, the epitaxial semiconductor material of the emitter region 212E and collector region 212C can be grown such that the emitter region 212E and collector region 212C each have a dopant region located at fin 124 ( Figure 11 and 12 The upper surface 212ES, 212CS above the upper surface 148S of the upper part 148) Figure 36 (shown as dashed lines in the middle) (i.e., the raised source / drain region).

[0049] Figure 37 This is shown after several process operations have been performed. Figure 36Structure 200. First, an insulating material layer 214 (e.g., silicon dioxide, low-k material, etc.) may be formed adjacent to the sidewall spacers 206 and planarized to the top surface 204S of the gate cap 204. A conformal etch stop layer (not shown) may be formed prior to the formation of the insulating material layer 214. Then, as... Figure 38 As shown, it is possible to... Figure 37 Structure 200 performs one or more processing steps (e.g., etching) to remove the sacrificial gate structure 202, thereby forming a base region cavity 216 that exposes the base region 106.

[0050] Further reference Figure 38 Epitaxial growth can be performed after the base cavity 216 is formed to grow in the base cavity 216 and in P - P is formed on doped region 152 + Doped epitaxial semiconductor material region 153. This additional epitaxial semiconductor material 153 forms the P-type of the lateral BJT device 100. + Doped outer base region 118 ( Figure 1 In one exemplary process flow, the epitaxial semiconductor material 153 can be doped in situ, meaning that dopant material can be added during the epitaxial growth process. In other applications, the epitaxial semiconductor material 153 can initially be formed as a substantially undoped epitaxial semiconductor material, and then an implantation process can be performed to introduce dopant material into the previously undoped epitaxial semiconductor material 153. Regardless of how the P-type dopant is introduced into the epitaxial semiconductor material 153, P... + The dopant concentration of the P-type dopant material in the doped epitaxial semiconductor material 153 can be varied according to specific applications. + The doped epitaxial semiconductor material 153 can be doped with any type of P-type dopant. The epitaxial semiconductor material 153 can be made of any desired semiconductor material, such as P-doped silicon-germanium for NPN devices. The volume of the formed epitaxial semiconductor material 153 can also vary depending on the specific application.

[0051] Figure 39 This is shown after several additional process operations were performed. Figure 38 Structure 200. For example, P can be in the base region cavity 216. + Another insulating material layer 218, such as silicon dioxide, a low-k material, etc., is formed over the doped epitaxial semiconductor material 153, and then it is planarized. As previously mentioned, a conformal etch stop layer (not shown) may be formed in the base cavity 216 before the insulating material layer 218 is formed.

[0052] Figure 40 This shows the result after performing one or more etching processes on insulating material layers 214 and 218. Figure 39Structure 200. For example, an etching process can be performed to form a P-type structure that exposes the emitter region 212E, the collector region 212C, and the base region 106, respectively. + Contact openings 220E, 220C, and 220B (using the numeral 220 for uniform reference) are formed in the doped epitaxial semiconductor material 153. A portion of the insulating material 214 may be retained after etching, thereby forming sidewall spacers 222.

[0053] like Figure 41 As shown, conductive contact structures 224E, 224C, and 224B (using the numeral 224 for consistent reference) can be formed in the contact opening 220 in a conventional manner to connect with the emitter region 212E, the collector region 212C, and the base region 106, respectively. + Conductive contacts 153 are doped with epitaxial semiconductor material. For example, conductive contact structures 224E, 224C, and 224B can be formed simultaneously with the formation of a power supply / drain metallization structure (not shown) for contacting the source / drain regions of a transistor device (not shown) formed elsewhere on structure 200. The forming material of these conductive contacts can be the same as that of the power supply / drain metallization structure, such as a trench silicide material.

[0054] As mentioned above Figure 33-41 The various exemplary processes described herein can be used according to... Figure 12 The embodiment of the structure shown forms a lateral BJT device 100. Figure 1 ). can be based on Figure 23 and 32 The embodiment of the structure shown performs a similar process to form the lateral BJT device 100.

[0055] Those skilled in the art will understand, upon fully reading this application, that the novel configuration of the lateral BJT device 100 disclosed herein offers significant benefits compared to prior art lateral BJT devices. For example, compared to prior art lateral BJT devices, the lateral BJT device 100, having an STI cavity 122 that separates the inner base region 116 from the underlying substrate, significantly reduces the base-to-body leakage current in the lateral BJT device 100.

[0056] Figure 42 This is a graph comparing the base-to-substrate leakage current of a lateral BJT device 100 with an STI cavity below the inner base region according to an embodiment, with the leakage current of a lateral BJT device formed on a bulk semiconductor without an STI cavity below the inner base region. Figure 42 As shown on the Y2 axis (right-hand side) of the graph, the leakage current in the lateral BJT device 100 with an STI cavity below the inner base region according to the embodiment can be about ten times (10x) smaller than the leakage current of the lateral BJT device formed on the bulk semiconductor.

[0057] Figure 43 This is a graph comparing the peak operating temperature of a lateral BJT device 100 with an STI cavity below the inner base region according to an embodiment with the peak operating temperature of a lateral BJT device constructed on a silicon-on-insulator (SOI) substrate (i.e., an oxide layer below the emitter, collector, and base). From Figure 43 As can be seen from the figure shown, the lateral BJT device 100 with an STI cavity below the inner base region according to the embodiment operates at a peak temperature lower than the peak temperature of lateral BJT devices built on a silicon-on-insulator (SOI) substrate (i.e., oxide below the emitter, collector and base).

[0058] In addition to providing significantly lower leakage current and improved heat dissipation, the lateral BJT device 100 with an STI cavity below the inner base region according to an embodiment can operate at speeds similar to lateral BJT devices built on an SOI substrate. Furthermore, the lateral BJT device 100 with an STI cavity below the inner base region according to an embodiment provides electrical isolation between the lateral BJT device 100 and other devices sharing the same well, which significantly reduces parasitics. For example, Figure 44 A structure comprising a plurality of lateral BJT devices 300 in a shared well (e.g., a P-well (PW) in this example) according to an embodiment of the present disclosure is shown. Adjacent lateral BJT devices 300 may share an emitter region E or a collector region C with adjacent lateral BJT devices 300. Each lateral BJT device 300 also includes a base region B and an STI cavity formed in the shared well beneath the base region B. Advantageously, the STI cavity in each lateral BJT device 300 electrically isolates the base regions B of the lateral BJT devices 300 from each other, thereby preventing current from flowing between the base regions B via the shared well.

[0059] The specific embodiments disclosed above are merely exemplary, as the invention can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art who benefit from this teaching. For example, the process steps described above may be performed in a different order. Furthermore, no limitation is intended to be made on the details of the configurations or designs shown herein, except as described in the claims below. Therefore, it is apparent that the specific embodiments disclosed above can be altered or modified, and all such changes are considered to be within the scope and spirit of the invention. It should be noted that the use of terms such as “first,” “second,” “third,” or “fourth” to describe various processes or structures in this specification and the appended claims is merely for abbreviated reference to these steps / structures and does not necessarily imply that such steps / structures are performed / formed in such an order. Of course, depending on the precise language of the claims, an ordered sequence of these processes may or may not be required. Therefore, the protection sought herein is set forth in the following claims.

Claims

1. A semiconductor device, comprising: The system comprises an emitter region, a collector region, and a base region, wherein the base region is located between the emitter region and the collector region and laterally separates the emitter region and the collector region, and the base region includes an inner base region. as well as A cavity, formed in a semiconductor substrate and filled with an insulating material, physically separates the lower surface of the inner base region from the semiconductor substrate. The emitter region, the collector region, the base region, and the cavity are formed within the fin structure. The cavity physically separates the first part of the fin structure from the second part of the fin structure.

2. The semiconductor device according to claim 1, further comprising an outer base region formed above the inner base region.

3. The semiconductor device of claim 1, wherein the bottom surface of the emitter region and the bottom surface of the collector region are located on the upper surface of the semiconductor substrate.

4. The semiconductor device of claim 1, wherein the cavity is located only below the inner base region.

5. The semiconductor device of claim 1, wherein the inner base region physically contacts the cavity.

6. The semiconductor device of claim 1, wherein the emitter region and the collector region are physically separated from the cavity via the semiconductor substrate.

7. A lateral bipolar junction transistor (BJT) device, comprising: The system comprises an emitter region, a collector region, and a base region, wherein the base region is located between the emitter region and the collector region and laterally separates the emitter region and the collector region, and the base region includes an inner base region. as well as A cavity, formed in a semiconductor substrate and filled with an insulating material, physically separates the lower surface of the inner base region from the semiconductor substrate. The inner base region physically contacts the cavity, and the bottom surface of the emitter region and the bottom surface of the collector region are located on the upper surface of the semiconductor substrate. The emitter region, the collector region, the base region, and the cavity are located within the fin structure. The cavity physically separates the upper part of the fin structure from the lower part of the fin structure.

8. The lateral bipolar junction transistor (BJT) device according to claim 7 further includes an outer base region formed above the inner base region.

9. The lateral bipolar junction transistor (BJT) device according to claim 7, wherein the cavity is located only below the inner base region.

10. The lateral bipolar junction transistor (BJT) device according to claim 7, wherein the emitter region and the collector region are physically separated from the cavity via the semiconductor substrate.

11. The lateral bipolar junction transistor (BJT) device according to claim 7, wherein the semiconductor substrate comprises a first semiconductor material, and the lateral bipolar junction transistor (BJT) device further comprises: A second semiconductor material layer embedded in the semiconductor substrate; as well as An opening formed in the second semiconductor material layer. The opening in the second semiconductor material layer includes the cavity, and the opening is filled with the insulating material.

12. The lateral bipolar junction transistor (BJT) device of claim 11, wherein the first portion of the second semiconductor material layer is separated from the second portion of the second semiconductor material layer through the opening.

13. A method for forming a lateral bipolar junction transistor (BJT) device, comprising: A cavity is formed in a semiconductor substrate; The cavity is filled with insulating material; as well as An emitter region, a collector region, and a base region are formed in the semiconductor substrate. The base region is located between the emitter region and the collector region and laterally separates the emitter region and the collector region. The formation also includes forming the base region above the cavity, in physical contact with the cavity, wherein the base region is physically separated from the semiconductor substrate through the cavity. The semiconductor substrate includes a fin structure. The cavity physically separates the upper part of the fin structure from the lower part of the fin structure.

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