Semiconductor structure and method for preparing semiconductor structure

Abstract

The present invention provides a semiconductor structure and a method for preparing the semiconductor structure, wherein the semiconductor structure comprises a substrate, a chip and a first adhesive layer; an insulating layer is disposed on the surface of the substrate; the chip is disposed on the surface of the insulating layer through the first adhesive layer; wherein the insulating layer is provided with a hole groove, the position of the hole groove corresponds to at least a portion of the edge of the first adhesive layer, a second adhesive layer is disposed in the hole groove, at least a portion of the surface of the second adhesive layer is connected to the first adhesive layer; wherein the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the first adhesive layer. The present invention can optimize the stress distribution at the connection edge between the chip and the substrate, so that when the semiconductor structure is bent or deformed, it is not easy to cause fracture at the connection edge between the chip and the substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Art

[0002] In the existing chip (memory thin die stack) packaging process, the chip, glue layer, and solder mask (SR, also known as "green film") on the substrate are in direct contact. As the thickness of the substrate (including the solder mask) and the chip is designed to be thinner and thinner in the art, when the chip itself is bent, or deformed by external force, or during the test process such as high temperature reliability (TC reliability) test, the edge of the connection between the chip and the substrate is prone to die crack or substrate crack due to stress concentration. Summary of the invention

[0003] A main purpose of the present invention is to overcome at least one of the defects of the above-mentioned prior art and provide a semiconductor structure that is not prone to chip breakage and substrate breakage.

[0004] Another main purpose of the present invention is to overcome at least one of the defects of the prior art mentioned above and provide a method for preparing a semiconductor structure capable of optimizing the stress distribution at the edge where the chip is connected to the substrate.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] According to one aspect of the present invention, there is provided a semiconductor structure, comprising a substrate, a chip and a first adhesive layer; an insulating layer is provided on the surface of the substrate; the chip is provided on the surface of the insulating layer through the first adhesive layer; wherein the insulating layer is provided with a hole groove, the position of the hole groove corresponds to at least a portion of the edge of the first adhesive layer, a second adhesive layer is provided in the hole groove, at least a portion of the surface of the second adhesive layer is connected to the first adhesive layer; wherein the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the first adhesive layer.

[0007] According to one embodiment of the present invention, the hole penetrates the insulating layer.

[0008] According to one embodiment of the present invention, the hole groove is in a ring-shaped closed structure, so that the hole groove corresponds to the entire edge of the first adhesive layer.

[0009] According to one embodiment of the present invention, the first adhesive layer is rectangular, and the edge of the first adhesive layer has four sides; wherein the holes and grooves are arranged in a rectangular ring.

[0010] According to one embodiment of the present invention, on the surface of the substrate, the outer edge of the orthographic projection pattern of the hole groove is located outside the edge of the orthographic projection pattern of the first adhesive layer.

[0011] According to one embodiment of the present invention, on the surface of the substrate, the orthographic projection pattern of the hole groove is completely covered by the orthographic projection pattern of the first adhesive layer, so that the entire surface of the second adhesive layer is connected to the first adhesive layer.

[0012] According to one embodiment of the present invention, on the surface of the substrate, the outer edge of the orthographic projection pattern of the hole groove coincides with the edge of the orthographic projection pattern of the first adhesive layer.

[0013] According to one embodiment of the present invention, the slot width of the hole is 5% to 10% of the width of the first adhesive layer.

[0014] According to one embodiment of the present invention, the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the insulating layer; and / or the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the chip.

[0015] According to one embodiment of the present invention, the thermal expansion coefficient of the second adhesive layer is smaller than the thermal expansion coefficient of the first adhesive layer.

[0016] According to one embodiment of the present invention, the thermal expansion coefficient of the second adhesive layer is smaller than the thermal expansion coefficient of the insulating layer; and / or the thermal expansion coefficient of the second adhesive layer is smaller than the thermal expansion coefficient of the chip.

[0017] According to one embodiment of the present invention, the bonding strength between the first adhesive layer and the second adhesive layer is smaller than the bonding strength between the first adhesive layer and the chip; and / or the bonding strength between the first adhesive layer and the second adhesive layer is smaller than the bonding strength between the first adhesive layer and the insulating layer.

[0018] According to one embodiment of the present invention, the material of the second adhesive layer includes silicone glue and epoxy resin glue.

[0019] According to another aspect of the present invention, a method for preparing a semiconductor structure is provided, wherein the method comprises the following steps:

[0020] Providing a substrate, wherein an insulating layer is disposed on the surface of the substrate;

[0021] forming a hole groove penetrating through the insulating layer on the insulating layer;

[0022] forming a second adhesive layer in the hole groove;

[0023] A chip is arranged on the surface of the insulating layer through a first adhesive layer, the position of the hole groove corresponds to at least a portion of the edge of the first adhesive layer, at least a portion of the surface of the second adhesive layer is connected to the first adhesive layer, and the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the first adhesive layer;

[0024] A packaging layer is formed on the surface of the insulating layer, and the chip and the first adhesive layer are packaged in the packaging layer.

[0025] According to one embodiment of the present invention, the forming of the hole groove comprises the following steps:

[0026] Disposing a photoresist on the surface of the insulating layer;

[0027] patterning the photoresist;

[0028] The patterned photoresist is exposed to remove the portion of the insulating layer not blocked by the photoresist, thereby forming the hole groove.

[0029] According to one embodiment of the present invention, the forming of the second adhesive layer comprises the following steps:

[0030] dripping a buffering rubber material into the hole groove;

[0031] The buffer adhesive material is heated and baked to solidify into the second adhesive layer.

[0032] It can be seen from the above technical solutions that the advantages and positive effects of the semiconductor structure and the method for preparing the semiconductor structure proposed in the present invention are:

[0033] The semiconductor structure and the method for preparing the semiconductor structure proposed in the present invention can optimize the stress distribution at the connection edge between the chip and the substrate by arranging a hole groove corresponding to the position of at least a portion of the edge of the first adhesive layer in the insulating layer, and arranging a second adhesive layer with an elastic modulus smaller than that of the first adhesive layer in the hole groove, so that it is not easy to break at the connection edge between the chip and the substrate when the semiconductor structure is bent or deformed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Various objects, features and advantages of the present invention will become more apparent by considering the following detailed description of preferred embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present invention and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0035] Figures 1 to 4 is a schematic structural diagram of a semiconductor structure in multiple steps of a method for preparing a semiconductor structure according to an exemplary embodiment;

[0036] Figure 5 yes Figure 4 A top view of a semiconductor structure in the steps shown;

[0037] Figures 6 to 11 is a schematic structural diagram of a semiconductor structure in multiple steps of a method for preparing a semiconductor structure according to an exemplary embodiment;

[0038] Fig.12 is a top view of a semiconductor structure in a step of a method for preparing a semiconductor structure according to another exemplary embodiment;

[0039] Fig.13 is a schematic structural diagram of a semiconductor structure according to another exemplary embodiment;

[0040] Fig.14 is a schematic structural diagram of a semiconductor structure according to another exemplary embodiment.

[0041] The following are the descriptions of the reference numerals:

[0042] 110.Substrate;

[0043] 120. Insulation layer;

[0044] 121. Hole slot;

[0045] 122. Second adhesive layer;

[0046] 130. Chip;

[0047] 131. Bare chips;

[0048] 132. Adhesive film;

[0049] 140. First adhesive layer;

[0050] 150. Lead wire;

[0051] 160. Encapsulation layer;

[0052] 170. Photoresist;

[0053] 200. Pressing device;

[0054] 300. Gluing device;

[0055] 400. Heating device;

[0056] 500. Heating device;

[0057] d1.width;

[0058] d2.Width. DETAILED DESCRIPTION

[0059] Typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments without departing from the scope of the present invention, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present invention.

[0060] In the following description of different exemplary embodiments of the present invention, reference is made to the accompanying drawings, which form a part of the present invention and in which different exemplary structures, systems and steps that can implement multiple aspects of the present invention are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present invention. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present invention, these terms are used herein only for convenience, such as according to the direction of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present invention.

[0061] Semiconductor structure implementation method 1

[0062] See also Fig.11 , which representatively shows a schematic diagram of the structure of the semiconductor structure proposed by the present invention. In this exemplary embodiment, the semiconductor structure proposed by the present invention is described by taking the packaging structure applied to a memory chip stack as an example. It is easy for those skilled in the art to understand that in order to apply the relevant design of the present invention to other types of semiconductor structures, various modifications, additions, substitutions, deletions or other changes are made to the specific embodiments described below, and these changes are still within the scope of the principle of the semiconductor structure proposed by the present invention.

[0063] like Fig.11 As shown, in this embodiment, the semiconductor structure proposed by the present invention mainly includes a substrate 110, a chip 130 and a first adhesive layer 140. Specifically, an insulating layer 120 is provided on the surface of the substrate 110. The chip 130 is provided on the surface of the insulating layer 120 through the first adhesive layer 140. Among them, the insulating layer 120 is provided with a hole groove 121, and the position of the hole groove 121 corresponds to the edge of the first adhesive layer 140. In addition, a second adhesive layer 122 is provided in the hole groove 121, and a part of the surface of the second adhesive layer 122 is connected to the first adhesive layer 140. On this basis, the elastic modulus of the second adhesive layer 122 is less than the elastic modulus of the first adhesive layer 140. Through the above design, the semiconductor structure proposed by the present invention can optimize the stress distribution of the connection edge between the chip 130 and the substrate 110 (including the insulating layer 120 provided on the surface of the substrate 110), so that when the semiconductor structure is bent or deformed, it is not easy to break at the connection edge between the chip 130 and the substrate 110.

[0064] Optionally, see Fig.11 In this embodiment, the hole 121 may penetrate the insulating layer 120 . In other embodiments, the hole 121 may not penetrate the insulating layer 120 , for example, it may only open on the upper surface of the insulating layer 120 .

[0065] Optionally, see Figure 5 , Figure 5 1 is a representative top view of the semiconductor structure in the step of forming the hole groove 121. In this embodiment, the hole groove 121 can be a substantially annular closed structure, so that the hole groove 121 corresponds to the entire edge of the first adhesive layer 140. Through the above design, the present invention can optimize the stress distribution at all positions of the connection edge of the chip 130 and the substrate 110, so that all the connection edges of the chip 130 and the substrate 110 are not prone to fracture.

[0066] Further, see Figure 5 Based on the design of the hole groove 121 being a ring-shaped closed structure, in this embodiment, the first adhesive layer 140 can be roughly rectangular, and the edge of the first adhesive layer 140 has four sides. On this basis, the hole groove 121 can be roughly arranged in the form of a rectangular ring. In other embodiments, based on the design that the hole groove 121 corresponds to the entire edge of the first adhesive layer 140, when the first adhesive layer 140 is in other shapes such as a circle, a triangle, a trapezoid, etc., the hole groove 121 can also be arranged in the form of a corresponding circular ring, a triangular ring, a trapezoidal ring, etc., and is not limited to this embodiment.

[0067] Alternatively, if Fig.11 As shown, in this embodiment, on the surface of the substrate 110, the outer edge of the orthographic projection pattern of the hole groove 121 can be located outside the edge of the orthographic projection pattern of the first adhesive layer 140. Accordingly, the second adhesive layer 122 provided in the hole groove 121 can extend to the outside of the edge of the first adhesive layer 140, so that the present invention can optimize the stress distribution of a part of the substrate 110 located outside the edge of the first adhesive layer 140, and further avoid the fracture of the relevant area.

[0068] Optionally, see Fig. 9 , Fig. 910 is a representative top view of a semiconductor structure in the step of setting a chip 130. In this embodiment, the slot width d1 of the slot 121 can be 5% to 10% of the width d2 of the first adhesive layer 140, such as 5%, 6.5%, 8%, and 10%. Accordingly, the present invention selects the above-mentioned width ratio of the slot 121 to the first adhesive layer 140 to be within a more reasonable range to avoid the overall viscosity of the chip 130 being insufficient due to the slot width d1 of the slot 121 being too large, and to avoid the semiconductor structure being deformed due to the slot width d1 being too small, which makes it impossible to achieve a better optimized stress distribution and avoid fracture. In other embodiments, the slot width d1 of the slot 121 may account for less than 5% of the width d2 of the first adhesive layer 140, or may account for more than 10%, such as 4.5%, 11%, etc., and is not limited to this embodiment.

[0069] Optionally, in this embodiment, the elastic modulus of the second adhesive layer 122 may be smaller than the elastic modulus of the insulating layer 120. Accordingly, the corresponding position of the insulating layer 120 (e.g., the position adjacent to the hole groove 121, i.e., the position corresponding to the edge of the first adhesive layer 140) is less likely to be broken. In other embodiments, on the basis of ensuring that the elastic modulus of the second adhesive layer 122 is smaller than the elastic modulus of the first adhesive layer 140, the elastic modulus of the second adhesive layer 122 may also be equal to or greater than the elastic modulus of the insulating layer 120, and is not limited to this embodiment.

[0070] Optionally, in this embodiment, the elastic modulus of the second adhesive layer 122 may be smaller than the elastic modulus of the chip 130. Accordingly, the corresponding position (e.g., edge position) of the chip 130 is less likely to be broken. In other embodiments, on the basis of ensuring that the elastic modulus of the second adhesive layer 122 is smaller than the elastic modulus of the first adhesive layer 140, the elastic modulus of the second adhesive layer 122 may also be equal to or greater than the elastic modulus of the chip 130, and is not limited to this embodiment.

[0071] Optionally, in this embodiment, the thermal expansion coefficient of the second adhesive layer 122 may be smaller than that of the first adhesive layer 140. Accordingly, when the semiconductor structure is deformed by heat, the second adhesive layer 122 can avoid the first adhesive layer 140 from being broken due to the same or even greater expansion deformation as the first adhesive layer 140, because the thermal expansion coefficient is lower than that of the first adhesive layer 140. In other embodiments, under the premise of ensuring that the present invention optimizes the stress distribution at the relevant position by setting the second adhesive layer 122, the thermal expansion coefficient of the second adhesive layer 122 may also be greater than or equal to the thermal expansion coefficient of the first adhesive layer 140, and is not limited to this embodiment.

[0072] Furthermore, based on the design that the thermal expansion coefficient of the second adhesive layer 122 is smaller than the thermal expansion coefficient of the first adhesive layer 140, in this embodiment, the thermal expansion coefficient of the second adhesive layer 122 may also be smaller than the thermal expansion coefficient of the insulating layer 120. Accordingly, when the semiconductor structure is deformed by heat, the second adhesive layer 122 can avoid the insulation layer 120 from being broken due to the same or even greater expansion deformation as the insulation layer 120, because the thermal expansion coefficient of the second adhesive layer 122 is lower than that of the insulating layer 120. In other embodiments, on the basis that the thermal expansion coefficient of the second adhesive layer 122 is smaller than that of the first adhesive layer 140, the thermal expansion coefficient of the second adhesive layer 122 may also be greater than or equal to the thermal expansion coefficient of the insulating layer 120, and the present embodiment is not limited thereto.

[0073] Furthermore, based on the design that the thermal expansion coefficient of the second adhesive layer 122 is smaller than the thermal expansion coefficient of the first adhesive layer 140, in this embodiment, the thermal expansion coefficient of the second adhesive layer 122 may also be smaller than the thermal expansion coefficient of the chip 130. Accordingly, when the semiconductor structure is deformed by heat, the second adhesive layer 122 can avoid the chip 130 from being broken due to the same or even greater expansion deformation as the chip 130, because the thermal expansion coefficient of the second adhesive layer 122 is lower than that of the chip 130. In other embodiments, on the basis that the thermal expansion coefficient of the second adhesive layer 122 is smaller than that of the first adhesive layer 140, the thermal expansion coefficient of the second adhesive layer 122 may also be greater than or equal to the thermal expansion coefficient of the chip 130, and is not limited to this embodiment.

[0074] Optionally, in this embodiment, the bonding strength between the first adhesive layer 140 and the second adhesive layer 122 may be less than the bonding strength between the first adhesive layer 140 and the chip 130. Accordingly, when the semiconductor structure is deformed, the above-mentioned design of the bonding strength can make the second adhesive layer 122 and the first adhesive layer 140 separate earlier than the first adhesive layer 140 and the chip 130, so as to ensure that when the deformation is large and the film structure is separated, the separation of the second adhesive layer 122 and the first adhesive layer 140 can be used to avoid or slow down the separation of the first adhesive layer 140 and the chip 130. In other embodiments, under the premise of ensuring that the present invention optimizes the stress distribution of the relevant position through the provision of the second adhesive layer 122, the bonding strength between the first adhesive layer 140 and the second adhesive layer 122 may also be greater than or equal to the bonding strength between the first adhesive layer 140 and the chip 130, and is not limited to this embodiment.

[0075] Optionally, in this embodiment, the bonding strength between the first adhesive layer 140 and the second adhesive layer 122 may be less than the bonding strength between the first adhesive layer 140 and the insulating layer 120. Accordingly, when the semiconductor structure is deformed, the above-mentioned bonding strength design can be used to separate the second adhesive layer 122 from the first adhesive layer 140 earlier than the first adhesive layer 140 from the insulating layer 120, so that when the deformation is large and the film structure is separated, the separation of the second adhesive layer 122 from the first adhesive layer 140 can be used to avoid or slow down the separation of the first adhesive layer 140 from the insulating layer 120. In other embodiments, under the premise of ensuring that the present invention optimizes the stress distribution of the relevant position by setting the second adhesive layer 122, the bonding strength between the first adhesive layer 140 and the second adhesive layer 122 may also be greater than or equal to the bonding strength between the first adhesive layer 140 and the insulating layer 120, and is not limited to this embodiment.

[0076] Optionally, in this embodiment, the material of the second adhesive layer 122 may include silicone, epoxy resin adhesive (such as silicone epoxy), etc.

[0077] Semiconductor structure implementation method 2

[0078] Based on the above detailed description of the first embodiment of the semiconductor structure proposed by the present invention, Fig.12 , a second embodiment of the semiconductor structure proposed by the present invention is described.

[0079] See also Fig.12 , which representatively shows a top view of the semiconductor structure in the second embodiment in the step of forming the hole groove 121. In the second embodiment, the semiconductor structure proposed by the present invention adopts substantially the same design as the first embodiment, and the design of the second embodiment different from the first embodiment will be described below.

[0080] like Fig.12 As shown, in this embodiment, the position of the hole groove 121 corresponds to a portion of the edge of the first adhesive layer 140. Accordingly, the present invention can optimize the stress distribution of a portion of the edge of the connection between the chip 130 and the substrate 110, so that the portion of the edge of the connection between the chip 130 and the substrate 110 is not prone to fracture. In other words, in various possible embodiments that conform to the design concept of the semiconductor structure proposed by the present invention, the position of the hole groove 121 can correspond to at least a portion of the edge of the first adhesive layer 140, so that the present invention can optimize the stress distribution of at least a portion of the edge of the connection between the chip 130 and the substrate 110.

[0081] Alternatively, if Fig.12As shown, based on the design that the position of the hole groove 121 corresponds to a portion of the edge of the first adhesive layer 140, in this embodiment, when the first adhesive layer 140 is substantially rectangular, the hole groove 121 corresponds to one, two or three sides of the rectangle. Of course, the hole groove 121 can also correspond to a portion of any side, or the hole groove 121 can also correspond to the four corners of the rectangle, which is not limited to this embodiment.

[0082] Semiconductor structure implementation method three

[0083] Based on the above detailed description of the first embodiment of the semiconductor structure proposed by the present invention, Fig.13 , a third embodiment of the semiconductor structure proposed by the present invention is described.

[0084] See also Fig.13 , which is a representative structural diagram of a semiconductor structure in a third embodiment. In the third embodiment, the semiconductor structure proposed by the present invention adopts substantially the same design as the first embodiment, and the design of the third embodiment that is different from the first embodiment will be described below.

[0085] like Fig.13 As shown, in this embodiment, on the surface of the substrate 110, the orthographic projection pattern of the hole groove 121 is completely covered by the orthographic projection pattern of the first glue layer 140, so that the entire surface of the second glue layer 122 is connected to the first glue layer 140. In other words, in various possible embodiments that conform to the design concept of the semiconductor structure proposed by the present invention, at least a portion of the surface of the second glue layer 122 is connected to the first glue layer 140.

[0086] Furthermore, if Fig.13 As shown, based on the design that the orthographic projection pattern of the hole groove 121 is completely covered by the orthographic projection pattern of the first adhesive layer 140, on the surface of the substrate 110, the outer edge of the orthographic projection pattern of the hole groove 121 can coincide with the edge of the orthographic projection pattern of the first adhesive layer 140.

[0087] Semiconductor structure implementation method 4

[0088] Based on the above detailed description of the first embodiment of the semiconductor structure proposed by the present invention, Fig.14 , a fourth embodiment of the semiconductor structure proposed by the present invention is described.

[0089] See also Fig.14 , which is a representative structural diagram of a semiconductor structure in a fourth embodiment. In the fourth embodiment, the semiconductor structure proposed by the present invention adopts substantially the same design as the first embodiment, and the design of the fourth embodiment that is different from the first embodiment will be described below.

[0090] like Fig.14 As shown, in this embodiment, the chip 130 can adopt a multi-layer stack structure, that is, the chip package is alternately stacked with multiple layers of bare chips 131 (die) and adhesive films 132 (die attach film, DAF for short). On this basis, the chip 130 is still arranged on the first adhesive layer 140 as an integral structure, and specifically, the bare chip 131 located at the bottom layer is arranged on the first adhesive layer 140.

[0091] It should be noted that the semiconductor structures shown in the drawings and described in this specification are only a few examples of the many types of semiconductor structures that can employ the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or any components of the semiconductor structures shown in the drawings or described in this specification.

[0092] For example, the semiconductor structure provided by the present invention may include a packaging layer 160 . The packaging layer 160 is disposed on the surface of the substrate and packages the chip 130 and the first adhesive layer 140 inside.

[0093] For another example, the bare die 131 of the chip 130 is bonded to the substrate 110 via a bonding wire 150 .

[0094] Implementation method of semiconductor structure preparation method

[0095] Based on the above detailed description of several exemplary embodiments of the semiconductor structure proposed by the present invention, Figures 1 to 11 , an exemplary implementation of the method for preparing the semiconductor structure proposed by the present invention is described.

[0096] See also Figures 1 to 11 , Figures 1 to 4 and Figures 6 to 11 The schematic diagrams of the structure of the semiconductor structure in the multiple steps of the method for preparing the semiconductor structure proposed in the present invention are respectively and representatively shown. In this exemplary embodiment, the method for preparing the semiconductor structure proposed in the present invention is described by taking the method for preparing the packaging structure applied to the memory chip stack as an example. It is easy for those skilled in the art to understand that in order to apply the relevant design of the present invention to other types of semiconductor structures, various modifications, additions, substitutions, deletions or other changes are made to the specific embodiments described below, and these changes are still within the scope of the principle of the method for preparing the semiconductor structure proposed in the present invention.

[0097] like Figures 1 to 11 As shown, in this embodiment, the method for preparing the semiconductor structure provided by the present invention mainly comprises the following steps:

[0098] A substrate 110 is provided, and an insulating layer 120 is disposed on the surface of the substrate 110;

[0099] A hole groove 121 penetrating the insulating layer 120 is formed on the insulating layer 120;

[0100] Forming a second adhesive layer 122 in the hole groove 121;

[0101] The chip 130 is arranged on the surface of the insulating layer 120 through the first adhesive layer 140, the position of the hole 121 corresponds to at least a portion of the edge of the first adhesive layer 140, at least a portion of the surface of the second adhesive layer 122 is connected to the first adhesive layer 140, and the elastic modulus of the second adhesive layer 122 is smaller than the elastic modulus of the first adhesive layer 140;

[0102] A packaging layer 160 is formed on the surface of the insulating layer 120 , and the chip 130 and the first adhesive layer 140 are packaged in the packaging layer 160 .

[0103] Through the above design, the preparation method of the semiconductor structure proposed in the present invention can optimize the stress distribution at the connection edge between the chip 130 and the substrate 110 (including the insulating layer 120 arranged on the surface of the substrate 110), so that when the semiconductor structure is bent or deformed, it is not easy to break at the connection edge between the chip 130 and the substrate 110.

[0104] like Figure 1 As shown, it is a representative structural schematic diagram of a semiconductor structure in the step of "providing a substrate 110". In the above steps, the semiconductor structure includes a substrate 110 and an insulating layer 120. Among them, the insulating layer 120 is arranged on the surface of the substrate 110. It is easy to understand that in some descriptions of this specification, the insulating layer 120 is regarded as a part of the substrate 110 for overall description, and in the actual process, a finished substrate with an insulating layer 120 can be directly prepared, which does not violate the relevant design concept of the present invention, and is hereby explained.

[0105] Alternatively, if Figures 2 to 4 As shown, in this embodiment, the formation of the hole groove 121 may specifically include the following steps:

[0106] Disposing a photoresist 170 on the surface of the insulating layer 120;

[0107] patterned photoresist 170;

[0108] The patterned photoresist 170 is exposed to light to remove the portion of the insulating layer 120 that is not blocked by the photoresist 170 , thereby forming a hole 121 .

[0109] like Figure 2As shown, it is a schematic diagram of the structure of the semiconductor structure in the step of "arranging the photoresist 170". In the above steps, the semiconductor structure includes a substrate 110, an insulating layer 120 and a photoresist 170. The photoresist 170 is coated on the surface of the insulating layer 120.

[0110] like Figure 3 , which is a representative structural schematic diagram of a semiconductor structure in the step of “patterning photoresist 170”. In the above steps, the semiconductor structure includes a substrate 110, an insulating layer 120, and a patterned photoresist 170. The portion of the photoresist 170 that is removed after the patterning process corresponds to the position where the hole groove 121 needs to be set on the insulating layer 120.

[0111] like Figure 4 As shown, it is a schematic diagram of the structure of the semiconductor structure in the step of "exposing and removing part of the insulating layer 120 by using the photoresist 170". In the above steps, the semiconductor structure includes a substrate 110 and the insulating layer 120 remaining after the partial removal. Among them, the part of the insulating layer 120 not blocked by the photoresist 170 is removed, thereby forming a hole 121 penetrating the insulating layer 120, and thus the process of transferring the photoresist 170 pattern to the insulating layer 120 is completed.

[0112] like Figure 5 , which is a representative top view of the semiconductor structure in the step of "exposing and removing part of the insulating layer 120 by using the photoresist 170". In this embodiment, the hole groove 121 is roughly annular and closed, that is, the hole groove 121 corresponds to the entire edge of the chip 130 (the first glue layer 140). Therefore, in order to form the hole groove 121 Figure 5 The arrangement shown is roughly rectangular, and the opening of the photoresist 170 after patterning can also be roughly rectangular. In other embodiments, when it is necessary to form the hole grooves 121 in other arrangements, for example Fig.12 The arrangement of the holes 121 shown, and the patterned openings of the photoresist 170 may also be adjusted accordingly, and are not limited to this embodiment.

[0113] Alternatively, if Figure 6 and Figure 7 As shown, in this embodiment, the formation of the second adhesive layer 122 may specifically include the following steps:

[0114] Applying a buffering adhesive material in the hole groove 121;

[0115] The buffer adhesive material is heated and baked to solidify into the second adhesive layer 122 .

[0116] like Figure 6As shown, it representatively shows a schematic diagram of the structure of the semiconductor structure in the step of "drip-coating the buffer glue material in the hole groove 121". In the above steps, the semiconductor structure includes a substrate 110, an insulating layer 120, and a buffer glue material being dripped into the hole groove 121 of the insulating layer 120. Among them, the buffer glue material can be filled into the hole groove 121 by dripping through the glue coating device 300, which can ensure the full filling of the hole groove 121, and at the same time can optimize the material uniformity and density of the second glue layer 122 formed in the subsequent process, and further optimize the optimization effect on the stress distribution. In other embodiments, the buffer glue material can also be filled in the hole groove 121 by other coating methods, which is not limited to this embodiment.

[0117] like Figure 7 , which is a schematic diagram of the structure of the semiconductor structure in the step of "heating and baking to solidify the buffer adhesive into the second adhesive layer 122". In the above steps, the semiconductor structure includes a substrate 110, an insulating layer 120 and a solidified second adhesive layer 122. The second adhesive layer 122 is formed by curing the buffer adhesive filled in the hole groove 121 by heating the heating device 400. The heating device 400 can be, for example, an oven.

[0118] Alternatively, if Figure 8 and Fig. 9 As shown, in this embodiment, the configuration of the chip 130 may specifically include the following steps:

[0119] Laminating the first adhesive layer 140 and the chip 130 on the substrate 110;

[0120] The first adhesive layer 140 is bonded between the chip 130 and the substrate 110 by heating and baking.

[0121] like Figure 8 As shown, it is a schematic diagram of the structure of the semiconductor structure in the step of "pressing the first glue layer 140 and the chip 130 on the substrate 110". In the above steps, the semiconductor structure includes the substrate 110, the insulating layer 120, the second glue layer 122, the first glue layer 140 and the chip 130. Among them, the first glue layer 140 is located on the surface of the insulating layer 120, and the chip 130 is located on the surface of the first glue layer 140. The first glue layer 140 and the chip 130 can be pressed on the surface of the substrate 110 (actually the insulating layer 120) by the pressing device 200.

[0122] like Fig. 9, which is a schematic diagram of the structure of the semiconductor structure in the step of "heating and baking to glue the first glue layer 140 between the chip 130 and the substrate 110". In the above steps, the semiconductor structure includes the substrate 110, the insulating layer 120, the second glue layer 122, the first glue layer 140 and the chip 130. The first glue layer 140 can glue the chip 130 to the substrate 110 through the heating of the heating device 500.

[0123] Furthermore, in this embodiment, for the steps of "heating and baking to solidify the buffer adhesive material into the second adhesive layer 122" and "heating and baking to solidify the first adhesive layer 140 between the chip 130 and the substrate 110", the heating device 400 and the heating device 500 in the above two steps can use the same heating device. On this basis, the heating and baking for solidifying and forming the second adhesive layer 122 can also be understood as "pre-baking", which is different from the heating step of setting the chip 130 in order to solidify the first adhesive layer 140. Accordingly, after "pre-baking", in addition to solidifying and forming the second adhesive layer 122, the loading device of the semiconductor structure can also be preheated.

[0124] like Fig.10 , which is a schematic diagram of the structure of the semiconductor structure in the step of "bonding the chip 130 to the substrate 110". In the above steps, the semiconductor structure includes the substrate 110, the insulating layer 120, the second adhesive layer 122, the first adhesive layer 140, the chip 130 and the lead 150. The lead 150 is connected between the chip 130 and the substrate 110, so as to achieve the bonding of the chip 130 and the substrate 110.

[0125] like Fig.11 As shown, it is a schematic diagram of the structure of the semiconductor structure in the step of "forming a packaging layer 160 on the surface of the insulating layer 120". In the above steps, the semiconductor structure includes a substrate 110, an insulating layer 120, a second adhesive layer 122, a first adhesive layer 140, a chip 130, a lead 150 and a packaging layer 160. The packaging layer 160 is formed on the surface of the substrate 110, and the packaging layer 160 encapsulates various structures on the substrate 110, such as the first adhesive layer 140, the second adhesive layer 122, the chip 130, the lead 150, etc.

[0126] It should be noted that the methods for preparing semiconductor structures shown in the drawings and described in this specification are only a few examples of many methods for preparing semiconductor structures that can employ the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or any steps of the methods for preparing semiconductor structures shown in the drawings or described in this specification.

[0127] In summary, the semiconductor structure and the method for preparing the semiconductor structure proposed in the present invention can optimize the stress distribution at the connection edge between the chip and the substrate by setting a hole groove corresponding to the position of at least a portion of the edge of the first adhesive layer in the insulating layer, and setting a second adhesive layer with an elastic modulus smaller than that of the first adhesive layer in the hole groove, so that the semiconductor structure is not prone to fracture at the connection edge between the chip and the substrate when it is bent or deformed.

[0128] The exemplary embodiments of the semiconductor structure and the method for preparing the semiconductor structure proposed by the present invention are described and / or illustrated in detail above. However, the embodiments of the present invention are not limited to the specific embodiments described herein. On the contrary, the components and / or steps of each embodiment can be used independently and separately from other components and / or steps described herein. Each component and / or each step of an embodiment can also be used in combination with other components and / or steps of other embodiments. When introducing the elements / components / etc. described and / or illustrated herein, the terms "one", "one" and "above" are used to indicate the presence of one or more elements / components / etc. The terms "comprising", "including" and "having" are used to indicate the meaning of open inclusion and mean that in addition to the listed elements / components / etc., there may be other elements / components / etc. In addition, the terms "first" and "second" in the claims and the specification are used only as marks and are not numerical restrictions on their objects.

[0129] Although the semiconductor structure and the method for manufacturing the semiconductor structure proposed by the present invention have been described according to different specific embodiments, those skilled in the art will recognize that the implementation of the present invention can be modified within the spirit and scope of the claims.

Claims

1. A semiconductor structure, comprising a substrate, a chip and a first adhesive layer; an insulating layer is disposed on the surface of the substrate; the chip is disposed on the surface of the insulating layer through the first adhesive layer; characterized in that: The insulating layer is provided with a hole groove, the position of the hole groove corresponds to at least a portion of the edge of the first adhesive layer, a second adhesive layer is provided in the hole groove, and at least a portion of the surface of the second adhesive layer is connected to the first adhesive layer; Wherein, the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the first adhesive layer.

2. The semiconductor structure according to claim 1, characterized in that: The hole penetrates the insulating layer.

3. The semiconductor structure according to claim 1, characterized in that: The hole groove is in a ring-shaped closed structure, so that the hole groove corresponds to the entire edge of the first adhesive layer.

4. The semiconductor structure according to claim 3, characterized in that: The first adhesive layer is rectangular, and the edge of the first adhesive layer has four sides; wherein the holes and grooves are arranged in a rectangular ring.

5. The semiconductor structure according to claim 1, characterized in that: On the surface of the substrate, an outer edge of the orthographic projection pattern of the hole groove is located outside an edge of the orthographic projection pattern of the first adhesive layer.

6. The semiconductor structure according to claim 1, characterized in that On the surface of the substrate, the orthographic projection patterns of the hole grooves are all covered by the orthographic projection patterns of the first adhesive layer, so that the entire surface of the second adhesive layer is connected to the first adhesive layer.

7. The semiconductor structure according to claim 6, characterized in that: On the surface of the substrate, the outer edge of the orthographic projection pattern of the hole groove coincides with the edge of the orthographic projection pattern of the first adhesive layer.

8. The semiconductor structure according to claim 1, characterized in that: The slot width of the hole is 5% to 10% of the width of the first adhesive layer.

9. The semiconductor structure according to claim 1, characterized in that: The elastic modulus of the second adhesive layer is smaller than the elastic modulus of the insulating layer; and / or the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the chip.

10. The semiconductor structure according to claim 1, wherein: The thermal expansion coefficient of the second adhesive layer is smaller than the thermal expansion coefficient of the first adhesive layer.

11. The semiconductor structure according to claim 10, characterized in that: The thermal expansion coefficient of the second adhesive layer is smaller than the thermal expansion coefficient of the insulating layer; and / or the thermal expansion coefficient of the second adhesive layer is smaller than the thermal expansion coefficient of the chip.

12. The semiconductor structure according to claim 1, characterized in that The bonding strength between the first adhesive layer and the second adhesive layer is smaller than the bonding strength between the first adhesive layer and the chip; And / or, the bonding strength between the first adhesive layer and the second adhesive layer is smaller than the bonding strength between the first adhesive layer and the insulating layer.

13. The semiconductor structure according to claim 1, characterized in that The material of the second adhesive layer includes silicone and epoxy resin adhesive.

14. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, wherein an insulating layer is disposed on the surface of the substrate; forming a hole groove penetrating through the insulating layer on the insulating layer; forming a second adhesive layer in the hole groove; A chip is arranged on the surface of the insulating layer through a first adhesive layer, the position of the hole groove corresponds to at least a portion of the edge of the first adhesive layer, at least a portion of the surface of the second adhesive layer is connected to the first adhesive layer, and the elastic modulus of the second adhesive layer is smaller than the elastic modulus of the first adhesive layer; A packaging layer is formed on the surface of the insulating layer, and the chip and the first adhesive layer are packaged in the packaging layer.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The formation of the hole groove comprises the following steps: Disposing a photoresist on the surface of the insulating layer; patterning the photoresist; The patterned photoresist is exposed to remove the portion of the insulating layer not blocked by the photoresist, thereby forming the hole groove.

16. The method for preparing a semiconductor structure according to claim 14, characterized in that: The formation of the second adhesive layer comprises the following steps: dripping a buffering rubber material into the hole groove; The buffer adhesive material is heated and baked to solidify into the second adhesive layer.

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