Bonded semiconductor structure and method of making the same

Abstract

This invention discloses a bonding semiconductor structure and its fabrication method. The bonding semiconductor structure includes a first element wafer and a second element wafer. The first element wafer includes a first insulating layer, a first element layer located on the first insulating layer, a first element region, a first transistor disposed within the first element region, and a first bonding layer located on the first element layer. The second element wafer includes a second insulating layer, a second element layer located on a first side of the second insulating layer, a second element region, a second transistor disposed within the second element region, and a second bonding layer located on the second element layer. The second element wafer is bonded to the first element wafer by bonding the second bonding layer to the first bonding layer. A first shielding structure is located on a second side of the second insulating layer opposite to the first side and overlaps with the second element region in the vertical direction.

Description

Technical Field

[0001] This invention relates to a bonding semiconductor structure and a method for fabricating the same, and more particularly to a bonding semiconductor structure including a shielding structure and a method for fabricating the same. Background Technology

[0002] 3D ICs refer to the use of wafer-level bonding and through-silicon via (TSV) technology to transform traditional two-dimensional chips into three-dimensional stacked chips. Because 3D ICs can effectively utilize space, shorten circuit transmission distances, and provide extremely low-resistance connections, they have gradually become the mainstream technology for power converters, low-noise amplifiers, and radio frequency (RF) or millimeter-wave (MMW) components. However, there are still problems to be improved in 3D ICs, such as heat dissipation and electromagnetic shielding of stacked chips, as well as harmonic distortion and crosstalk during operation. Further miniaturization of 3D ICs remains a subject of ongoing research in this field. Summary of the Invention

[0003] The present invention aims to provide a bonding semiconductor structure and its fabrication method. A shielding structure is provided on one side of the insulating layer relative to the semiconductor layer, and the shielding structure overlaps with the device area of ​​the semiconductor layer in the vertical direction. The shielding structure helps dissipate heat from the device area and also provides electromagnetic shielding. Furthermore, the present invention also provides a bonding semiconductor structure including mirrored dual transistors, which achieves good transistor matching and provides the same current while reducing the device area by half, thereby achieving a smaller foam factor and reducing harmonic distortion and signal crosstalk problems.

[0004] According to an embodiment of the present invention, a bonding semiconductor structure includes a first element wafer, a second element wafer, and a first shielding structure. More specifically, the first element wafer includes a first insulating layer and a first element layer, located on the first insulating layer, and includes a first element region and a first transistor disposed within the first element region, and a first bonding layer located on the first element layer. The second element wafer includes a second insulating layer and a second element layer, located on a first side of the second insulating layer, and includes a second element region and a second transistor disposed within the second element region, and a second bonding layer located on the second element layer, wherein the second element wafer is bonded to the first element wafer by bonding the second bonding layer to the first bonding layer. The first shielding structure is located on a second side of the second insulating layer opposite to the first side and overlaps with the second element region in the vertical direction.

[0005] According to another embodiment of the present invention, a bonding semiconductor structure includes a first element wafer, a second element wafer disposed on the first element wafer, a third element wafer disposed on the second element wafer, a first shielding structure disposed between the second element wafer and the third element wafer, and a second shielding structure disposed on the third element wafer. More specifically, the first element wafer includes a first insulating layer and a first element layer disposed on the first insulating layer, and includes a first element region and a first transistor disposed within the first element region, and a first bonding layer disposed on the first element layer. The second element wafer includes a second insulating layer and a second element layer disposed on a first side of the second insulating layer, and includes a second element region and a second transistor disposed within the second element region, and a second bonding layer disposed on the second element layer, wherein the second element wafer is bonded to the first element wafer by bonding the second bonding layer to the first bonding layer. The first shielding structure is located on a second side of the second insulating layer opposite to the first side and overlaps with the second element region in the vertical direction. The third element wafer includes a third insulating layer, a third element layer located on a first side of the third insulating layer, and includes a third element region and a third transistor disposed in the third element region, and a third bonding layer located on the third element layer. The bonding semiconductor structure further includes a fourth insulating layer located on a second side of the second insulating layer and covering the first shielding structure, and a fourth bonding layer located on the fourth insulating layer, wherein the third element wafer is bonded to the second element wafer by bonding the third bonding layer to the fourth bonding layer. The second shielding structure is located on a second side of the third insulating layer opposite to the first side and overlaps with the third element region in the vertical direction.

[0006] A method for fabricating a semiconductor structure according to another embodiment of the present invention includes the following steps. First, a first element wafer and a second element wafer are provided. The first element wafer includes a first insulating layer, a first element layer located on the first insulating layer, a first element region and a first transistor disposed within the first element region, and a first bonding layer located on the first element layer. The second element wafer includes a second insulating layer, a second element layer located on a first side of the second insulating layer, a second element region and a second transistor disposed within the second element region, and a second bonding layer located on the second element layer. Next, the first bonding layer and the second bonding layer are bonded, and then a first via is formed, which passes through the second insulating layer and a portion of the second element layer from a second side of the second insulating layer relative to the first side and is electrically connected to the second transistor. Then, a first shielding structure and a first conductive structure are formed on the second side of the second insulating layer, wherein the first shielding structure overlaps with the second element region in the vertical direction, and the first conductive structure directly contacts the first via. Attached Figure Description

[0007] Figures 1 to 4 This is a cross-sectional schematic diagram of the steps in the fabrication method of the bonding semiconductor structure according to the first embodiment of the present invention;

[0008] Figure 5 This is a component circuit diagram of an embodiment of the present invention;

[0009] Figure 6 and Figure 7 This is a schematic diagram of the planar layout of the shielding structure according to some embodiments of the present invention;

[0010] Figure 8 This is a cross-sectional schematic diagram of the bonding semiconductor structure according to the second embodiment of the present invention;

[0011] Figure 9 This is a schematic cross-sectional view of the bonding semiconductor structure according to the third embodiment of the present invention;

[0012] Figure 10 This is a cross-sectional schematic diagram of the bonding semiconductor structure according to the fourth embodiment of the present invention.

[0013] Explanation of main component symbols

[0014] 100 First Component Wafer

[0015] 102 First Layer

[0016] 104 First Insulation Layer

[0017] 105 First Component Layer

[0018] 106 First Semiconductor Layer

[0019] 108 First Interconnect Layer

[0020] 108a Contact plug

[0021] 108b interconnect structure

[0022] 110 First bonding layer

[0023] 110a First bonding dielectric layer

[0024] 110b First joint pad

[0025] 116 First Transistor

[0026] 116R First Component Region

[0027] 116D First Drain Region

[0028] 116G First Gate Region

[0029] 116S First Source Polar Region

[0030] 200 Second Component Wafer

[0031] 202 Second bottom layer

[0032] 204 Second Insulation Layer

[0033] 204a First Side

[0034] 204b Second Side

[0035] 205 Second Component Layer

[0036] 206 Second Semiconductor Layer

[0037] 208 Second Interconnect Layer

[0038] 208a Contact plug

[0039] 208b interconnect structure

[0040] 210 Second bonding layer

[0041] 210a Second bonding dielectric layer

[0042] 210b Second Joint Pad

[0043] 216 Second Transistor

[0044] 216R Second Component Region

[0045] 216D Second Drain Region

[0046] 216G Second Gate Region

[0047] 216S Second Source Polar Region

[0048] 222 First Through Hole

[0049] 224 First conductive structure

[0050] 226 First Shielding Structure

[0051] 226a Metallic Materials

[0052] 230 passivation layer

[0053] 300 Third Component Chip

[0054] 304 Third Insulation Layer

[0055] 304a First Side

[0056] 304b Second Side

[0057] 305 Third Component Layer

[0058] 306 Third Semiconductor Layer

[0059] 308 Third Interconnect Layer

[0060] 308a Contact Plug

[0061] 308b interconnect structure

[0062] 310 Third bonding layer

[0063] 310a Third bonding dielectric layer

[0064] 310b Third Joint Pad

[0065] 312 Shielding Structure

[0066] 316 Third Transistor

[0067] 316R Third Component Area

[0068] 322 Second Through Hole

[0069] 324 Second Conductive Structure

[0070] 408 Fourth Insulation Layer

[0071] 410 Fourth bonding layer

[0072] 410a Fourth bonding dielectric layer

[0073] 410b Fourth Joint Pad

[0074] 412 Shielding Structure

[0075] OP opening

[0076] S1 mating surface

[0077] S2 mating surface

[0078] Vd drain voltage

[0079] Vg gate voltage

[0080] Vs Source Voltage Detailed Implementation

[0081] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in conjunction with the accompanying drawings. The accompanying drawings are schematic diagrams and not drawn to scale, and the same or similar features are generally described using the same reference numerals. The embodiments and drawings described herein are for reference and illustration only and are not intended to limit the invention. The scope of the invention is defined by the claims. Anything with the same meaning as the claims of the present invention should also be included within the scope of the present invention.

[0082] The meanings of "on," "above," and "above" in this text should be interpreted in the broadest sense, such that "on" is not limited to referring to "directly on" something, but may also include the meaning of "on" something with an intermediate feature or layer. Similarly, "above" or "above" is not limited to the meaning of "above" or "above" something, but may also include the meaning of "directly above" or "directly above" something without an intermediate feature or layer.

[0083] For ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one device or feature and another (or more) devices or features as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the element in use or operation. The element may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially related descriptive terms used herein may be interpreted accordingly.

[0084] As used herein, the term "substrate" refers to the material on which components are fabricated and / or on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0085] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located in a region between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, and a substrate may include one or more layers, and / or may have one or more layers on, above, and / or below it. The term "layer" as used herein may include one or more layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0086] Please refer to Figures 1 to 4 The diagram shown is a cross-sectional schematic diagram of the steps in fabricating a bonded semiconductor structure according to a first embodiment of the present invention. Figure 1 As shown, a first component chip 100 and a second component chip 200 are provided first.

[0087] According to one embodiment of the present invention, a first element wafer 100 may be fabricated using a silicon on-insulator (SOI) substrate, comprising a first bottom layer 102, a first insulating layer 104 disposed on the first bottom layer 102, a first element layer 105 disposed on the first insulating layer 104, and a first bonding layer 110 disposed on the first element layer 105. The first bottom layer 102 may include a semiconductor material, such as a silicon substrate, and preferably a lightly doped silicon substrate with high resistance. In some embodiments, the first bottom layer 102 may have a charge trap layer (not shown) on its surface in contact with the first insulating layer 104, which can reduce harmonic distortion and signal crosstalk caused by induced charges generated in the first bottom layer 102 during element operation. The first insulating layer 104 is used to electrically isolate the first semiconductor layer 106 of the first bottom layer 102 and the first element layer 105, and may include an insulating material, such as silicon oxide. The first element layer 105 may include the first semiconductor layer 106 and a first interconnect layer 108 disposed on the first semiconductor layer 106. The first semiconductor layer 106 may include semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), carbon-doped silicon-germanium (SiGe:C), carbon-doped silicon (SiC), or combinations thereof, but is not limited thereto. The first semiconductor layer 106 may include a first element region 116R, which is the region where the first transistor 116 is disposed. According to an embodiment of the present invention, the first transistor 116 is, for example, a field-effect transistor (FET), which may include a first source region 116S and a first drain region 116D disposed in the first semiconductor layer 106, and a first gate region 116G disposed on the first semiconductor layer 106 between the first source region 116S and the first drain region 116D and separated from the first semiconductor layer 106 by a gate dielectric layer (not shown), for controlling the conduction or deactivation of the channel region between the first source region 116S and the first drain region 116D. The first interconnect layer 108 may include multiple dielectric material layers (not shown), such as silicon oxide, silicon nitride, or other suitable dielectric materials, and electrical connection structures, such as contact plugs 108a and interconnect structures 108b, made of metals such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, or tantalum nitride, disposed in these dielectric material layers. The first interconnect layer 108 may also include circuit elements such as capacitors, inductors, resistors, embedded memory, etc., which are not shown for simplicity. The first source region 116S, the first drain region 116D, and the first gate region 116G of the first transistor 116 can be electrically connected to the interconnect structure 108b through the contact plug 108a. The first bonding layer 110 may include a first bonding dielectric layer 110a and a plurality of first bonding pads 110b disposed in the first bonding dielectric layer 110a.The first bonding dielectric layer 110a may include a dielectric material, such as silicon oxide, silicon nitride, or other dielectric material suitable for bonding with the second bonding dielectric layer 210a of the second element wafer 200. The first bonding pad 110b may include a conductive metal, such as copper, suitable for bonding with the second bonding pad 210b of the second element wafer 200.

[0088] According to one embodiment of the present invention, the second element wafer 200 can be fabricated using a silicon on-insulator (SOI) substrate, which may include a second bottom layer 202, a second insulating layer 204 disposed on the second bottom layer 202, a second element layer 205 disposed on the second insulating layer 204, and a second bonding layer 210 disposed on the second element layer 205. In other words, the second element layer 205 and the second bottom layer 202 are respectively disposed on a first side 204a and a second side 204b opposite to the second insulating layer 204. The second bottom layer 102 may include a semiconductor material, such as a silicon substrate, or other bottom material suitable for supporting the second element wafer 200 in a semiconductor fabrication process. The second insulating layer 204 is used to electrically isolate the second semiconductor layer 206 of the second bottom layer 102 and the second element layer 205, and may include an insulating material, such as silicon oxide. The second element layer 205 may include the second semiconductor layer 206 and a second interconnect layer 108 disposed on the second semiconductor layer 206. The second semiconductor layer 206 may include semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), carbon-doped silicon-germanium (SiGe:C), carbon-doped silicon (SiC), or combinations thereof, but is not limited thereto. The second semiconductor layer 206 may include a second element region 216R, which is the region where the second transistor 216 is disposed. According to one embodiment of the present invention, the second transistor 216 is, for example, a field-effect transistor (FET), which may include a second source region 216S and a second drain region 216D disposed in the second semiconductor layer 206, and a second gate region 216G disposed on the second semiconductor layer 206 between the second source region 216S and the second drain region 216D and separated from the second semiconductor layer 206 by a gate dielectric layer (not shown), for controlling the conduction or deactivation of the channel region between the second source region 216S and the second drain region 216D. The second interconnect layer 208 may include multiple dielectric material layers (not shown), such as silicon oxide, silicon nitride, or other suitable dielectric materials, and electrical connection structures made of metals such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, or tantalum nitride disposed in these dielectric material layers, such as contact plugs 208a and interconnect structures 208b. It may also include circuit elements such as capacitors, inductors, resistors, embedded memory, etc., which are not shown for simplicity. The second source region 216S, the second drain region 216D, and the second gate region 216G of the second transistor 216 can be electrically connected to the interconnect structure 208b via contact plugs 208a. The second bonding layer 210 may include a second bonding dielectric layer 210a and a plurality of second bonding pads 210b disposed in the second bonding dielectric layer 210a.The second bonding dielectric layer 210a may include a dielectric material, such as silicon oxide, silicon nitride, or other dielectric materials suitable for bonding with the first bonding dielectric layer 110a of the first element wafer 100. The second bonding pad 210b may include a conductive metal, such as copper, suitable for bonding with the first bonding pad 110b of the first element wafer 100.

[0089] like Figure 2 As shown, the second component wafer 200 is then positioned such that the second bonding layer 210 faces the first bonding layer 110 of the first component wafer 100. The corresponding first bonding pad 110b and second bonding pad 210b are bonded and electrically connected by direct bonding technology. At the same time, the first bonding dielectric layer 110a and the second bonding dielectric layer 210a that are in contact with each other are bonded to each other, thereby stacking and bonding the second component wafer 200 onto the first component wafer 100, with a bonding surface S1 between them.

[0090] like Figure 3 As shown, the second bottom layer 202 of the second element wafer 200 can then be removed by grinding or etching processes to expose the second side 204b of the second insulating layer 204. A first via 222 is then formed, extending from the second side 204b through the second insulating layer 204 and a portion of the second element layer 205, and electrically connected to the interconnect structure 208b within the second element layer 205, thereby electrically connecting to the second transistor 216. Next, a first shielding structure 226 and a first conductive structure 224 directly contacting the end of the first via 222 are formed on the second side 204b of the second insulating layer 204. Specifically, the first shielding structure 226 overlaps the second element region 216R in the vertical direction (i.e., the stacking direction), preferably with the first shielding structure 226 overlapping the entire area of ​​the second element region 216R, to provide better heat dissipation and electromagnetic shielding for the second element region 216R. According to one embodiment of the present invention, the first shielding structure 226 and the first conductive structure 224 may be formed simultaneously by the same manufacturing process and include the same metallic material, such as copper, aluminum, nickel, silver, tin, platinum, titanium, iron, or alloys thereof, but are not limited thereto. In other embodiments, different steps or different metallic materials may be used to form the first shielding structure 226 and the first conductive structure 224.

[0091] like Figure 4As shown, a passivation layer 230 is then formed on the second side 204b of the second insulating layer 204. The passivation layer 230 is then patterned to form openings that expose portions of the first conductive structure 224, but do not expose any portion of the first shielding structure 226. The passivation layer 230 may include, but is not limited to, an organic dielectric material, such as polyimide (PI). In this embodiment, the first conductive structure 224 serves as a pad for electrical connection to the outside. The first shielding structure 226 is surrounded by the second insulating layer 204 and the passivation layer 230, and is electrically isolated from other structures.

[0092] Please continue to refer to this. Figure 4 Also refer to Figure 5 The circuit diagram shown is illustrated. According to an embodiment of the present invention, by designing the layout of the first transistor 116 and the second transistor 216, after the first component wafer 100 and the second component wafer 200 are bonded, the first source region 116S, the first drain region 116D, and the first gate region 116G of the first transistor 116 are vertically aligned with the second source region 216S, the second drain region 216D, and the second gate region 216G of the second transistor 216, respectively. This facilitates electrical connection using contact plugs 108a and 208a and interconnect structures 1018b and 208b, achieving the following: Figure 5 The circuit shown. Preferably, the first transistor 116 and the second transistor 216 can be mirror images of each other along the junction surface S1 to achieve good transistor matching.

[0093] like Figure 5 As shown, the first source region 116S and the second source region 216S are coupled to the same source voltage Vs, the first drain region 116D and the second drain region 216D are coupled to the same drain voltage Vd, and the first gate region 116G and the second gate region 216G are coupled to the same gate voltage Vg. This design allows for the synchronous driving of the first transistor 116 and the second transistor 216 to provide the combined current. In other words, compared to the prior art which provides the required current with a single transistor, this invention has at least the following advantages: First, this invention can provide the required current while reducing the component area by half, thus enabling a smaller chip form factor. Second, due to the reduction in transistor component area, i.e., the smaller overlap area between the transistor component and the first bottom layer 102, problems such as harmonic distortion and signal crosstalk caused by the induced charge of the first bottom layer 102 can be reduced. Third, the first shielding structure 226 can simultaneously overlap the first component region 116R and the second component region 216R in the vertical direction, providing electromagnetic shielding for both the first transistor 116 and the second transistor 216 simultaneously.

[0094] Please refer to Figure 6 and Figure 7 The diagram shown is a planar layout schematic of a shielding structure (e.g., a first shielding structure 226) according to some embodiments of the present invention. Figure 6 As shown, the first shielding structure 226 may include a metal material 226a, and the metal material 226a has multiple openings OP formed therein, constituting a mesh-like pattern. Figure 7 As shown, the first shielding structure 226 may include multiple strip-shaped metal materials 226a, which together form a strip-shaped pattern array. It should be understood that the above-described layout of the shielding structure is only an example, and can be adjusted according to design requirements in actual applications. The pattern of the first shielding structure 226 preferably overlaps the entire range of the component area (e.g., the second component area 216R) to provide better heat dissipation and electromagnetic shielding effects.

[0095] The following description will focus on different embodiments of the present invention. For simplicity, the description will primarily focus on the differences between the embodiments, without repeating the similarities. Identical elements in each embodiment are designated with the same reference numerals to facilitate comparison between embodiments.

[0096] Figure 8 The diagram shown is a cross-sectional schematic of a junction semiconductor structure according to a second embodiment of the present invention, which is consistent with... Figure 4 The main difference in the junction semiconductor structure of the first embodiment shown is that, Figure 8 A third element chip 300 is also bonded to the second element chip 200.

[0097] In detail, after bonding the first element wafer 100 and the second element wafer 200 and forming a first shielding structure 226 and a first conductive structure 224 on the second side 204b of the second insulating layer 204, a fourth insulating layer 408 is then formed on the second side 204b of the second insulating layer 204 to completely cover the first shielding structure 226 and the first conductive structure 224, and then a fourth bonding layer 410 is formed on the fourth insulating layer 408. The fourth insulating layer 408 may include a single layer or multiple layers of dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The fourth bonding layer 410 may include a fourth bonding dielectric layer 410a and a plurality of fourth bonding pads 410b disposed in the fourth bonding dielectric layer 410a. The fourth bonding dielectric layer 410a may include a dielectric material, such as silicon oxide, silicon nitride, or other dielectric materials suitable for bonding with the third bonding dielectric layer 310a of the third element wafer 300. The fourth bonding pad 410b may include a conductive metal, such as copper, suitable for bonding with the third bonding pad 310b of the third element wafer 300.

[0098] like Figure 8As shown, the third element wafer 300 may include a third insulating layer 304 having a first side 304a and a second side 304b opposite to the first side 304a, a third element layer 305 located on the first side 304a, and a third bonding layer 310 located on the third element layer 305. The third insulating layer 304 may include an insulating material, such as silicon oxide. The third element layer 305 may include a third semiconductor layer 306 and a third interconnect layer 308 disposed on the third semiconductor layer 306. The third semiconductor layer 306 may include semiconductor materials, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), carbon-doped silicon-germanium (SiGe:C), carbon-doped silicon (SiC), or combinations thereof, but is not limited thereto. The third semiconductor layer 306 may include a third element region 316R, which is the region where a third transistor 316 is disposed. The third transistor 316 may be, for example, a field-effect transistor (FET) or other active or passive semiconductor device. The third interconnect layer 308 may include multiple dielectric material layers (not shown) and electrical connection structures disposed in these dielectric material layers, such as contact plugs 308a and interconnect structures 308b. It may also include circuit elements such as capacitors, inductors, resistors, embedded memory, etc., which are not shown for simplicity. The ends (e.g., source, drain, and gate) of the third transistor 316 can be electrically connected to the interconnect structure 308b through contact plugs 308a. It should be noted that the third element wafer 300 can be fabricated using a silicon-on-insulator (SOI) substrate, that is, a third bottom layer (not shown) may be provided on the second side 304b of the third insulating layer 304, such as a silicon substrate, or other bottom material suitable for supporting the third element wafer 300 in semiconductor fabrication processes.

[0099] like Figure 8 As shown, the third bonding layer 310 may include a third bonding dielectric layer 310a and a plurality of third bonding pads 310b disposed in the third bonding dielectric layer 310a. The third element wafer 300 is positioned with the third bonding layer 310 facing the fourth bonding layer 410. Through direct bonding technology, corresponding third bonding pads 310b and fourth bonding pads 410b are bonded and electrically connected, while the fourth bonding dielectric layer 410a and the third bonding dielectric layer 310a, which are in contact with each other, are bonded together. This stacks and bonds the third element wafer 300 onto the second element wafer 200, forming a bonding surface S2 between the third bonding layer 310 and the fourth bonding layer 410. In some embodiments, the third transistor 316 may be electrically connected to the semiconductor elements of the second element wafer 200 and the first element wafer 100 through the configuration of contact plugs 308a, interconnect structures 308b, the third bonding layer 310, the fourth bonding layer 410, the first conductive structure 224, and the first via 222.

[0100] Subsequently, the third bottom layer (not shown) is removed, exposing the second side 304b of the third insulating layer 304. Then, a second via 322 is formed, penetrating the third insulating layer 304 and a portion of the third element layer 305 from the second side 304b, and electrically connected to the interconnect structure 308b, thereby electrically connecting to the third transistor 316. Next, a second shielding structure 326 and a second conductive structure 324 directly contacting the end of the second via 322 are formed on the second side 304b of the third insulating layer 304. Specifically, the second shielding structure 326 overlaps the third element region 316R in the vertical direction (i.e., the stacking direction), preferably with the second shielding structure 326 overlapping the entire area of ​​the third element region 316R, to provide better heat dissipation and electromagnetic shielding effects. According to one embodiment of the present invention, the second shielding structure 326 and the second conductive structure 324 may be formed simultaneously using the same manufacturing process and may include the same metallic material, such as copper, aluminum, nickel, silver, tin, platinum, titanium, iron, or alloys thereof, but are not limited thereto. In other embodiments, different steps or different metal materials may be used to form the second shielding structure 326 and the second conductive structure 324. Subsequently, a passivation layer 330 is formed on the second side 304b of the third insulating layer 304 to completely cover the second shielding structure 326 and expose a portion of the second conductive structure 324 through an opening.

[0101] In the second embodiment, the second conductive structure 324 serves as a contact pad for electrical connection to the outside. The second shielding structure 326 is surrounded by a third insulating layer 304 and a passivation layer 330, and the first shielding structure 226 is surrounded by a second insulating layer 204 and a fourth insulating layer 408, both of which are electrically isolated from other structures. In some embodiments, the first element region 116R, the second element region 216R, the first shielding structure 226, the third element region 316R, and the second shielding structure 326 can overlap in the vertical direction to obtain a better electromagnetic shielding effect.

[0102] Figure 9 The diagram shown is a cross-sectional schematic of a junction semiconductor structure according to a third embodiment of the present invention, which is consistent with... Figure 8 The main difference in the junction semiconductor structure of the second embodiment shown is that, Figure 9 Instead of a shielding structure on the second insulating layer 204, shielding structures 412 and 312 are respectively provided in the fourth bonding layer 410 and the third bonding layer 310. Shielding structures 412 and 312 can simultaneously provide electromagnetic shielding and act as bonding pads, forming the bonding surface S2 between the second element wafer 200 and the third element wafer 300 together with the fourth bonding dielectric layer 410a, the fourth bonding pad 410b, the third bonding dielectric layer 310a, and the third bonding pad 310. Compared to... Figure 8 The second embodiment, Figure 9 The third embodiment places the shielding structure in the bonding layer, which can provide greater layout flexibility for the circuitry (e.g., the first conductive structure 224) within the fourth insulating layer 408.

[0103] Figure 10 The diagram shown is a cross-sectional schematic of a junction semiconductor structure according to a fourth embodiment of the present invention, which is consistent with... Figure 9 The main difference in the junction semiconductor structure of the third embodiment shown is that, Figure 10 The fourth bonding layer 410, which has a shielding structure 412, is directly disposed on the second side 204b of the second insulating layer 204, and no insulating layer is disposed between the two (e.g., Figure 9 The fourth insulating layer 408 reduces the overall height of the bonding semiconductor structure compared to the other embodiments described above.

[0104] In summary, the bonding semiconductor structure provided by this invention, by providing a shielding structure on one side (i.e., the second side) of the insulating layer relative to the semiconductor layer and overlapping the shielding structure with the device region of the semiconductor layer in the vertical direction, not only helps dissipate heat from the device region but also provides electromagnetic shielding for the device region. Furthermore, the mirrored dual transistor (e.g., [missing information]) of the bonding semiconductor structure provided by this invention... Figure 4 The design of the first transistor 116 and the second transistor 216 enables good transistor matching and provides the same amount of current while reducing the component area by half, resulting in a smaller chip form factor and reducing harmonic distortion and signal crosstalk issues.

[0105] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A junction semiconductor structure, characterized in that, include: The first component chip includes: First insulating layer; A first element layer is located on the first insulating layer and includes a first element region and a first transistor disposed within the first element region; as well as The first bonding layer is located on the first element layer; The second component chip includes: Second insulating layer; The second element layer is located on the first side of the second insulating layer and includes a second element region and a second transistor disposed within the second element region; as well as A second bonding layer is located on the second element layer, wherein the second element wafer is bonded to the first element wafer by bonding the second bonding layer to the first bonding layer; and The first shielding structure is located on the second side of the second insulating layer opposite to the first side, and overlaps with the second element region in the vertical direction. The first transistor and the second transistor are mirror images of each other along the bonding surface between the first bonding layer and the second bonding layer. The first gate region, the first source region, and the first drain region of the first transistor are respectively aligned and electrically connected with the second gate region, the second source region, and the second drain region of the second transistor in the vertical direction.

2. The bonding semiconductor structure as claimed in claim 1, further comprising: A first through-hole passes through the second insulating layer and a portion of the second element layer and is electrically connected to the second transistor; and A first conductive structure is disposed on the second side of the second insulating layer and directly contacts the first through hole.

3. The junction semiconductor structure as claimed in claim 2, wherein the first shielding structure and the first conductive structure comprise the same metallic material.

4. The bonding semiconductor structure as claimed in claim 2, further comprising a passivation layer located on the second side of the second insulating layer, completely covering the first shielding structure and exposing a portion of the first conductive structure.

5. The bonding semiconductor structure of claim 1, wherein the first bonding layer includes a first bonding dielectric layer and a plurality of first bonding pads disposed in the first bonding dielectric layer, and the second bonding layer includes a second bonding dielectric layer and a plurality of second bonding pads disposed in the second bonding dielectric layer, wherein the plurality of first bonding pads are electrically bonded to one of the plurality of second bonding pads respectively.

6. The junction semiconductor structure of claim 1, wherein the first shielding structure is electrically isolated.

7. The bonding semiconductor structure of claim 1, wherein the first shielding structure comprises a sieve pattern.

8. The bonding semiconductor structure of claim 1, wherein the first shielding structure comprises a strip pattern array.

9. A junction semiconductor structure, characterized in that, include: The first component chip includes: First insulating layer; A first element layer is located on the first insulating layer and includes a first element region and a first transistor disposed within the first element region; as well as A first bonding layer is located on the first element layer; The second component chip includes: Second insulating layer; The second element layer is located on the first side of the second insulating layer and includes a second element region and a second transistor disposed within the second element region; as well as A second bonding layer is located on the second element layer, wherein the second element wafer is bonded to the first element wafer by bonding the second bonding layer to the first bonding layer; The first shielding structure is located on the second side of the second insulating layer relative to the first side, and overlaps with the second element region in the vertical direction; A fourth insulating layer is located on the second side of the second insulating layer and covers the first shielding structure; The fourth bonding layer is located on the fourth insulating layer; The third component chip includes: Third insulating layer; The third element layer is located on the first side of the third insulating layer and includes a third element region and a third transistor disposed in the third element region; as well as A third bonding layer is located on the third element layer, wherein the third element wafer is bonded to the second element wafer by bonding the third bonding layer to the fourth bonding layer; as well as The second shielding structure is located on the second side of the third insulating layer opposite to the first side, and overlaps with the third element region in the vertical direction. The first gate region, the first source region, and the first drain region of the first transistor are respectively aligned and electrically connected with the second gate region, the second source region, and the second drain region of the second transistor in the vertical direction.

10. The junction semiconductor structure of claim 9, further comprising: The second via passes through the third insulating layer and a portion of the third element layer and is electrically connected to the third transistor; and The second conductive structure is disposed on the second side of the third insulating layer and directly contacts the second through hole.

11. The bonding semiconductor structure of claim 10, further comprising a passivation layer disposed on the second side of the third insulating layer, completely covering the second shielding structure and exposing a portion of the second conductive structure.

12. A method for fabricating a semiconductor structure, comprising: Provides a first component chip, including: First insulating layer; A first element layer is located on the first insulating layer and includes a first element region and a first transistor disposed within the first element region; as well as A first bonding layer is located on the first element layer; Provide a second component chip, including: Second insulating layer; The second element layer is located on the first side of the second insulating layer and includes a second element region and a second transistor disposed within the second element region; as well as The second bonding layer is located on the second element layer; Join the first bonding layer and the second bonding layer; A first through-hole is formed, which passes through the second insulating layer and a portion of the second element layer from the second side of the second insulating layer relative to the first side and is electrically connected to the second transistor; A first shielding structure and a first conductive structure are formed on the second side of the second insulating layer, wherein the first shielding structure overlaps with the second element region in the vertical direction, and the first conductive structure directly contacts the first through-hole. The first transistor and the second transistor are mirror images of each other along the bonding surface between the first bonding layer and the second bonding layer. The first gate region, the first source region, and the first drain region of the first transistor are respectively aligned and electrically connected with the second gate region, the second source region, and the second drain region of the second transistor in the vertical direction.

13. The method for fabricating a bonding semiconductor structure as described in claim 12, wherein the first shielding structure and the first conductive structure comprise the same metallic material.

14. The method for fabricating a semiconductor structure as described in claim 12, further comprising: A passivation layer is formed on the second side of the second insulating layer, completely covering the first shielding structure and exposing a portion of the first conductive structure.

15. The method for fabricating a semiconductor structure as described in claim 12, further comprising: A fourth insulating layer is formed on the second side of the second insulating layer, completely covering the first shielding structure and the first conductive structure; A fourth bonding layer is formed on the fourth insulating layer; Provide third-party component chips, including: Third insulating layer; The third element layer is located on the first side of the third insulating layer and includes a third element region and a third transistor disposed in the third element region; as well as The third bonding layer is located on the third element layer; Join the third bonding layer and the fourth bonding layer; as well as A second shielding structure is formed on the second side of the third insulating layer relative to the first side, wherein the second shielding structure overlaps with the third element region in the vertical direction.

16. The method of fabricating a bonded semiconductor structure as claimed in claim 12, wherein the first transistor and the second transistor are aligned in the vertical direction.

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