Power management circuitry and systems thereof

Abstract

The present application relates to a power management circuit and system thereof, the power management circuit includes MxN operation units, a first power supply unit, a second power supply unit and N-1 connection interfaces, M and N are both natural numbers greater than 1, the first power supply unit is used for supplying power to the Nth row operation unit in the MxN operation units, the Nth row operation unit supplies power to the N-1th row operation unit respectively, and so on to the second row operation unit supplies power to the first row operation unit respectively. The second power supply unit is used for supplying current to the MxN operation units, and the N-1 connection interfaces are respectively coupled to the corresponding operation unit of the first column in the MxN operation units.

Description

Technical Field

[0001] This invention relates to a power management technology, and more particularly to a power management circuit and system suitable for a two-dimensional accelerator chip (containing multiple computing units). Background Technology

[0002] In recent years, to improve the computing efficiency of computing chips, a large number of accelerator chips have been applied to them. However, the current of existing high-power power supply units is insufficient to provide the power required by a large number of accelerator chips.

[0003] In addition, existing acceleration chips are all one-dimensional architectures, and the power and data transmission between each computing unit are in the same direction. In other words, when one computing unit burns out or stops working, the power and data of the entire architecture cannot be transmitted normally, resulting in a complete transmission failure.

[0004] Furthermore, in the existing technology's overall architecture, in addition to the need for interfaces between computing units within each row to transmit power and data, interfaces are also required between computing units in different rows for power and data transmission. Therefore, the existing technology's overall architecture requires a large number of connection interfaces, resulting in a complex design and high cost.

[0005] Furthermore, due to the rapid development of semiconductor manufacturing technology, the operating power supply voltage of integrated circuit chips is getting lower and lower. Therefore, the power management and efficiency of integrated circuit chips have become one of the important factors that need to be considered when designing integrated circuit chips.

[0006] In view of the above, how to provide a high-efficiency power management circuit and system that can effectively supply power to the two-dimensional acceleration chip and significantly reduce the number of connection interfaces connected to the two-dimensional computing unit, thereby reducing the overall chip size, improving power and data transmission efficiency, and reducing chip cost has become a very important issue. Summary of the Invention

[0007] This invention provides a power management circuit and system applicable to power management and supply of a two-dimensional accelerator chip (containing multiple computing units). In addition to effectively providing power to all two-dimensional computing units, it can also significantly reduce the number of connection interfaces connected to the two-dimensional computing units, thereby reducing the overall chip size and improving power and data transmission efficiency.

[0008] The power management circuit of the present invention includes: M×N arithmetic units, wherein M and N are both natural numbers greater than 1; a first power supply unit coupled to and supplying power to the Nth row arithmetic unit of the M×N arithmetic units, wherein the Nth row arithmetic unit is coupled to and supplying power to the (N-1)th row arithmetic unit; a second power supply unit coupled to and supplying power to the M×N arithmetic units; and N-1 connection interfaces, which are respectively coupled to the corresponding arithmetic unit of the first column of the M×N arithmetic units.

[0009] In one embodiment, the first power supply unit includes a single power source to be coupled to and power the first to Mth column arithmetic units of the Nth row arithmetic unit.

[0010] In another embodiment, the first power supply unit includes less than or equal to M power sources, which are respectively coupled to and supply power to the first to the Mth column arithmetic units of the Nth row arithmetic unit.

[0011] In one embodiment, the second power supply unit includes less than or equal to N DC-to-DC converters or less than or equal to N low-dropout regulators (LDO regulators) to supply power to the Mth column arithmetic units in the Nth row to the 1st row arithmetic units, respectively, through the less than or equal to N DC-to-DC converters or the less than or equal to N LDO regulators.

[0012] In one embodiment, each of the N-1 connection interfaces includes a unidirectional circuit for transmission to the corresponding arithmetic unit and a unidirectional circuit for transmission from the corresponding arithmetic unit.

[0013] In another embodiment, each of the N-1 connection interfaces includes bidirectional circuitry for transmission to and from the corresponding arithmetic unit.

[0014] In one embodiment, the corresponding operation unit includes the Nth row operation unit to the second row operation unit in the first column operation unit.

[0015] In one embodiment, one end of each arithmetic unit in the first row of arithmetic units is coupled to ground.

[0016] In one embodiment, when any of the M×N arithmetic units needs to perform input / output transmission, the second power supply unit supplies power only to that specific unit.

[0017] The power management system of the present invention includes: M×N arithmetic units, wherein M and N are both natural numbers greater than 1; a first power supply unit coupled to and supplying power to the Nth row arithmetic unit of the M×N arithmetic units, wherein the Nth row arithmetic unit is coupled to and supplying power to the (N-1)th row arithmetic unit; a second power supply unit coupled to and supplying power to the M×N arithmetic units; N-1 connection interfaces, each coupled to the corresponding arithmetic unit in the first column of the M×N arithmetic units; and a processor coupled to the N-1 connection interfaces.

[0018] In one embodiment, the processor is coupled to the N-1 connection interfaces through N-1 input / output terminals of the multiple input / output terminals, and the processor is directly coupled to the arithmetic unit in the first column and first row through another input / output terminal of the multiple input / output terminals.

[0019] In another embodiment, the processor is coupled to the N-1 connection interfaces and the arithmetic unit in the first column and first row via a single input / output terminal.

[0020] In one embodiment, each of the N-1 connection interfaces includes a unidirectional circuit for transmitting data from the processor to the corresponding arithmetic unit and a unidirectional circuit for transmitting data from the corresponding arithmetic unit to the processor.

[0021] In another embodiment, each of the N-1 connection interfaces includes bidirectional circuitry for transmission between the processor and the corresponding arithmetic unit.

[0022] To make the above-described features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Additional features and advantages of the invention will be set forth in part in the following description, and these features and advantages will be apparent in part from the description or may be learned by practice of the invention. It should be understood that both the foregoing general description and the following detailed description are illustrative and explanatory only and are not intended to limit the scope claimed by the invention. Attached Figure Description

[0023] Figure 1 A schematic diagram of the power management circuit and system of the present invention is shown according to an embodiment of the present invention.

[0024] Figure 2 According to another embodiment of the present invention, a schematic diagram of the power management circuit and system of the present invention is shown.

[0025] Figure 3 According to an embodiment of the present invention, a circuit diagram showing the connection interface of the power management circuit and system of the present invention is provided.

[0026] Figure 4According to another embodiment of the present invention, a circuit diagram showing the connection interface of the power management circuit and system of the present invention is provided.

[0027] Figure 5A A schematic diagram of the main power supply unit with a single power source is shown according to an embodiment of the present invention.

[0028] Figure 5B According to another embodiment of the present invention, a schematic diagram of the main power supply unit having M power supplies is shown.

[0029] Figure 6 A schematic diagram showing the input / output power supply unit of the power management circuit and system of the present invention.

[0030] Explanation of reference numerals in the attached figures

[0031] 10, 20 M×N operational units

[0032] 12, 22 Main power supply units

[0033] 14, 24 Input / Output Power Supply Units

[0034] 142, 242 DC-DC converters, low dropout voltage regulators

[0035] 144, 244 power supplies

[0036] Connection interfaces 16 and 26

[0037] 162, 262 Unidirectional circuits that transmit data from the processor to the arithmetic unit

[0038] 164, 264 unidirectional circuits transmitting data from the arithmetic unit to the processor

[0039] 166, 266 bidirectional circuits

[0040] 18, 28 processors. Detailed Implementation

[0041] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification, and it can also be implemented or applied through other different specific embodiments.

[0042] This invention proposes a power management circuit and system, which is suitable for power management and supply of a two-dimensional accelerator chip (containing multiple computing units). The main features are that it can effectively supply power to the two-dimensional computing units and significantly reduce the number of connection interfaces connected to the two-dimensional computing units, thereby improving power supply and data transmission efficiency.

[0043] According to embodiments of the present invention, Figure 1 A schematic diagram of the power management circuit and system of the present invention is shown. (See diagram for reference.) Figure 1 As shown, the power management circuit and system of the present invention include at least M×N arithmetic units 10, a main power supply unit 12 (also called a first power supply unit), an input / output power supply unit 14 (also called a second power supply unit), N-1 connection interfaces 16, and a processor 18.

[0044] According to embodiments of the present invention, such as Figure 1 As shown, the M×N arithmetic units 10 include M columns and N rows of arithmetic units. The arrangement of the M columns and N rows is not a limitation of the present invention. M and N are both natural numbers greater than 1. The main power supply unit 12 is coupled to and supplies power to the Nth row of arithmetic units (i.e., (1,N) to (M,N) arithmetic units) in the M×N arithmetic units 10. The Nth row of arithmetic units is coupled to and supplies power to the (N-1)th row of arithmetic units (i.e., (1,N-1) to (M,N-1) arithmetic units), and so on. The second row of arithmetic units (i.e., (1,2) to (M,2) arithmetic units) is coupled to and supplies power to the first row of arithmetic units (i.e., (1,1) to (M,1) arithmetic units). The input / output power supply unit 14 is coupled to and supplies current to the M×N arithmetic units 10, and the N-1 connection interfaces 16 are respectively coupled to the corresponding arithmetic units in the first column of the M×N arithmetic units. In addition, the processor 18 is coupled to N-1 connection interfaces 16, wherein the corresponding arithmetic unit is the Nth row arithmetic unit to the second row arithmetic unit in the first column arithmetic unit (i.e. (1,N) to (1,2) arithmetic units).

[0045] like Figure 1 As shown, according to an embodiment of the present invention, the processor is coupled to N-1 connection interfaces 16 through N-1 input / output terminals of multiple input / output terminals (I / O), while the processor 18 is directly coupled to the arithmetic unit (i.e. (1,1) arithmetic unit) in the first column and first row through another input / output terminal of multiple input / output terminals.

[0046] Furthermore, according to an embodiment of the present invention, when any one of the M×N arithmetic units 10 needs to perform input / output transmission, the input / output power supply unit 14 only supplies current (approximately 50mA or less) to that arithmetic unit.

[0047] Furthermore, according to another embodiment of the present invention, one end of each arithmetic unit in the first row (i.e., (1,1) to (M,1) arithmetic units) is coupled to ground.

[0048] Figure 2This is a schematic diagram of a power management circuit and system according to another embodiment of the present invention, which is similar to the embodiment described above. Figure 2 As shown, according to another embodiment of the present invention, the power management system circuit of the present invention includes at least M×N arithmetic units 20, a main power supply unit 22 (also referred to as a first power supply unit), an input / output power supply unit 24 (also referred to as a second power supply unit), N-1 connection interfaces 26, and a processor 28.

[0049] According to another embodiment of the present invention, such as Figure 2 As shown, the M×N arithmetic units 20 include M columns of arithmetic units and N rows of arithmetic units. The arrangement of the M columns and N rows of arithmetic units is not a limitation of the present invention. M and N are both natural numbers greater than 1. The main power supply unit 22 is coupled to and supplies power to the Nth row of arithmetic units (i.e., (1,N) to (M,N) arithmetic units) in the M×N arithmetic units 20. The Nth row of arithmetic units is coupled to and supplies power to the (N-1)th row of arithmetic units (i.e., (1,N-1) to (M,N-1) arithmetic units), and so on. The second row of arithmetic units (i.e., (1,2) to (M,2) arithmetic units) is coupled to and supplies power to the first row of arithmetic units (i.e., (1,1) to (M,1) arithmetic units). The input / output power supply unit 24 is coupled to and supplies power to the M×N arithmetic units 20, and the N-1 connection interfaces 26 are respectively coupled to the corresponding arithmetic units in the first column of the M×N arithmetic units. In addition, the processor 28 is coupled to N-1 connection interfaces 26. The corresponding arithmetic unit includes the Nth row arithmetic unit to the second row arithmetic unit in the first column arithmetic unit (i.e., (1,N) to (1,2) arithmetic units).

[0050] like Figure 2 As shown, this embodiment differs from the above embodiment in that the processor 28 is coupled to the N-1 connection interfaces 26 and the arithmetic unit (i.e. (1,1) arithmetic unit) in the first column and first row through a single input / output terminal.

[0051] Furthermore, according to another embodiment of the present invention, when any one of the M×N arithmetic units 20 needs to perform input / output transmission, the input / output power supply unit 24 only supplies current (about 50mA or less) to that arithmetic unit.

[0052] Furthermore, according to another embodiment of the present invention, one end of each arithmetic unit in the first row (i.e., (1,1) to (M,1) arithmetic units) is coupled to ground.

[0053] Figure 3The circuit diagrams of various connection interfaces according to embodiments of the present invention are shown. Each connection interface 16, 26 includes two unidirectional circuits: unidirectional circuits 162 and 262 for data transmission from the processor to the arithmetic unit, and unidirectional circuits 164 and 264 for data transmission from the arithmetic unit to the processor. In one embodiment, Figure 3 The Vref value is chosen as an intermediate value based on the input voltage range as the reference input voltage. In another embodiment, Figure 3 In this context, Vx and Vy will have different voltage levels in different rows. In yet another embodiment, Figure 3 In this context, GND refers to the system ground.

[0054] Figure 4 A circuit diagram showing the connection interfaces of another embodiment of the present invention is provided. Each connection interface 16, 26 includes bidirectional circuits 166, 266 for transmission between the processor and the arithmetic unit. In one embodiment, Figure 4 The Vref value is chosen as an intermediate value based on the input voltage range as the reference input voltage. In another embodiment, Figure 4 In this context, Vx, Vy, and Vz will have different voltage levels in different rows. In yet another embodiment, Figure 4 In this context, GND refers to the system ground, while Figure 4 In this context, GNDy refers to row grounding, meaning that different rows will have different grounding standards.

[0055] like Figure 5A As shown, according to an embodiment of the present invention, the main power supply units 12 and 22 include a single power supply, and the main power supply units 12 and 22 are coupled to and powered by the single power supply to the first column to the Mth column of the Nth row of the arithmetic unit (i.e., (1,N) to (M,N) arithmetic units).

[0056] like Figure 5B As shown, according to another embodiment of the present invention, the main power supply units 12 and 22 include M power supplies, and the main power supply units 12 and 22 are respectively coupled to and supply power to the first column to the Mth column of the Nth row of the arithmetic unit (i.e., (1,N) to (M,N) arithmetic units) through the M power supplies.

[0057] Figure 6This diagram illustrates the input / output power supply units 14 and 24 (also referred to as the second power supply unit) of the power management circuit and system of the present invention. The input / output power supply units 14 and 24 are composed of N DC-to-DC converters 142 and 242 or N low-dropout regulators (LDO regulators) 142 and 242. The input / output power supply units 14 and 24 can be coupled to and supply current to the M-th column of each of the Nth row to the 1st row of arithmetic units through the N DC-to-DC converters 142 and 242 or the N LDO regulators 142 and 242, respectively. Additionally, the input / output power supply unit may also include a power supply 144 and 244, which is connected to the N DC-to-DC converters or the N LDO regulators 142 and 242.

[0058] Based on the above embodiments of the present invention, it can be seen that the power management circuit and system of the present invention can effectively solve the following problems: 1. The current of the high-power power supply unit of the prior art cannot provide the power required by multiple acceleration chips; 2. The acceleration chip of the prior art is a one-dimensional architecture, and the power transmission and data transmission of each computing unit are in the same direction. When one computing unit burns out or does not work, it will cause the power and data transmission of the entire architecture to fail; and 3. The overall architecture of the prior art requires a large number of connection interfaces, which makes the design more complex and the cost higher.

[0059] Therefore, the power management circuit and system of the present invention have the following advantages: 1. The total current required by the M column arithmetic units is less than the output current of the input / output power supply unit; 2. The total voltage required by the N row arithmetic units is less than the output voltage of the main power supply unit; 3. Data transmission can be performed between the arithmetic units in each row without any connection interface; 4. Power transmission can be performed between the arithmetic units in different rows without any connection interface; 5. This power management system requires only N-1 connection interfaces (that is, each row arithmetic unit requires only one connection interface); and 6. Since power transmission is performed vertically and data transmission is performed horizontally, the overall chip transmission performance will not be affected if any arithmetic unit is burned out or not working.

[0060] Furthermore, the power management circuit and system of the present invention are applicable to accelerated chip applications using 10-nanometer or smaller semiconductor technologies.

[0061] The above embodiments are merely illustrative of the technical principles, features, and effects of the present invention, and are not intended to limit the scope of implementation of the present invention. Any person skilled in the art can modify and alter the above embodiments without departing from the spirit and scope of the present invention. However, any equivalent modifications and alterations made using the teachings of this invention should still be covered by the claims. The scope of protection of this invention should be as set forth in the claims.

Claims

1. A power management circuit, characterized by, The application relates to a processing system, comprising: MxN operation units, wherein M and N are natural numbers greater than 1; a first power supply unit for supplying power to Nth-row operation units in the MxN operation units, wherein the Nth-row operation units supply power to (N-1)th-row operation units respectively; a second power supply unit for supplying power to the MxN operation units; and N-1 connection interfaces respectively coupled to corresponding operation units in the first column of the MxN operation units, wherein the second power supply unit comprises a power supply and N DC-DC converters or N low-dropout voltage stabilizers, the power supply being connected to the N DC-DC converters or the N low-dropout voltage stabilizers, wherein each of the N-1 connection interfaces comprises a first one-way circuit for transmitting to the corresponding operation unit and a second one-way circuit for transmitting from the corresponding operation unit, or each of the N-1 connection interfaces comprises a bidirectional circuit for transmitting to the corresponding operation unit and from the corresponding operation unit, and wherein the voltage levels of Vy in the first one-way circuit, Vx in the second one-way circuit and Vx, Vy and Vz in the bidirectional circuit are different in different rows, and Vref in the second one-way circuit and Vref in the bidirectional circuit take an intermediate value as a reference input voltage according to an input voltage range.

2. The power management circuit of claim 1, wherein, The first power supply unit comprises a single power supply for supplying power to the first column operation units to the Mth-column operation units of the Nth-row operation units through the single power supply, or the first power supply unit comprises less than or equal to M power supplies for supplying power to the first column operation units to the Mth-column operation units of the Nth-row operation units through the less than or equal to M power supplies respectively.

3. The power management circuit of claim 1, wherein, The power supply transmission is performed in a vertical direction, and the data transmission is performed in a horizontal direction.

4. The power management circuit of claim 1, wherein, The corresponding operation units comprise the Nth-row operation units to the (N+1)th-row operation units in the first column operation units.

5. The power management circuit of claim 1, wherein, When any one of the MxN operation units needs to perform input / output transmission, the second power supply unit only supplies power to the any one.

6. The power management circuit of claim 1, wherein, One end of each operation unit in the first row operation units is coupled to a ground.

7. A power management system, characterized by, The application relates to a processing system, comprising: MxN operation units, wherein M and N are natural numbers greater than 1; a first power supply unit for supplying power to Nth-row operation units in the MxN operation units, wherein the Nth-row operation units supply power to (N-1)th-row operation units respectively; a second power supply unit for supplying power to the MxN operation units; N-1 connection interfaces respectively coupled to corresponding operation units in the first column of the MxN operation units; and a processor coupled to the N-1 connection interfaces, wherein the second power supply unit comprises a power supply and N DC-DC converters or N low-dropout voltage stabilizers, the power supply being connected to the N DC-DC converters or the N low-dropout voltage stabilizers, wherein each of the N-1 connection interfaces comprises a first one-way circuit for transmitting to the corresponding operation unit and a second one-way circuit for transmitting from the corresponding operation unit, or each of the N-1 connection interfaces comprises a bidirectional circuit for transmitting to the corresponding operation unit and from the corresponding operation unit, and wherein the voltage levels of Vy in the first one-way circuit, Vx in the second one-way circuit and Vx, Vy and Vz in the bidirectional circuit are different in different rows, and Vref in the second one-way circuit and Vref in the bidirectional circuit take an intermediate value as a reference input voltage according to an input voltage range. In this circuit, Vy in the first unidirectional circuit, Vx in the second unidirectional circuit, and Vx, Vy, and Vz in the bidirectional circuit will have different voltage levels in different rows. Vref in the second unidirectional circuit and Vref in the bidirectional circuit take an intermediate value as the reference input voltage according to the input voltage range.

8. The power management system of claim 7, wherein, The processor is coupled to the N-1 connection interfaces through N-1 input / output terminals of multiple input / output terminals, and another input / output terminal of the multiple input / output terminals is directly coupled to the arithmetic unit in the first column and first row. Alternatively, the processor is coupled to the N-1 connection interfaces and the arithmetic unit in the first column and first row through a single input / output terminal.

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