A frequency discrimination circuit, a clock correction circuit, a chip, and an information processing device

Abstract

This disclosure relates to a frequency discrimination circuit, a clock correction circuit, a chip, and an information processing device. The frequency discrimination circuit includes a comparison module, a reference module, and a switched capacitor module. A first input terminal of the comparison module is electrically connected to the switched capacitor module, and a second input terminal of the comparison module is electrically connected to the reference module. The switched capacitor module outputs a voltage to be measured to the first input terminal of the comparison module based on the frequency of the signal to be corrected input to the frequency discrimination circuit. The reference module outputs a reference voltage to the second input terminal based on a preset reference frequency. The comparison module outputs a comparison result based on the voltage values ​​at the first and second input terminals. The frequency discrimination circuit provided by this disclosure simplifies the internal circuit structure of the frequency discrimination circuit, thereby reducing its manufacturing cost.

Description

Technical Field

[0001] This disclosure relates to the field of clock circuits, and more particularly to a frequency discrimination circuit, a clock correction circuit, a chip, and an information processing device. Background Technology

[0002] Existing clock circuits typically include a frequency discriminator circuit to determine the relationship between the frequency of the clock signal and the expected frequency. However, existing frequency discriminators have complex internal circuit structures and high costs, which makes them unsuitable for widespread use.

[0003] In view of this, there is an urgent need to provide a new frequency discrimination circuit to solve the problems of complex structure and high cost of existing frequency discrimination circuits. Summary of the Invention

[0004] According to one aspect of this disclosure, a frequency discrimination circuit is provided, comprising: a comparison module, a reference module, and a switched capacitor module; a first input terminal of the comparison module is electrically connected to the switched capacitor module, and a second input terminal of the comparison module is electrically connected to the reference module; the switched capacitor module is used to output a voltage to be measured to the first input terminal of the comparison module according to the frequency of the signal to be calibrated input to the frequency discrimination circuit; wherein the voltage value of the voltage to be measured is negatively correlated with the frequency of the signal to be calibrated; the reference module is used to output a reference voltage to the second input terminal according to a preset reference frequency; and the comparison module is used to output a comparison result based on the voltage values ​​of the first input terminal and the second input terminal.

[0005] In one possible implementation, the switched capacitor module includes: a first resistor unit and a switched capacitor unit electrically connected to the first resistor unit; wherein, the switched capacitor unit includes: a first switch, a second switch, and a capacitor; one end of the capacitor is electrically connected to the first resistor unit through the first switch, and the other end is grounded; one end of the second switch is electrically connected to the first resistor unit through the first switch, and the other end is grounded; wherein, the first input terminal of the comparator module is connected to the connection point between the switched capacitor unit and the first resistor unit; the first switch and the second switch are used to control the charging and discharging of the capacitor according to the signal to be calibrated; wherein, when the first switch is closed and the second switch is open, the capacitor is in a charging state; when the second switch is closed and the first switch is open, the capacitor is in a discharging state.

[0006] In one possible implementation, the capacitor is in a charging state when the signal to be calibrated is high, and in a discharging state when the signal to be calibrated is low.

[0007] In one possible implementation, the voltage to be measured is equal to the voltage drop across the equivalent resistance of the switched capacitor unit. The resistance value of the equivalent resistance of the switched capacitor unit is negatively correlated with the frequency of the signal to be corrected and positively correlated with the capacitance value of the capacitor in the switched capacitor unit.

[0008] In one possible implementation, the reference module includes: a second resistor unit and a trimming resistor unit; the second resistor unit is electrically connected to the trimming resistor unit, and the second input terminal of the comparison module is connected to the connection point of the second resistor unit and the trimming resistor unit; the trimming resistor unit is used to determine the resistance value of the trimming resistor unit according to the preset reference frequency, and output the reference voltage to the second input terminal of the comparison module; wherein the reference voltage and the resistance value of the trimming resistor unit are negatively correlated with the preset reference frequency.

[0009] In one possible implementation, the comparison module includes a first control unit, a second control unit, a comparison unit, and a switching unit. During a first preset time period of the signal to be corrected, the first input terminal of the comparison module is electrically connected to the non-inverting input terminal of the comparison unit via the first control unit, and the second input terminal of the comparison module is electrically connected to the inverting input terminal of the comparison unit via the second control unit. During a second preset time period of the signal to be corrected, the first input terminal of the comparison module is electrically connected to the inverting input terminal of the comparison unit via the first control unit, and the second input terminal of the comparison module is electrically connected to the non-inverting input terminal of the comparison unit via the second control unit. The input terminal of the switching unit is electrically connected to the output terminal of the comparison unit, and is used to generate and output a comparison result based on the comparison signal generated and output by the comparison unit during the first preset time period, and to generate and output the comparison result based on the inverted signal of the comparison signal generated and output by the comparison unit during the second preset time period.

[0010] In one possible implementation, the first preset time is the time when the comparison unit generates the odd-numbered comparison signal, and the second preset time is the time when the comparison unit generates the even-numbered comparison signal.

[0011] In one possible implementation, the frequency discrimination circuit further includes: a voltage regulator module connected at the connection point between the switched capacitor module and the first input terminal of the comparison module, for reducing voltage fluctuations at the connection point between the switched capacitor module and the first input terminal of the comparison module.

[0012] In one possible implementation, the signal to be calibrated is a clock signal.

[0013] According to another aspect of this disclosure, a clock correction circuit is also provided, the clock correction circuit including the frequency discrimination circuit described in any of the preceding claims.

[0014] In one possible implementation, the clock correction circuit further includes: a clock control circuit, the input of which is electrically connected to the output of the comparison module, the clock control circuit being used to generate and output a control value based on the comparison result; and a clock generation circuit, the control terminal of which is electrically connected to the output of the clock control circuit, and the output of which is electrically connected to the switched capacitor module, the clock generation circuit being used to determine the frequency of the signal to be corrected based on the control value, and to output the signal to be corrected to the switched capacitor module.

[0015] In one possible implementation, the clock control circuit includes: a register module, whose first input terminal is electrically connected to the output terminal of the comparison module, and whose second input terminal is electrically connected to the output terminal of the clock generating circuit; the register module is used to digitize the comparison result output by the comparison module according to the signal to be corrected, and output the digitized comparison result; and a digital integration module, whose input terminal is electrically connected to the output terminal of the register module, and whose output terminal is electrically connected to the control terminal of the clock generating circuit; the digital integration module is used to generate an accumulated value according to each digitized comparison result, and generate a control value corresponding to the sum of the accumulated values ​​if the absolute value of the sum of the accumulated values ​​is greater than a preset threshold.

[0016] In one possible implementation, the clock generation circuit includes: a clock generation module, the control terminal of which is electrically connected to the output terminal of the digital integration module, the clock generation module being used to determine the frequency of the reference clock signal according to the control value and output the reference clock signal; and a frequency divider module, the input terminal of which is electrically connected to the output terminal of the clock generation module and the output terminal of which is electrically connected to the switched capacitor module, the frequency divider module being used to output the signal to be corrected according to a preset divisor and the reference clock signal.

[0017] In one possible implementation, the clock correction circuit further includes a relationship determination module and a signal control module; wherein the relationship determination module is electrically connected to the signal control module; the relationship determination module is used to determine a numerical correspondence based on the change in the control value output by the digital integration module when the signal to be corrected has been corrected and the preset divisor of the frequency divider has changed; wherein the numerical correspondence is the correspondence between the change in the preset divisor and the change in the control value; the signal control module is used to determine the current control value output by the digital integration module based on the numerical correspondence and the current preset divisor of the frequency divider.

[0018] According to another aspect of this disclosure, a chip is also provided, the chip comprising: the clock correction circuit described in any of the preceding claims.

[0019] According to another aspect of this disclosure, an information processing apparatus is also provided, the information processing apparatus comprising: the chip described above.

[0020] In one possible implementation, the information processing device is applied to at least one electronic device from the group consisting of smartphones, smart TVs, smartwatches, smart bracelets, tablets, desktop computers, industrial computers, laptops, all-in-one computers, access control devices, wireless network equipment, and wireless computer peripherals.

[0021] The frequency discrimination circuit provided in this disclosure can determine the relationship between the voltage value of the voltage to be measured and the voltage value of the reference voltage, and thus determine the relationship between the preset reference frequency and the frequency of the signal to be calibrated, thereby achieving frequency discrimination of the signal to be calibrated. Since the circuit structure of the switched capacitor module that converts the signal to be calibrated into the voltage to be measured is simple and does not require complex electrical components, the internal circuit structure of the frequency discrimination circuit can be simplified, thereby reducing the manufacturing cost of the frequency discrimination circuit.

[0022] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0024] Figure 1 This is a schematic diagram of the frequency discrimination circuit provided in an embodiment of the present disclosure.

[0025] Figure 2 This is a schematic diagram of the frequency discrimination circuit provided in an embodiment of the present disclosure.

[0026] Figure 3 This is a schematic diagram of the structure of a switched capacitor module provided in an embodiment of this disclosure.

[0027] Figure 4 A schematic diagram of the structure of a reference module provided in an embodiment of this disclosure.

[0028] Figure 5 This is a schematic diagram of the clock correction circuit provided in an embodiment of the present disclosure.

[0029] Figure 6 This is a schematic diagram of the clock correction circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0030] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0031] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0032] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0033] See Figure 1 As shown, this disclosure provides a frequency discrimination circuit 1, which includes a comparison module 11, a switched capacitor module 12, and a reference module 13. The first input terminal of the comparison module 11 is electrically connected to the switched capacitor module 12, and the second input terminal of the comparison module 11 is electrically connected to the reference module 13.

[0034] For example, the switched capacitor module 12 is used to output a voltage to be measured to the first input terminal of the comparison module 11 according to the frequency of the signal to be calibrated input to the frequency discriminator circuit 1. The voltage value of the voltage to be measured is negatively correlated with the frequency of the signal to be calibrated. In other words, by adjusting the frequency of the signal to be calibrated input to the frequency discriminator circuit 1, the voltage value of the voltage to be measured can be adjusted; that is, increasing the frequency of the signal to be calibrated can decrease the voltage value of the voltage to be measured, and decreasing the frequency of the signal to be calibrated can increase the voltage value of the voltage to be measured.

[0035] For example, the signal to be corrected input to the frequency discrimination circuit 1 can be a clock signal, which can be generated by the clock generation circuit 2 described below and output to the switched capacitor module 12 of the frequency discrimination circuit 1 (see below). Figure 5 as well as Figure 6 The clock generating circuit shown is 2).

[0036] For example, the reference module 13 is used to output a reference voltage to the second input terminal according to a preset reference frequency. Optionally, the preset reference frequency can be determined according to actual conditions, and this disclosure does not limit it.

[0037] For example, the reference voltage output by the reference module 13 is negatively correlated with the preset reference frequency. In other words, the higher the preset reference frequency, the lower the reference voltage value, and vice versa.

[0038] For example, the reference voltage value is equal to the voltage value of the voltage to be measured when the frequency of the signal to be calibrated is a preset reference frequency. For instance, if the preset reference frequency is 100MHz and the frequency of the signal to be calibrated is also 100MHz, the voltage value of the voltage to be measured output by the switched capacitor module 12 is equal to 5V. Therefore, the voltage value of the reference voltage corresponding to the preset reference frequency is 5V.

[0039] For example, the comparison module 11 is used to output a comparison result based on the voltage value at the first input terminal and the voltage value at the second input terminal. In other words, the comparison result is a signal output by the comparison module 11 based on the magnitude relationship between the voltage value of the voltage to be measured at the first input terminal and the voltage value of the reference voltage at the second input terminal.

[0040] For example, since the reference voltage is equal to the voltage of the voltage under test when the frequency of the signal to be calibrated is a preset reference frequency, the correspondence between the reference voltage and frequency is consistent with the correspondence between the voltage of the voltage under test and frequency. In other words, when the preset reference frequency is equal to the frequency of the signal to be calibrated, the reference voltage is equal to the voltage of the voltage under test. Because the voltage of the voltage under test is negatively correlated with the frequency of the signal to be calibrated, and the voltage of the reference voltage is also negatively correlated with the preset reference frequency, if the comparison result indicates that the voltage of the voltage under test is greater than the voltage of the reference voltage, then the preset reference frequency is greater than the frequency of the signal to be calibrated. Conversely, if the comparison result indicates that the voltage of the voltage under test is less than the voltage of the reference voltage, then the preset reference frequency is less than the frequency of the signal to be calibrated.

[0041] The frequency discrimination circuit provided in this disclosure can determine the relationship between the voltage value of the voltage to be measured and the voltage value of the reference voltage, and thus determine the relationship between the preset reference frequency and the frequency of the signal to be calibrated, thereby achieving frequency discrimination of the signal to be calibrated. Since the circuit structure of the switched capacitor module that converts the signal to be calibrated into the voltage to be measured is simple and does not require complex electrical components, the internal circuit structure of the frequency discrimination circuit can be simplified, thereby reducing the manufacturing cost of the frequency discrimination circuit.

[0042] In one possible implementation, see [reference] Figure 2 As shown, the frequency discrimination circuit 1 also includes a voltage regulator module 14.

[0043] For example, the voltage regulator module 14 is connected at the connection point between the switched capacitor module 12 and the first input terminal of the comparator module 11, and is used to reduce the voltage fluctuation at the connection point between the switched capacitor module 12 and the first input terminal of the comparator module 11.

[0044] Optionally, the voltage regulator module 14 can be implemented using a voltage regulator capacitor (e.g., Figure 6As shown, one end of the voltage-regulating capacitor is connected to the connection point between the switched capacitor module 12 and the first input terminal of the comparator module 11, and the other end of the voltage-regulating capacitor is grounded. The internal structure of the voltage-regulating module 14 provided in this disclosure is not limited to the voltage-regulating capacitor mentioned above, and it can also be implemented through other related technologies, which this disclosure does not limit.

[0045] Optionally, to further reduce the voltage fluctuation at the connection point between the switched capacitor module 12 and the first input terminal of the comparator module 11, in addition to adding a voltage regulator module 14, the voltage fluctuation at the connection point between the switched capacitor module 12 and the first input terminal of the comparator module 11 can also be reduced by controlling the charging and discharging rate of the capacitor in the switched capacitor module 12. This can be achieved through related technologies, which will not be elaborated here.

[0046] The frequency discrimination circuit provided in this disclosure reduces voltage fluctuations at the connection between the switched capacitor module and the first input terminal of the comparison module by setting a voltage regulator module. This reduces the voltage value at the first input terminal of the comparison module to a relatively stable state, thereby reducing the impact of voltage fluctuations on the comparison result output by the comparison module, improving the accuracy of the comparison result output by the comparison module, and enhancing the reliability of the frequency discrimination circuit.

[0047] In one possible implementation, see [reference] Figure 3 As shown, the switched capacitor module 12 includes: a first resistor unit 121 and a switched capacitor unit 122 electrically connected to the first resistor unit 121. The switched capacitor unit 122 includes: a first switch 1221, a second switch 1222, and a capacitor 1223.

[0048] For example, one end of capacitor 1223 is electrically connected to first resistor unit 121 via first switch 1221, and the other end is grounded. One end of second switch 1222 is electrically connected to first resistor unit 121 via first switch 1221, and the other end is grounded. The first input terminal of comparison module 11 is connected at the junction of switched capacitor unit 122 and first resistor unit 121.

[0049] For example, the first switch 1221 and the second switch 1222 are used to control the charging and discharging of the capacitor 1223 according to the signal to be calibrated. Specifically, when the first switch 1221 is closed and the second switch 1222 is open, the capacitor 1223 is in a charging state. When the second switch 1222 is closed and the first switch 1221 is open, the capacitor 1223 is in a discharging state.

[0050] Exemplarily, the charging and discharging of the capacitor 1223 (i.e., the on and off states of the first switch 1221 and the second switch 1222) are controlled by the high and low levels of the signal to be corrected. For example, when the signal to be corrected is at a high level, the capacitor 1223 is in a charging state, that is, the first switch 1221 is closed and the second switch 1222 is open. When the signal to be corrected is at a low level, the capacitor 1223 is in a discharging state, that is, the first switch 1221 is open and the second switch 1222 is closed.

[0051] In a possible implementation, the voltage to be measured is equal to the voltage drop across the equivalent resistance of the switched-capacitor unit 122. The resistance value of the equivalent resistance of the switched-capacitor unit 122 is negatively correlated with the frequency of the signal to be corrected and positively correlated with the capacitance value of the capacitor 1223 in the switched-capacitor unit 122. Optionally, the equivalent resistance of the switched-capacitor unit 122 is equal to the product of the reciprocal of the frequency of the signal to be corrected and the capacitance value of the capacitor 1223.

[0052] Optionally, each period of the signal to be corrected corresponds to an equivalent resistance of the switched-capacitor unit 122. For example, if the frequency corresponding to the first period of the signal to be corrected is N1, the resistance value of the equivalent resistance of the switched-capacitor unit 122 corresponding to this period is R1 (i.e., the product of the capacitance value of the capacitor 1223 and 1 / N1). If the frequency corresponding to the second period of the signal to be corrected is N2, the resistance value of the equivalent resistance of the switched-capacitor unit 122 corresponding to this period is R2 (i.e., the product of the capacitance value of the capacitor 1223 and 1 / N2). If the frequency corresponding to the first period of the signal to be corrected is equal to the frequency corresponding to the second period (i.e., N1 = N2), the resistance value of the equivalent resistance of the switched-capacitor unit 122 remains unchanged (i.e., R1 = R2). If the frequency corresponding to the first period of the signal to be corrected is greater than the frequency corresponding to the second period (i.e., N1 > N2), the resistance value of the equivalent resistance of the switched-capacitor unit 122 decreases (i.e., R1 < R2). If the frequency corresponding to the first period of the signal to be corrected is less than the frequency corresponding to the second period (i.e., N1 < N2), the resistance value of the equivalent resistance of the switched-capacitor unit 122 increases (i.e., R1 > R2).

[0053] In a possible implementation, referring to Figure 4 as shown, the reference module 13 includes: a second resistor unit 131 and a trimming resistor unit 132.

[0054] Exemplarily, the second resistor unit 131 is electrically connected to the trimming resistor unit 132, and the second input terminal of the comparison module 11 is connected to the connection point between the second resistor unit 131 and the trimming resistor unit 132.

[0055] For example, the adjusting resistor unit 132 is used to determine the resistance value of the adjusting resistor unit 132 according to a preset reference frequency, and output a reference voltage to the second input terminal of the comparison module 11. The reference voltage and the resistance value of the adjusting resistor unit 132 are negatively correlated with the preset reference frequency.

[0056] For example, the reference voltage is equal to the voltage drop across the adjustment resistor unit 132. When the preset reference frequency is high, the resistance of the adjustment resistor unit 132 is smaller, and the reference voltage output by the reference module 13 is also smaller. When the preset reference frequency is low, the resistance of the adjustment resistor unit 132 is larger, and the reference voltage output by the reference module 13 is also larger. For example, if the preset reference frequency is 200MHz, the resistance of the adjustment resistor unit 132 is R3, and the reference voltage output by the reference module 13 is U1. Then, when the preset reference frequency is 100MHz, the resistance of the adjustment resistor unit 132 is R4, and the reference voltage output by the reference module 13 is U2. Where R3 is less than R4, and U1 is less than U2.

[0057] In one possible implementation, when the signal to be calibrated in the input frequency discriminator circuit 1 has been calibrated, the average frequency of the signal to be calibrated over several adjacent cycles is approximately a preset reference frequency. For example, if the preset reference frequency is 100MHz, then when the signal to be calibrated in the input frequency discriminator circuit 1 has been calibrated, the frequency of the first cycle of the signal to be calibrated is 102MHz, the frequency of the second cycle is 98MHz, the frequency of the third cycle is 97MHz, and the frequency of the fourth cycle is 103MHz.

[0058] To ensure the frequency of the signal to be calibrated is accurately reflected by the difference between the voltage value of the voltage to be measured and the voltage value of the reference voltage, the resistance value of the first resistor unit 121 in the switched capacitor module 12 and the resistance value of the second resistor unit 131 in the reference module 13 can be set to the same value. Furthermore, the voltage value at the input terminal of the first resistor unit 121 (i.e., the end furthest from the switched capacitor unit 122) is equal to the voltage value at the input terminal of the second resistor unit 131 (i.e., the end furthest from the adjustment resistor unit 132). For example, if the resistance value of the first resistor unit 121 is 10Ω and the voltage value at its input terminal is 10V, the resistance value of the second resistor unit 131 is also 10Ω, and its input voltage value is also 10V.

[0059] The frequency discrimination circuit provided in this disclosure, when the preset reference frequency is changed, correspondingly changes the resistance value of the adjustment resistor unit, enabling the comparison module to compare the speed relationship between the new preset reference frequency and the frequency of the signal to be calibrated. This makes the frequency discrimination circuit suitable for identifying the speed relationship between the frequency of the signal to be calibrated and different preset reference frequencies. Furthermore, when the preset reference frequency changes, the frequency discrimination circuit provided in this disclosure only needs to adjust the resistance value of the adjustment resistor unit accordingly, without complex circuit changes, to identify the speed relationship between the new reference frequency and the frequency of the signal to be calibrated.

[0060] In one possible implementation, see [reference] Figure 6 As shown, the comparison module 11 includes a first control unit 111, a second control unit 112, a comparison unit 113, and a switching unit 114.

[0061] For example, during a first preset time period of the signal to be corrected, the first input terminal of the comparison module 11 is electrically connected to the non-inverting input terminal of the comparison unit 113 through the first control unit 111, and the second input terminal of the comparison module 11 is electrically connected to the inverting input terminal of the comparison unit 113 through the second control unit 112. During a second preset time period of the signal to be corrected, the first input terminal of the comparison module 11 is electrically connected to the inverting input terminal of the comparison unit 113 through the first control unit 111, and the second input terminal of the comparison module 11 is electrically connected to the non-inverting input terminal of the comparison unit 113 through the second control unit 112.

[0062] For example, the input terminal of the switching unit 114 is electrically connected to the output terminal of the comparison unit 113, and is used to generate and output a comparison result based on the comparison signal generated and output by the comparison unit 113 within a first preset time, and to generate and output a comparison result based on the inverted signal of the comparison signal generated and output by the comparison unit 113 within a second preset time.

[0063] For example, the time when the comparison unit 113 generates the odd-numbered comparison signal can be considered as the first preset time, and the time when the comparison unit 113 generates the even-numbered comparison signal can be considered as the second preset time. For instance, within the first cycle of the signal to be corrected, during the time when the comparison unit 113 generates the first comparison signal (i.e., the odd-numbered comparison signal), the first input terminal of the comparison module 11 is electrically connected to the non-inverting input terminal of the comparison unit 113 through the first control unit 111, and the second input terminal of the comparison module 11 is electrically connected to the inverting input terminal of the comparison unit 113 through the second control unit 112. During the time when the comparison unit 113 generates the second comparison signal (i.e., the even-numbered comparison signal), the first input terminal of the comparison module 11 is electrically connected to the inverting input terminal of the comparison unit 113 through the first control unit 111, and the second input terminal of the comparison module 11 is electrically connected to the non-inverting input terminal of the comparison unit 113 through the second control unit 112, and so on. In other words, for each comparison signal output by the comparison unit 113, the input voltage of the non-inverting input terminal and the inverting input terminal of the comparison unit 113 needs to be switched once through the first control unit 111 and the second control unit 112.

[0064] For example, within a first preset time period, if the comparison signal output by the comparison unit 113 is "high level", then the comparison result output by the switching unit 114 based on the comparison signal is also "high level". Conversely, if the comparison signal output by the comparison unit 113 is "low level", then the comparison result output by the switching unit 114 based on the comparison signal is also "low level". Within a second preset time period, if the comparison signal output by the comparison unit 113 is "high level", then the comparison result output by the switching unit 114 based on the comparison signal is "low level". Conversely, if the comparison signal output by the comparison unit 113 is "low level", then the comparison result output by the switching unit 114 based on the comparison signal is "high level".

[0065] For example, ideally, when the voltage at the non-inverting input of comparator 113 is greater than the voltage at its inverting input, comparator 113 outputs a high level; conversely, when the voltage at the non-inverting input is less than the voltage at its inverting input, comparator 113 outputs a low level. However, in a non-ideal situation, the voltage at the non-inverting input of comparator 113 needs to be greater than the offset value to output a high level. The magnitude of the offset value is determined by the precision of comparator 113; a higher precision results in a smaller offset value, and a lower precision results in a larger offset value. In other words, when a low-precision comparator outputs a high level, the difference between the voltage at its non-inverting and inverting inputs should be greater than the difference between the voltage at the non-inverting and inverting inputs when a high-precision comparator outputs a high level. The first control unit 111 and the second control unit 112 provided in this disclosure can compensate for the difference between low-precision comparators and high-precision comparators.

[0066] For example, taking the first preset time as the time for comparison unit 113 to generate the odd-numbered comparison signal and the second preset time as the time for comparison unit 113 to generate the even-numbered comparison signal, and assuming the voltage value of the voltage to be measured is greater than the voltage value of the reference voltage, since comparison unit 113 is a low-precision comparison unit (i.e., its bias value is large), under normal conditions (i.e., the circuit does not include the first control unit 111 and the second control unit 112), even if the initial voltage to be measured is higher than the reference voltage, the comparison signal is still low due to the high bias value. Therefore, the first three comparison signals output by comparison unit 113 based on the signal to be calibrated in one cycle are all "low level" before it can output "high level". For example, within one cycle of the signal to be calibrated, the comparison signals output by comparison unit 113 are "low level", "low level", "low level", "high level", "high level". If the output terminal of comparison unit 113 is connected to the clock control circuit 3 described below, the clock control circuit 3 may easily consider that the frequency of the signal to be calibrated at this time is greater than the preset reference frequency, thereby accumulating incorrect values. Through the first control unit 111 and the second control unit 112, when the comparison unit 113 generates the first comparison signal, the voltage at its non-inverting input terminal is the voltage to be measured, and the voltage at its inverting input terminal is the reference voltage, outputting a "low level" comparison signal. When the comparison unit 113 generates the second comparison signal, the voltage at its inverting input terminal is the voltage to be measured, and the voltage at its non-inverting input terminal is the reference voltage, also outputting a "low level" comparison signal, and so on. The comparison signals output by the comparison unit 113 according to the signal to be corrected in one cycle are "low level", "low level", "low level", "low level", and "high level" in sequence. The comparison result output by the switching unit 114 according to the above comparison signals is "low level", "high level", "low level", "high level", and "high level". If the output terminal of the switching unit 114 is connected to the clock control circuit 3 described below, the clock control circuit 3 can consider that the frequency of the signal to be corrected at this time is less than the preset reference frequency, thereby correctly controlling the clock generating circuit 2 to adjust the frequency of the signal to be corrected, and thus compensating for the difference between the high-precision comparison unit and the low-precision comparison unit.

[0067] For example, the first preset time can be an odd-numbered period of the signal to be corrected, and the second preset time can be an even-numbered period of the signal to be corrected. Optionally, the first preset time can be the first three periods of the signal to be corrected, and the second preset time can be the fourth to sixth periods of the signal to be corrected, so that the comparison results corresponding to the first six periods of the signal to be corrected can compensate for each other. Optionally, the first preset time can also be the time when the comparison unit 113 generates the first m comparison signals within one period of the signal to be corrected, and the second preset time can be the time when the comparison unit 113 generates the last n comparison signals within one period of the signal to be corrected, where m and n are positive integers, and the sum of m and n is equal to the total number of comparison signals generated by the comparison unit 113 within one period of the signal to be corrected. Alternatively, the second preset time can be the time when the comparison unit 113 generates the first m comparison results within one period of the signal to be corrected, and the first preset time can be the time when the comparison unit 113 generates the last n comparison results within one period of the signal to be corrected. This disclosure does not limit the first preset time and the second preset time.

[0068] For example, the faster the switching frequency of the first control unit 111 and the second control unit 112, the more accurate the comparison result output by the comparison module 11.

[0069] For example, as described below, the comparison module 11 can output the comparison result to the clock control circuit 3 to control the frequency of the signal to be corrected generated by the clock generation circuit 2. Then, by switching the voltage values ​​of the two input terminals of the comparison unit 113 through the first control unit 111 and the second control unit 112, the control value generated by the clock control circuit 3 based on the comparison result output by the low-precision comparison unit 113 is essentially equivalent to the control value generated based on the comparison result output by the high-precision comparison unit 113. In other words, the first control unit 111 and the second control unit 112 can minimize the influence of the bias value on the low-precision comparison unit, making the low-precision comparison unit equivalent to the high-precision comparison unit.

[0070] Optionally, if the comparison unit 113 in the comparison module 11 is a high-precision comparison unit, or if the structure of the frequency discrimination circuit 1 is further simplified and the manufacturing cost of the frequency discrimination circuit 1 is reduced, the first control unit 111, the second control unit 112 and the switching unit 114 may not be provided. In this case, the comparison result output by the comparison module 11 is the comparison signal output by the comparison unit 113.

[0071] As can be seen from the above, the frequency discrimination circuit provided in this disclosure can compensate for the difference between the comparison results output by the low-precision comparison unit and the high-precision comparison unit at the first preset time and the second preset time by switching the voltage values ​​of the two input terminals of the comparison unit through the first control unit and the second control unit, thereby reducing the accuracy requirements of the frequency discrimination circuit for the comparison unit.

[0072] According to another aspect of this disclosure, a clock correction circuit 100 is also provided, see reference. Figure 5 as well as Figure 6 As shown, the clock correction circuit 100 includes the frequency discrimination circuit 1 described above.

[0073] In one possible implementation, see [reference] Figure 5 As shown, the clock correction circuit 100 also includes a clock generation circuit 2 and a clock control circuit 3.

[0074] For example, the input terminal of the clock control circuit 3 is electrically connected to the output terminal of the comparison module 11. The clock control circuit 3 is used to generate and output a control value based on the comparison result.

[0075] For example, the control terminal of the clock generating circuit 2 is electrically connected to the output terminal of the clock control circuit 3, and its output terminal is electrically connected to the switched capacitor module 12. The clock generating circuit 2 is used to determine the frequency of the signal to be corrected according to the control value, and output the signal to be corrected to the switched capacitor module 12.

[0076] For example, when the clock generating circuit 2 outputs a signal to be calibrated to the switched capacitor module 12, the switched capacitor module 12 outputs a voltage to be measured to the first input terminal of the comparison module 11. The comparison module 11 generates a comparison result by comparing the voltage value at the first input terminal (i.e., the voltage value of the voltage to be measured) with the voltage value at the second input terminal (i.e., the voltage value of the reference voltage), and outputs the comparison result to the clock control circuit 3. The clock control circuit 3 outputs a control value to the clock generating circuit 2 based on multiple comparison results (the specific number is determined according to the preset threshold below) to control the frequency at which the clock generating circuit 2 generates the signal to be calibrated.

[0077] For example, as described in the frequency discrimination circuit 1 above, changing the preset reference frequency, i.e., changing the resistance value of the adjustment resistor unit 132 in the frequency discrimination circuit 1, can change the comparison result output by the comparison module 11. Since the clock control circuit 3 adjusts the frequency of the signal to be calibrated generated by the clock generation circuit 2 to the preset reference frequency based on the comparison result, changing the resistance value of the adjustment resistor unit 132 at a certain moment can change the frequency of the signal to be calibrated generated by the clock generation circuit 2 at the next moment, thereby achieving modulation of the frequency of the signal to be calibrated, such as spread spectrum.

[0078] Compared to existing crystal oscillators that rely on an external crystal for their local oscillator frequency, the clock correction circuit provided in this disclosure can control the frequency of the signal to be corrected generated by the clock generator circuit through the comparison result output by the frequency discriminator circuit, thereby correcting the frequency of the signal to be corrected and generating a high-precision signal. Furthermore, the clock correction circuit provided in this disclosure can correct the signal to be corrected to other frequencies by changing the resistance value of the adjustment resistor unit, without the need for additional PLL (Phase Locked Loop) circuits. Therefore, the clock correction circuit provided in this disclosure simplifies the circuit structure of existing clock circuits and reduces their manufacturing costs. In addition, except for the analog comparison module, all other modules and circuits in the clock correction circuit provided in this disclosure can be implemented using core devices, which facilitates the integration of the clock correction circuit.

[0079] Furthermore, compared to the integrated oscillators in the prior art that generate signals with lower frequencies, the clock correction circuit provided in this disclosure can be applied to chips with large signal frequency variation requirements, such as those ranging from tens or hundreds of MHz to GHz.

[0080] In one possible implementation, see [reference] Figure 6 As shown, the clock control circuit 3 includes a register module 31 and a digital integration module 32.

[0081] For example, the first input terminal of the register module 31 is electrically connected to the output terminal of the comparison module 11, and its second input terminal is electrically connected to the output terminal of the clock generator circuit 2. The register module 31 is used to digitize the comparison result output by the comparison module 11 according to the signal to be corrected, and output the digitized comparison result.

[0082] Optionally, when the comparison result output by the comparison module 11 is high, the comparison result digitized by the register module 31 is binary "1", and when the comparison result output by the comparison module 11 is low, the comparison result digitized by the register module 31 is binary "0".

[0083] The input terminal of the digital integration module 32 is electrically connected to the output terminal of the register module 31, and its output terminal is electrically connected to the control terminal of the clock generation circuit 2. The digital integration module 32 is used to generate an accumulated value based on the digitized comparison result, and generate a control value corresponding to the sum of the accumulated values ​​if the absolute value of the sum of the accumulated values ​​is greater than a preset threshold.

[0084] For example, if the first digitized comparison result output by register module 31 is binary "1", then digital integration module 32 generates an accumulated value "1", and the absolute value of the accumulated sum corresponding to digital integration module 32 is |Z+1| (Z is the initial value of digital integration module 32). If the first digitized comparison result output by register module 31 is binary "0", then digital integration module 32 generates an accumulated value "-1", and the absolute value of the accumulated sum corresponding to digital integration module 32 is |Z-1|. Taking the comparison result where a high level indicates that the voltage value of the voltage to be measured is greater than the voltage value of the reference voltage, and a low level indicates that the voltage value of the voltage to be measured is less than the voltage value of the reference voltage, as an example, when the voltage value of the voltage to be measured is greater than the voltage value of the reference voltage, the comparison result output by comparison module 11 is high level, register module 31 stores the comparison result as binary "1", and outputs binary data "1" to digital integration module 32. At this time, digital integration module 32 generates an accumulated value "1". When the voltage value of the voltage to be measured is less than the voltage value of the reference voltage, the comparison result output by the comparison module 11 is low level, the register module 31 stores the comparison result as binary "0" and outputs binary data "0" to the digital integration module 32. At this time, the digital integration module 32 generates an accumulated value "-1".

[0085] For example, the initial value Z in the clock control circuit 3, that is, the initial value Z in the digital integration module 32, can be 0, or a fixed value set according to the actual situation, or a specific value obtained by simulating the clock correction circuit 3 under ideal conditions through relevant technologies.

[0086] For example, if the comparison module 11 generates 5 comparison results within one cycle of the signal to be calibrated, and the non-inverting input of the comparison unit 113 is the voltage to be measured and its inverting input is the reference voltage within a first preset time, and the inverting input of the comparison unit 113 is the voltage to be measured and its non-inverting input is the reference voltage within a second preset time, then, in the case where the first preset time is the time when the comparison unit 113 generates the odd-numbered comparison signal and the second preset time is the time when the comparison unit 113 generates the even-numbered comparison signal, within one cycle of the signal to be calibrated, the comparison results input to the register module 31 are "low level", "high level", "low level", "high level" and "high level", and the binary values ​​stored in the register module 31 are "0", "1", "0", "1" and "1". At this time, the accumulated value generated by the digital integration module 32 is 1, and the absolute value of the sum of the accumulated values ​​generated by the digital integration module 32 is |Z+1|. The process of accumulating values ​​in the digital integration module 32 is as described above. Only when the absolute value of the sum of the accumulated values ​​equals a preset threshold can a control value be output to control the clock generation circuit 2 to adjust the frequency of the signal to be corrected. For example, if the preset threshold is 1024, then a control value can only be output when the sum of the accumulated values ​​in the digital integration module 32 equals 1024, thus increasing the frequency of the signal to be corrected generated by the clock generation circuit 2. Conversely, a control value can only be output when the accumulated value in the digital integration module 32 equals -1024, thus decreasing the frequency of the signal to be corrected generated by the clock generation circuit 2.

[0087] For example, the aforementioned preset threshold can be determined by the control bit corresponding to the clock generating circuit 2. For instance, if the control bit corresponding to the clock generating circuit 2 is 8 bits, then the control value output by the digital integration module 32 is <7:0>, meaning the range of the control value (i.e., the preset threshold) is 0 to 255. It is worth noting that the number of bits in the digital integration module 32 provided in this disclosure is not necessarily consistent with the number of bits in the control bit corresponding to the clock generating circuit 2. That is, if the control bit corresponding to the clock generating circuit 2 is 8 bits, the digital integration module 32 can be an 8-bit digital integration module or a digital integration module with more than 8 bits, such as 16 bits. However, in this case, the control value output by the digital integration module 32 is only the first 8 bits of the digital integration module 32, i.e., <16:10>.

[0088] For example, when the signal to be calibrated is calibrated, the number of "1" and "0" input to the digital integration module 32 is almost equal within a certain period of time. That is, the number of accumulated values ​​"1" and accumulated values ​​"-1" generated by the digital integration module 32 is basically equal. At this time, the absolute value of the sum of accumulated values ​​generated by the digital integration module 32 is basically 0, and the digital integration module 32 remains in a state of not outputting control values.

[0089] In one possible implementation, see [reference] Figure 6 As shown, the clock generation circuit 2 includes a clock generation module 21 and a frequency divider module 22.

[0090] For example, the control terminal of the clock generation module 21 is electrically connected to the output terminal of the digital integration module 32. The clock generation module 21 is used to determine the frequency of the reference clock signal according to the control value and output the reference clock signal.

[0091] For example, the input terminal of the frequency divider module 22 is electrically connected to the output terminal of the clock generation module 21, and its output terminal is electrically connected to the switched capacitor module 12. The frequency divider module 22 is used to output a signal to be corrected based on a preset divisor and a reference clock signal.

[0092] For example, the frequency of the reference clock signal corresponding to the calibrated signal is equal to the reciprocal of the product of the resistance value of the adjustment resistor unit 132 and the capacitance value of the capacitor 1223, multiplied by a preset divisor. In other words, if the resistance value of the adjustment resistor unit 132 is R... x The capacitance of capacitor 1223 is C. x The default divisor is N. x Then the frequency of the reference clock signal is equal to N. x *1 / (R x *C x ).

[0093] For example, see [link / reference] Figure 6 As shown. When MOS switch 212 is closed, MOS switch 212 transmits the voltage at the output terminal of the third resistor unit 211 to each inverter (i.e., inverters 213 to 215) to drive each inverter to work. At this time, the input terminal A of the first inverter 213 is at a low level, the output terminal B of the first inverter 213 (i.e., the input terminal of the second inverter 214) is at a high level, the output terminal C of the second inverter 214 (i.e., the input terminal of the third inverter 215) is at a low level, the output terminal D of the third inverter 215 (i.e., the input terminal of the fourth inverter 216) is at a high level, and the output of the fourth inverter 216 is at a low level, that is, point E is at a low level. At this time, the input terminal A of the first inverter 213 is electrically connected to the output terminal D of the third inverter 215. Therefore, when the third inverter 215 outputs a high level, the input terminal A of the first inverter 213 is also at a high level, and the output terminal B of the first inverter 213 (i.e., the input terminal of the second inverter 214) is at a low level. By analogy, the fourth inverter 216 outputs a high level (i.e., point E is at a high level), thus forming a signal for one cycle of the reference clock signal.

[0094] For example, if the frequency of the reference clock signal output by the clock generation module 21 is 200MHz and the preset divisor of the frequency division module 22 is 2, then the frequency of the output signal to be corrected is 100MHz.

[0095] In one possible implementation, the clock correction circuit 100 further includes a relationship determination module and a signal control module. The relationship determination module and the signal control module are electrically connected.

[0096] For example, the relationship determination module is used to determine the numerical correspondence based on the change in the control value output by the digital integration module 32 when the signal to be corrected has been corrected and the preset divisor of the frequency divider module 22 has changed. The numerical correspondence is the correspondence between the change in the preset divisor and the change in the control value.

[0097] For example, the signal control module is used to determine the control value currently output by the digital integrator module 32 based on the numerical correspondence and the current preset divisor of the frequency divider module 22.

[0098] For example, when the signal to be calibrated is calibrated (as described above), if the preset divisor of the frequency divider module 22 changes from 10 to 11, the relationship determination module determines the change in the control value output by the digital integrator module 32. If the control value output by the digital integrator module 32 changes from 100 to 110, the relationship determination module can determine that for every 1 change in the divisor of the frequency divider module 22, the control value output by the digital integrator module 32 changes by 10%. The signal control module can determine the current control value output by the digital integrator module 32, i.e., 120, based on the numerical correspondence obtained by the relationship determination module and the current preset divisor of the frequency divider module 22. For example, if the current preset divisor is 12, the signal control module can determine the current control value output by the digital integrator module 32.

[0099] The clock correction circuit provided in this disclosure can determine the control value corresponding to each preset divisor through the relationship determination module and the signal control module. Then, when the preset divisor corresponding to the frequency division module 22 changes, the control value of the digital integration module can be adjusted accordingly, thereby enabling more accurate modulation of the frequency of the signal to be corrected.

[0100] According to another aspect of this disclosure, a chip is also provided that includes the clock correction circuit described above.

[0101] According to another aspect of this disclosure, an information processing apparatus is also provided, the information processing apparatus comprising: the chip described above.

[0102] In one possible implementation, the information processing device is applied to at least one electronic device from the group consisting of smartphones, smart TVs, smartwatches, smart bracelets, tablets, desktop computers, industrial computers, laptops, all-in-one computers, access control devices, wireless network equipment, and wireless computer peripherals.

[0103] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A frequency discrimination circuit, characterized in that, The frequency discrimination circuit includes: a comparison module, a reference module, and a switched capacitor module; The first input terminal of the comparison module is electrically connected to the switched capacitor module, and the second input terminal of the comparison module is electrically connected to the reference module. The switched capacitor module is used to output a voltage to be measured to the first input terminal of the comparison module according to the frequency of the signal to be calibrated input to the frequency discrimination circuit; wherein the voltage value of the voltage to be measured is negatively correlated with the frequency of the signal to be calibrated; The reference module is used to output a reference voltage to the second input terminal according to a preset reference frequency; The comparison module is used to output a comparison result based on the voltage value of the first input terminal and the voltage value of the second input terminal. The comparison result is used as the basis for adjusting the frequency of the signal to be corrected. The reference module includes: a second resistor unit and a trimming resistor unit; The second resistor unit is electrically connected to the adjustment resistor unit, and the second input terminal of the comparison module is connected to the connection point between the second resistor unit and the adjustment resistor unit; The adjustment resistor unit is used to determine the resistance value of the adjustment resistor unit according to the preset reference frequency, and output the reference voltage to the second input terminal of the comparison module; wherein the reference voltage and the resistance value of the adjustment resistor unit are negatively correlated with the preset reference frequency.

2. The frequency discrimination circuit according to claim 1, characterized in that, The switched capacitor module includes: a first resistor unit and a switched capacitor unit electrically connected to the first resistor unit; wherein, the switched capacitor unit includes: a first switch, a second switch, and a capacitor; One end of the capacitor is electrically connected to the first resistor unit through the first switch, and the other end is grounded; one end of the second switch is electrically connected to the first resistor through the first switch, and the other end is grounded; wherein, the first input terminal of the comparison module is connected to the connection point between the switched capacitor unit and the first resistor unit; The first switch and the second switch are used to control the charging and discharging of the capacitor according to the signal to be corrected; Specifically, when the first switch is closed and the second switch is open, the capacitor is in a charging state; when the second switch is closed and the first switch is open, the capacitor is in a discharging state.

3. The frequency discrimination circuit according to claim 2, characterized in that, When the signal to be corrected is high, the capacitor is in a charging state; When the signal to be corrected is low, the capacitor is in a discharged state.

4. The frequency discrimination circuit according to claim 2 or 3, characterized in that, The voltage to be measured is equal to the voltage drop across the equivalent resistance of the switched capacitor unit. The resistance value of the equivalent resistance of the switched capacitor unit is negatively correlated with the frequency of the signal to be corrected and negatively correlated with the capacitance value of the capacitor in the switched capacitor unit.

5. The frequency discrimination circuit according to claim 1, characterized in that, The comparison module includes a first control unit, a second control unit, a comparison unit, and a switching unit; During a first preset time period of the signal to be corrected, the first input terminal of the comparison module is electrically connected to the non-inverting input terminal of the comparison unit through the first control unit, and the second input terminal of the comparison module is electrically connected to the inverting input terminal of the comparison unit through the second control unit. During the second preset time period of the signal to be corrected, the first input terminal of the comparison module is electrically connected to the inverting input terminal of the comparison unit through the first control unit, and the second input terminal of the comparison module is electrically connected to the non-inverting input terminal of the comparison unit through the second control unit. The input terminal of the switching unit is electrically connected to the output terminal of the comparison unit, and is used to generate and output a comparison result based on the comparison signal generated and output by the comparison unit within the first preset time period, and to generate and output the comparison result based on the inverted signal of the comparison signal generated and output by the comparison unit within the second preset time period.

6. The frequency discrimination circuit according to claim 5, characterized in that, The first preset time is the time when the comparison unit generates the odd-numbered comparison signal, and the second preset time is the time when the comparison unit generates the even-numbered comparison signal.

7. The frequency discrimination circuit according to claim 1, characterized in that, The frequency discrimination circuit also includes: A voltage regulator module is connected at the connection point between the switched capacitor module and the first input terminal of the comparator module, and is used to reduce voltage fluctuations at the connection point between the switched capacitor module and the first input terminal of the comparator module.

8. The frequency discrimination circuit according to claim 1, characterized in that, The signal to be corrected is a clock signal.

9. A clock correction circuit, characterized in that, The clock correction circuit includes a frequency discrimination circuit according to any one of claims 1-8.

10. The clock correction circuit according to claim 9, characterized in that, The clock correction circuit also includes: A clock control circuit, the input of which is electrically connected to the output of the comparison module, is used to generate and output a control value based on the comparison result; and A clock generating circuit, the control terminal of which is electrically connected to the output terminal of the clock control circuit, and the output terminal of which is electrically connected to the switched capacitor module, the clock generating circuit is used to determine the frequency of the signal to be corrected according to the control value, and output the signal to be corrected to the switched capacitor module.

11. The clock correction circuit according to claim 10, characterized in that, The clock control circuit includes: A register module, whose first input terminal is electrically connected to the output terminal of the comparison module, and whose second input terminal is electrically connected to the output terminal of the clock generation circuit, is used to digitize the comparison result output by the comparison module according to the signal to be corrected, and output the digitized comparison result. The digital integration module has its input terminal electrically connected to the output terminal of the register module and its output terminal electrically connected to the control terminal of the clock generation circuit. The digital integration module is used to generate an accumulated value based on each of the digitized comparison results, and generate a control value corresponding to the sum of the accumulated values ​​when the absolute value of the sum of the accumulated values ​​is greater than a preset threshold.

12. The clock correction circuit according to claim 11, characterized in that, The clock generating circuit includes: A clock generation module, whose control terminal is electrically connected to the output terminal of the digital integration module, is used to determine the frequency of the reference clock signal according to the control value and output the reference clock signal. The frequency divider module has its input terminal electrically connected to the output terminal of the clock generation module and its output terminal electrically connected to the switched capacitor module. The frequency divider module is used to output the signal to be corrected according to the preset divisor and the reference clock signal.

13. The clock correction circuit according to claim 12, characterized in that, The clock correction circuit further includes a relationship determination module and a signal control module; wherein the relationship determination module is electrically connected to the signal control module. The relationship determination module is used to determine a numerical correspondence based on the change in the control value output by the digital integration module when the signal to be corrected is completed and the preset divisor of the frequency division module changes; wherein, the numerical correspondence is the correspondence between the change in the preset divisor and the change in the control value. The signal control module is used to determine the control value currently output by the digital integral module based on the numerical correspondence and the current preset divisor of the frequency division module.

14. A chip, characterized in that, The chip includes: a clock correction circuit according to any one of claims 9 to 13.

15. An information processing device, characterized in that, The information processing device includes: the chip according to claim 14.

16. The information processing apparatus according to claim 15, characterized in that, The information processing device is applied to at least one electronic device in the group consisting of smartphones, smart TVs, smartwatches, smart bracelets, tablets, desktop computers, laptops, all-in-one computers, access control devices, wireless network equipment, and wireless computer peripherals.

17. The information processing apparatus according to claim 15, characterized in that, The information processing device is used in industrial computers.

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