A readout circuit with arbitrary windowing function

Abstract

The present invention relates to a readout circuit with an arbitrary windowing function, belonging to the fields of optoelectronic technology and microelectronic technology. The readout circuit includes a signal preprocessing circuit, a column control circuit, a column gating circuit, a row control circuit and a row gating circuit; the column control circuit and the row control circuit are respectively connected to the signal preprocessing circuit; the column gating circuit is connected to the column control circuit; the row gating circuit is connected to the row control circuit; the present invention does not use a combinational logic circuit, thus avoiding the problem of competition and risk; a reusable circuit is used, which has good scalability, and when the array changes, the circuit does not need to be re-customized and can be applied to readout circuits of different arrays; the present invention controls the window position by the control word without occupying the pixel area, thereby realizing the windowing of a minimum window size of 1×1 at any position in the readout circuit, and is easy to promote and apply.

Description

Technical Field

[0001] The invention belongs to the field of optoelectronics and microelectronics, and relates to a focal plane readout circuit in an imaging system, and in particular to a readout circuit with an arbitrary windowing function of a COMS image sensor. Background Art

[0002] The main function of the readout circuit (ROIC) is to perform pre-processing (such as integration, amplification, filtering, and sampling / holding, etc.) on the weak electrical signals sensed by the detector and the parallel / serial conversion of the signal. As one of the main components of the COMS image sensor, the readout circuit is a very important link in the entire system, and its performance directly affects the imaging quality. With the continuous development of infrared detector technology, the requirements for readout circuits are getting higher and higher. The continuous expansion of the image sensor array has put forward higher requirements for data transmission, power consumption, and layout design and wiring. One of the important functions of the COMS image sensors currently developed is the random windowing function. Random windowing readout, also known as the multi-window opening function or the region of interest readout function, is an effective way to improve the detector readout frame rate. With the continuous development of COMS image sensor technology, the detector resolution has also increased. In the case of high resolution, in order to reduce bandwidth and power consumption, one of the methods is to read out only the window area, that is, the random windowing function. In addition, random windowing can also be used for different applications, such as target tracking or pattern recognition, to improve processing speed and efficiency by changing the image size. Especially on large-array COMS image sensors, the user-reconstructable image size helps to observe the area of ​​interest and quickly export the signal of the specified area.

[0003] The paper "640×512-25um Multifunctional Infrared Readout Circuit Design" discloses a windowing scheme for the readout circuit 1, which selects the circuit line by line through a Gray code counter and decoder. However, the circuit still has the following specific problems that need to be improved:

[0004] 1. When the array is large, the decoder will have serious contention issues, resulting in output errors.

[0005] 2. When the array changes, the decoder circuit is different, which requires the circuit to be re-customized.

[0006] US Patent US009894294B2 discloses a windowing scheme 2 for a readout circuit, in which an independent logic circuit and storage circuit are designed inside each pixel, and an independent control signal bus is used to write control words. However, the circuit still has the following specific problems that need to be improved:

[0007] 1. The control circuit occupies the space inside the pixel, making it difficult to reduce the pixel area;

[0008] 2. There are many control words. Each time the window position changes, the control words need to be rewritten, resulting in slow window change speed.

[0009] The paper "A 1 K×1 K high dynamic range CMOS image sensor with on-chip programmable region-of-interest readout" discloses a windowing scheme for the readout circuit 3, which treats a set of pixel sets as subarrays and marks them at the same time. This scheme places registers and logic circuits in each set of subarrays. When the circuit reads out, it scans the values ​​in the registers in each set of pixel sets, marks valid readouts, and skips invalid ones. However, the circuit still has the following specific problems that need to be improved:

[0010] 1. The minimum window size is limited by the subarray size, and the minimum size is 32×32;

[0011] 2. The control circuit occupies the space inside the pixel, making it difficult to reduce the pixel area;

[0012] Therefore, how to overcome the shortcomings of the existing technology is an urgent problem to be solved in the field of optoelectronic technology and microelectronic technology. Summary of the invention

[0013] The purpose of the present invention is to solve the shortcomings of the prior art and provide a readout circuit with an arbitrary windowing function, which is applied to the readout circuit of a CMOS image sensor. The row selection and column selection signals generated by the circuit support windowing of any size at any position of the image sensor. It has the characteristics of minimum 1×1 windowing, does not occupy pixel area, has good scalability, and is easy to promote and apply.

[0014] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0015] A readout circuit with an arbitrary windowing function comprises a signal preprocessing circuit, a column control circuit, a column gating circuit, a row control circuit and a row gating circuit;

[0016] A signal preprocessing circuit is used to receive external data WIN_DATA, preprocess the data, output row start data DATARS, row end data DATARE, row clock data DATARCP and data change signal REDATA to the row control circuit, and output column start data DATACS, column end data DATACE, column clock data DATACCP and data change signal REDATA to the column control circuit;

[0017] The column control circuit is connected to the signal preprocessing circuit and is used to receive the column start data DATACS, the column end data DATACE, the column clock data DATACCP and the data change signal REDATA generated by the signal preprocessing circuit, and the column start signal CST, and generate a column selection signal CS <0> , column register enable signal COL_ST, column window start signal ROI_CS, column window end signal COL_ED, column clock CLKC and column shift register reset signal RST_C;

[0018] A column gating circuit, connected to the column control circuit, is used to receive a signal output by the column control circuit and control the gating of different columns;

[0019] The row control circuit is connected to the signal preprocessing circuit and is used to receive the row start data DATARS, the row end data DATARE, the row clock data DATARCP and the data change signal REDATA, as well as the frame start signal FST, and generate the row selection signal RS <0> , row register enable signal ROW_ST, row window start signal ROI_RS, row window end signal ROW_ED, row clock CLKR and row shift register reset signal RST_R;

[0020] The row gating circuit is connected to the row control circuit and is used to receive the signal output by the row control circuit and control the gating of different rows.

[0021] Further, preferably, the column gating circuit and the row gating circuit each include a plurality of selection sub-circuits;

[0022] The column selection circuit is used to receive the signal output by the column control circuit and output the selection signal CS <n>, control the gating of different columns;

[0023] The row selection circuit is used to receive the signal output by the column row control circuit and output the selection signal RS <n>, control the strobe of different rows;

[0024] The selection subcircuit comprises a memory, a first AND gate, an OR gate, a second AND gate, and a shift register.

[0025] Further, preferably, the selection subcircuit in the row gating circuit is specifically:

[0026] The enable end of the memory is connected to the row register enable signal ROW_ST, and the output end and the row window start signal ROI_RS are connected to the input end of the first AND gate. The output of the first AND gate is connected to the row selection signal RS <n-1>The output of the OR gate and the row window end signal ROW_ED are connected to the input of the second AND gate. The output of the second AND gate is connected to the input of the shift register. The clock of the shift register is connected to the row clock CLKR. The reset end of the shift register is connected to the row shift register reset signal RST_R. The output end of the shift register outputs the row selection signal RS <n>, and connected to the input of the memory; the row selection signal RS <n>Used to select the Nth row of the array.

[0027] Further, preferably, the selection subcircuit in the column gating circuit is specifically:

[0028] The enable end of the memory is connected to the column register enable signal COL_ST, and the output end and the column window start signal ROI_CS are connected to the input end of the first AND gate. The output of the first AND gate is connected to the column selection signal CS <n-1>The output of the OR gate and the column window end signal COL_ED are connected to the input of the second AND gate, the output of the second AND gate is connected to the input of the shift register, the clock of the shift register is connected to the column clock CLKC, the reset end of the shift register is connected to the column shift register reset signal RST_C, and the output end of the shift register outputs the column selection signal CS <n>, and connected to the input of the memory; column selection signal CS <n>Used to select the Nth column of the array.

[0029] Further, preferably, in the column gating circuit, the output of the shift register is connected to the output terminal of the first AND gate in the selection subcircuit of the next column;

[0030] In the row selection circuit, the output of the shift register is connected to the output end of the first AND gate in the selection subcircuit of the next row.

[0031] Furthermore, preferably, the signal preprocessing circuit includes multiple triggers, the clocks of all triggers are connected together, the clock signal is CP, the input end of the trigger directly receives external data WIN_DATA, when the clock signal is valid, the input data passes through the trigger and unifies the timing, and then the data is classified, the output column start data DATACS, column end data DATACE, column clock data DATACCP and data change signal REDATA are transmitted to the column control circuit 2, and the output row start data DATARS, row end data DATARE, row clock data DATARCP and data change signal REDATA are transmitted to the row control circuit 4; the external data WIN_DATA is the control data for windowing, which includes data for controlling the window size and position, and clock frequency data.

[0032] Further, preferably, the row control circuit includes a first frequency divider, a first counting comparator, a second counting comparator, a first D flip-flop, a second D flip-flop, and a third D flip-flop, the input end of the frequency divider is DATARCP, the clock signal is the basic clock signal DCLK, and the row clock CLKR is generated; the first counting comparator has the row start data DATARS as input, the row clock CLKR as input clock, and the row register enable signal ROW_ST as output; the second counting comparator has the row end data DATARE as input, the row clock CLKR as input clock, and the row window end signal ROW_ED as output; the first D flip-flop has the row register enable signal ROW_ST as input, the row clock CLKR as input clock, and the shift register reset signal RST_R as output; the second D flip-flop has the frame start signal FST as input, the row clock CLKR as input clock, and the row window start signal ROI_RS as output; the third D flip-flop has the data change signal REDATA as input clock, the row clock CLKR as input clock, and the row select signal RS as output. <0> .

[0033] Further, preferably, the column control circuit includes a second frequency divider, a third counter comparator, a fourth counter comparator, a fourth D flip-flop, a fifth D flip-flop, and a sixth D flip-flop, the input end of the second frequency divider is DATACCP, the clock signal is the basic clock signal DCLK, and the column clock CLKC is generated; the third counter comparator, its input is the column start data DATACS, the input clock is the column clock CLKC, and the output is the column register enable signal COL_ST; the fourth counter comparator input is the column end data DATACE, the input clock is the column clock CLKC, and the output is the column window end signal COL_ED; the fourth D flip-flop input is the column register enable signal COL_ST, the input clock is the column clock CLKC, and the output is the column shift register reset signal RST_C; the fifth D flip-flop input is the column start signal CST, the input clock is the column clock CLKC, and the output is the column window start signal ROI_CS; the sixth D flip-flop input is the data change signal REDATA, the input clock is the column clock CLKR, and the output is the column select signal CS <0> .

[0034] Further, preferably, the counting comparator includes a counter and a comparator; the input of the counter is the clock CLKCT, the output of the counter and the input WIN_DATA are connected to the comparator input, when the clock CLKCT is valid, the counter starts counting, and when the output of the counter is consistent with the input external data WIN_DATA, the comparator output is a high level.

[0035] In the present invention, the first frequency divider and the second frequency divider are circuits with a clock frequency dividing function, and do not specifically refer to a certain circuit structure.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] (1) The present invention provides a readout circuit with an arbitrary windowing function, which is used to control a digital focal plane readout circuit. The present invention does not use a combinational logic circuit, thereby avoiding the problem of competition and risk. A reusable circuit is used, which has good scalability. When the array changes, the circuit does not need to be re-customized and can be applied to readout circuits of different arrays.

[0038] (2) The present invention reduces the number of control words and optimizes the control word logic, so that when the window position and size are changed, the window change speed is increased;

[0039] (3) The present invention controls the window position by the control word without occupying the pixel area, thereby realizing window opening at any position in the readout circuit with a minimum window size of 1×1, which is easy to promote and apply.

[0040] The comparison with the three solutions mentioned in the present invention is shown in Table 1.

[0041] Table 1

[0042]

[0043] Solution 1 is more commonly used and the contention risk of the circuit on a small array will not have a great impact on the circuit, so it has a better performance on a small array. However, when the array is larger, a more serious contention risk phenomenon will occur. In order to reduce the impact on the circuit, the only thing to do is to increase the redundant time. Moreover, when the array size changes, the decoder circuit will change, and the circuit needs to be re-customized, which increases the workload.

[0044] Solution 2 places the circuit inside the pixel while ensuring that the minimum window size remains unchanged at 1×1, avoiding the risk of competition. It also uses a modular circuit design, so there is no need to re-customize the design when the array size changes, which increases the scalability of the circuit. However, the additional circuit in this solution occupies the area inside the pixel, making it difficult to reduce the pixel size. At the same time, since there is a control word in each pixel, the control word needs to be rewritten when the window size or position changes, which takes a long time.

[0045] Solution 3 regards a group of pixels as a subarray, which reduces the area occupied by the pixels and the number of control words. When the window size or position changes, the time to rewrite the control words is reduced compared to the single-pixel control word architecture. However, the minimum window size of this architecture is equal to the size of the subarray. If you want to further reduce the minimum window size, you need to further reduce the size of the subarray. At this time, the area occupied by the control module and the storage unit in the circuit will increase, and the area of ​​the pixel will further increase.

[0046] The architecture proposed in the present invention also adopts a synchronous readout mode to avoid the competition risk phenomenon and adopts a repeated module, so there is no need to redesign when the array size changes; compared with the sub-array architecture, the minimum window size of this scheme reaches 1×1, and the control circuit is designed on the periphery of the array, without occupying the pixel area, making it easy to reduce the pixel size; compared with the single-pixel control word scheme, under the same minimum window size, no pixel area is occupied, and the window change time is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a structural block diagram of a readout circuit with an arbitrary windowing function according to the present invention;

[0048] Figure 2 It is a schematic diagram of the overall structure of the present invention;

[0049] Figure 3 is a schematic diagram of the structure of a selection subcircuit according to an embodiment of the present invention;

[0050] Figure 4 is a connection diagram of a selection subcircuit according to an embodiment of the present invention;

[0051] Figure 5 is a schematic diagram of writing a row control word according to an embodiment of the present invention;

[0052] Figure 6 is a schematic diagram of writing a column control word according to an embodiment of the present invention;

[0053] Figure 7 is a schematic diagram of row window selection according to an embodiment of the present invention;

[0054] Figure 8 is a schematic diagram of column window gating according to an embodiment of the present invention;

[0055] Fig. 9 is a schematic diagram of a signal preprocessing circuit according to an embodiment of the present invention;

[0056] Fig.10 is a schematic diagram of a row control circuit according to an embodiment of the present invention;

[0057] Fig.11 is a schematic diagram of a column control circuit according to an embodiment of the present invention;

[0058] Fig.12 Schematic diagram of a counting comparison circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The present invention is further described in detail below in conjunction with embodiments.

[0060] Those skilled in the art will appreciate that the following examples are only used to illustrate the present invention and should not be considered to limit the scope of the present invention. If no specific techniques or conditions are specified in the examples, the techniques or conditions described in the literature in the art or the product specifications are used. If the manufacturer of the materials or equipment used is not specified, they are all conventional products that can be purchased.

[0061] Those skilled in the art will appreciate that, unless expressly stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" to another element, it may be directly connected to the other element, or there may be intermediate elements. The term "and / or" used herein includes any unit and all combinations of one or more associated listed items.

[0062] In the description of the present invention, unless otherwise specified, "plurality" means two or more than two. The terms "inside", "upper", "lower", etc. indicate positions or state relationships based on the positions or state relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operate in a specific position, and therefore cannot be understood as limiting the present invention.

[0063] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "provided with" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention will be understood according to specific circumstances.

[0064] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the field to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0065] like Figure 1 and Figure 2 As shown, a readout circuit with arbitrary windowing function includes a signal preprocessing circuit 1, a column control circuit 2, a column gating circuit 3, a row control circuit 4 and a row gating circuit 5;

[0066] The signal preprocessing circuit 1 is used for receiving external data WIN_DATA, preprocessing the data, outputting row start data DATARS, row end data DATARE, row clock data DATARCP and data change signal REDATA to the row control circuit 4, and outputting column start data DATACS, column end data DATACE, column clock data DATACCP and data change signal REDATA to the column control circuit 2;

[0067] The column control circuit 2 is connected to the signal preprocessing circuit 1 and is used to receive the column start data DATACS, the column end data DATACE, the column clock data DATACCP and the data change signal REDATA generated by the signal preprocessing circuit 1, and the column start signal CST, and generate the column selection signal CS <0> , column register enable signal COL_ST, column window start signal ROI_CS, column window end signal COL_ED, column clock CLKC and column shift register reset signal RST_C;

[0068] The column gating circuit 3 is connected to the column control circuit 2 and is used to receive the signal output by the column control circuit 2 to control the gating of different columns;

[0069] The row control circuit 4 is connected to the signal preprocessing circuit 1 and is used to receive the row start data DATARS, the row end data DATARE, the row clock data DATARCP and the data change signal REDATA, as well as the frame start signal FST, and generate the row selection signal RS <0> , row register enable signal ROW_ST, row window start signal ROI_RS, row window end signal ROW_ED, row clock CLKR and row shift register reset signal RST_R;

[0070] The row selection circuit 5 is connected to the row control circuit 4 and is used to receive the signal output by the row control circuit 4 to control the selection of different rows.

[0071] In a specific preferred embodiment, the column gating circuit 3 and the row gating circuit 5 each include a plurality of selection sub-circuits 6;

[0072] The column selection circuit 3 is used to receive the signal output by the column control circuit 2 and output the selection signal CS <n>, control the gating of different columns;

[0073] The row selection circuit 5 is used to receive the signal output by the column row control circuit 4 and output the selection signal RS <n>, control the strobe of different rows;

[0074] like Figure 3 As shown, the selection subcircuit 6 includes a memory 7, a first AND gate 8, an OR gate 9, a second AND gate 10, and a shift register 11.

[0075] Specific preferred solutions, such as Figure 3 and Figure 4 As shown, the selection subcircuit 6 in the row gating circuit 5 is specifically:

[0076] The enable terminal of the memory 7 is connected to the row register enable signal ROW_ST, and the output terminal and the row window start signal ROI_RS are connected to the input terminal of the first AND gate 8. The output of the first AND gate 8 is connected to the row selection signal RS <n-1>The output of the OR gate 9 and the row window end signal ROW_ED are connected to the input of the second AND gate 10, and the output of the second AND gate 10 is connected to the input of the shift register 11. The clock of the shift register 11 is connected to the row clock CLKR, the reset end of the shift register 11 is connected to the row shift register reset signal RST_R, and the output end of the shift register 11 outputs the row selection signal RS <n>, and connected to the input terminal of the memory 7; the row selection signal RS <n>Used to select the Nth row of the array.

[0077] In a specific preferred embodiment, the selection subcircuit 6 in the column gating circuit 3 is specifically:

[0078] The enable terminal of the memory 7 is connected to the column register enable signal COL_ST, and the output terminal and the column window start signal ROI_CS are connected to the input terminal of the first AND gate 8. The output of the first AND gate 8 is connected to the column selection signal CS <n-1>The output of the OR gate 9 and the column window end signal COL_ED are connected to the input of the second AND gate 10, and the output of the second AND gate 10 is connected to the input of the shift register 11. The clock of the shift register 11 is connected to the column clock CLKC, the reset end of the shift register 11 is connected to the column shift register reset signal RST_C, and the output end of the shift register 11 outputs the column selection signal CS. <n>, and connected to the input terminal of memory 7; column selection signal CS <n>Used to select the Nth column of the array.

[0079] In a specific preferred embodiment, in the column gating circuit 3, the output of the shift register 11 is connected to the output end of the first AND gate 8 in the selection subcircuit 6 of the next column;

[0080] In the row selection circuit 5, the output of the shift register 11 is connected to the output end of the first AND gate 8 in the selection sub-circuit 6 of the next row.

[0081] A specific preferred solution is that the signal preprocessing circuit 1 includes a plurality of triggers 14, the clocks of all the triggers 14 are connected together, the clock signal is CP, the input end of the trigger 14 directly receives the external data WIN_DATA, when the clock signal is valid, the input data passes through the trigger 14, the timing is unified, and then the data is classified, the output column start data DATACS, the column end data DATACE, the column clock data DATACCP and the data change signal REDATA are transmitted to the column control circuit 2, the output row start data DATARS, the row end data DATARE, the row clock data DATARCP and the data change signal REDATA are transmitted to the row control circuit 4; the external data WIN_DATA is the control data for windowing, which includes the data for controlling the window size and position, and the clock frequency data.

[0082] Specifically, the row control circuit 4 includes a first frequency divider 15, a first counter comparator 16, a second counter comparator 17, a first D flip-flop 18, a second D flip-flop 19, and a third D flip-flop 20. The input end of the frequency divider 15 is DATARCP, and the clock signal is the basic clock signal DCLK, which generates the row clock CLKR; the first counter comparator 16 has the row start data DATARS as input, the row clock CLKR as input clock, and the row register enable signal ROW_ST as output; the second counter comparator 17 has the row end data as input, and the row register enable signal ROW_ST as output clock. According to DATARE, the input clock is the row clock CLKR, and the output is the row window end signal ROW_ED; the input of the first D flip-flop 18 is the row register enable signal ROW_ST, the input clock is the row clock CLKR, and the output is the shift register reset signal RST_R; the input of the second D flip-flop 19 is the frame start signal FST, the input clock is the row clock CLKR, and the output is the row window start signal ROI_RS; the input of the third D flip-flop 20 is the data change signal REDATA, the input clock is the row clock CLKR, and the output is the row select signal RS <0> .

[0083] Specifically, the column control circuit 2 includes a second frequency divider 21, a third counter comparator 22, a fourth counter comparator 23, a fourth D flip-flop 24, a fifth D flip-flop 25, and a sixth D flip-flop 26. The input end of the second frequency divider 21 is DATACCP, and the clock signal is the basic clock signal DCLK, which generates a column clock CLKC; the third counter comparator 22 has an input of the column start data DATACS, an input clock of the column clock CLKC, and an output of the column register enable signal COL_ST; the fourth counter comparator 23 has an input of the column end data According to DATACE, the input clock is the column clock CLKC, and the output is the column window end signal COL_ED; the input of the fourth D flip-flop 24 is the column register enable signal COL_ST, the input clock is the column clock CLKC, and the output is the column shift register reset signal RST_C; the input of the fifth D flip-flop 25 is the column start signal CST, the input clock is the column clock CLKC, and the output is the column window start signal ROI_CS; the input of the sixth D flip-flop 26 is the data change signal REDATA, the input clock is the column clock CLKR, and the output is the column select signal CS <0> .

[0084] In a specific preferred embodiment, the counting comparator includes a counter 27 and a comparator 28; the input of the counter 27 is the clock CLKCT, the output of the counter 27 and the input WIN_DATA are connected to the input of the comparator 28, when the clock CLKCT is valid, the counter 27 starts counting, when the output of the counter 27 is consistent with the input external data WIN_DATA, the output of the comparator 28 is a high level.

[0085] In one embodiment, Figure 3 As shown, it is a schematic diagram of the structure of the selection subcircuit 6. The selection subcircuit 6 is composed of a memory 7, a first AND gate 8, an OR gate 9, a second AND gate 10, and a shift register 11. Among them, the memory 7 and the shift register 11 are triggers with a reset function. The enable end of the memory 7 is connected to the row register enable signal ROW_ST, the reset end is connected to the row memory reset signal RST_DR, the output end and the row window start signal ROI_RS are connected to the input end of the first AND gate 8, and the output of the first AND gate 8 is connected to the row selection signal RS <n-1>The output of the OR gate 9 and the row window end signal ROW_ED are connected to the input of the second AND gate 10, and the output of the second AND gate 10 is connected to the input of the shift register 11. The clock of the shift register 11 is connected to the row clock CLKR, the reset end of the shift register 11 is connected to the row shift register reset signal RST_R, and the output end of the shift register 11 outputs the row selection signal RS <n>, and connected to the input terminal of the memory 7. The signal RS <n>Used to select the Nth row of the array, RS <n-1>Used to select the N-1th row of the array.

[0086] In this embodiment, if Figure 4 As shown, it can be Figure 3 The selection subcircuit shown is repeatedly used to control multiple rows and columns, so that the present invention has excellent scalability and repeatability, and can be applied to readout circuits of different array sizes. Figure 4 2 is a connection diagram of the selection sub-circuit. The output of the shift register 11 of the N-1th selection sub-circuit is connected to the output end of the first AND gate 8 in the Nth selection sub-circuit 6.

[0087] In one embodiment, the window control circuit repeatedly constructed by the above-mentioned selection subcircuit can realize the reading of any window position. The reading of any window position is divided into two processes: control word writing and window reading. The control word writing is further divided into two parts: row control word writing and column control word writing. The window reading is divided into two parts: row window selection and column window selection.

[0088] In one embodiment, Figure 5 The figure shows the row control word writing part in the control word writing process, wherein area 12 is the window area for analog readout. Figure 5 (a) is the initial state of the circuit, signal RS <0> The first bit selection subcircuit of the row selection circuit is input to the input end of the shift register 11. At the same time, the row clock CLKR is input to the clock end of the shift register 11. The first bit shift register 11 in the row selection circuit 5 latches the input start signal RS <0> ,like Figure 5 As shown in (b), the row clock CLKR is continuously input, and the row control word signal is shifted backward one by one, such as Figure 5 As shown in (c), when the control word is shifted to the initial position of the row, which is the third row in this embodiment, the row control circuit 4 generates a row register enable signal ROW_ST, the control word register 7 reads the output of the current corresponding shift register, and the row control word signal is written into the control word register 7, as shown in FIG. Figure 5 As shown in (d), after the control word signal is written, the row control circuit 4 generates a row shift register reset signal RST_R to reset the row shift register.

[0089] In one embodiment, Figure 6 FIG. 1 shows the column control word writing part in the control word writing process of this embodiment. Figure 6 (a) is the initial state of the circuit, signal CS <0> The first bit selection subcircuit of the column selection circuit is input to the input end of the shift register 11. At the same time, the column clock CLKC is input to the clock end of the shift register 11. The first bit shift register 11 in the column selection circuit 3 latches the input start signal CS. <0> ,like Figure 6 As shown in (b), the column clock CLKC is continuously input, and the column control word signal is shifted backward one by one, such as Figure 6 As shown in (c), when the control word is shifted to the initial position of the column, which is the third column in this embodiment, the column control circuit 2 generates a column register enable signal COL_ST, the control word register 7 reads the output of the current corresponding shift register, and the column control word signal is written into the control word register 7, as shown in FIG. Figure 6 As shown in (d), after the control word signal is written, the column control circuit 2 generates a column shift register reset signal RST_C to reset the column shift register.

[0090] In this embodiment, the window readout part is divided into a row window gating part and a column window gating part. During each row window gating time, the column window gating always completes the process of gating each column one by one.

[0091] In one embodiment, Figure 7 As shown in the figure, it is the row window selection part in the window readout. Figure 7 (a) is the state when the control word signal is written. Figure 7 (b) is the row window start signal ROI_RS input to the shift register 11. The shift register 11 is affected by the data in the control word register 7 and changes at the start row of the window, corresponding to the row selection. Figure 7 (c) is the clock signal CLKR input of the shift register 11. The control word in the shift register 11 moves downward to select the next row. Figure 7 (d) The clock signal CLKR of the shift register 11 is continuously input, and the control word in the shift register 11 moves downward and is selected to the last row of the window. When the last row of the window is selected, the row control circuit 4 generates a row window end signal ROW_ED to reset the shift register data and wait for the next frame to start.

[0092] In one embodiment, Figure 8 As shown in the figure, it is the column window selection part in the window readout. Figure 8 (a) is the state when the control word signal is written. Bus 13 is the read data bus. Each pixel is connected to bus 13. When the pixel is selected, the data in the pixel is transferred to bus 13 and read out. Figure 8 (b) The column window start signal ROI_CS is input into the shift register 11. The shift register 11 is affected by the data in the control word register 7. The start column of the window changes, and the corresponding column is selected, thereby selecting the corresponding pixel. Figure 8 (c) is the clock signal CLKC input to the shift register 11. The control word in the shift register 11 moves downward, selecting each column in turn until the last column in the window. Figure 8 As shown in (d), when the last column of the window is selected, the column control circuit 2 generates a column window end signal COL_ED, the shift register data is reset, and waits for the next row to start.

[0093] In one embodiment, Fig. 9 As shown, the signal preprocessing circuit 1 in the circuit is composed of a plurality of triggers 14. The clocks of all the triggers 14 are connected together. The clock signal is CP. The input end of the trigger 14 directly receives the external input data. When the clock signal is valid, the input data passes through the trigger 14, unifies the timing, and then classifies the data. The output column start data DATACS and the column end data DATACE are transmitted to the column control circuit 2, and the output row start data DATARS and the row end data DATARE are transmitted to the row control circuit 4. At the same time, the data change signal REDATA is output to the column control circuit 2 and the row control circuit 4.

[0094] In one embodiment, Fig.10 As shown, the row control circuit 4 includes a first frequency divider 15, a first counter comparator 16, a second counter comparator 17, a first D flip-flop 18, a second D flip-flop 19, and a third D flip-flop 20. The input end of the frequency divider 15 is DATARCP, and the clock signal is the basic clock signal DCLK, which generates the row clock CLKR; the first counter comparator 16, whose input is the row start data DATARS, whose input clock is the row clock CLKR, and whose output is the row register enable signal ROW_ST; the second counter comparator 17, whose input is the row end data D ATARE, the input clock is the row clock CLKR, and the output is the row window end signal ROW_ED; the input of the first D flip-flop 18 is the row register enable signal ROW_ST, the input clock is the row clock CLKR, and the output is the shift register reset signal RST_R; the input of the second D flip-flop 19 is the frame start signal FST, the input clock is the row clock CLKR, and the output is the row window start signal ROI_RS; the input of the third D flip-flop 20 is the data change signal REDATA, the input clock is the row clock CLKR, and the output is the row select signal RS <0> .

[0095] In one embodiment, Fig.11 As shown, the column control circuit 2 includes a second frequency divider 21, a third counter comparator 22, a fourth counter comparator 23, a fourth D flip-flop 24, a fifth D flip-flop 25, and a sixth D flip-flop 26. The input end of the second frequency divider 21 is DATACCP, and the clock signal is the basic clock signal DCLK, which generates a column clock CLKC; the third counter comparator 22 has an input of the column start data DATACS, an input clock of the column clock CLKC, and an output of the column register enable signal COL_ST; the fourth counter comparator 23 has an input of the column end data D ATACE, the input clock is the column clock CLKC, and the output is the column window end signal COL_ED; the input of the fourth D flip-flop 24 is the column register enable signal COL_ST, the input clock is the column clock CLKC, and the output is the column shift register reset signal RST_C; the input of the fifth D flip-flop 25 is the column start signal CST, the input clock is the column clock CLKC, and the output is the column window start signal ROI_CS; the input of the sixth D flip-flop 26 is the data change signal REDATA, the input clock is the column clock CLKR, and the output is the column select signal CS <0> .

[0096] In one embodiment, Fig.12 As shown, the counting comparator (the first counting comparator 16, the second counting comparator 17, the third counting comparator 22, and the fourth counting comparator 23) includes a counter 27 and a comparator 28; the input of the counter 27 is the clock CLKCT, and the output of the counter 27 and the input WIN_DATA are connected to the input of the comparator 28. When the clock CLKCT is valid, the counter 27 starts counting, and when the output of the counter 27 is consistent with the input external data WIN_DATA, the output of the comparator 28 is a high level.

[0097] The above shows and describes the basic principles, main features and advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A readout circuit with arbitrary windowing function, It is characterized in that It comprises a signal preprocessing circuit (1), a column control circuit (2), a column gating circuit (3), a row control circuit (4) and a row gating circuit (5); A signal preprocessing circuit (1) is used to receive external data WIN_DATA, preprocess the data, output row start data DATARS, row end data DATARE, row clock data DATARCP and data change signal REDATA to a row control circuit (4), and output column start data DATACS, column end data DATACE, column clock data DATACCP and data change signal REDATA to a column control circuit (2); The column control circuit (2) is connected to the signal preprocessing circuit (1) and is used to receive the column start data DATACS, the column end data DATACE, the column clock data DATACCP and the data change signal REDATA, as well as the column start signal CST generated by the signal preprocessing circuit (1), and generate a column selection signal CS <0> , column register enable signal COL_ST, column window start signal ROI_CS, column window end signal COL_ED, column clock CLKC and column shift register reset signal RST_C; A column gating circuit (3) connected to the column control circuit (2) and used to receive a signal output by the column control circuit (2) and control the gating of different columns; The row control circuit (4) is connected to the signal preprocessing circuit (1) and is used to receive the row start data DATARS, the row end data DATARE, the row clock data DATARCP and the data change signal REDATA, as well as the frame start signal FST, and generate a row selection signal RS <0> , row register enable signal ROW_ST, row window start signal ROI_RS, row window end signal ROW_ED, row clock CLKR and row shift register reset signal RST_R; A row gating circuit (5) connected to the row control circuit (4) and used to receive a signal output by the row control circuit (4) and control the gating of different rows; The column selection circuit (3) and the row selection circuit (5) each include a plurality of selection sub-circuits (6); The column selection circuit (3) is used to receive the signal output by the column control circuit (2) and output a selection signal CS <n> , control the gating of different columns;< / n> The row selection circuit (5) is used to receive the signal output by the column row control circuit (4) and output a selection signal RS <n> , control the strobe of different rows;< / n> The selection subcircuit (6) comprises a memory (7), a first AND gate (8), an OR gate (9), a second AND gate (10), and a shift register (11); The selection subcircuit (6) in the row selection circuit (5) is specifically: The enable end of the memory (7) is connected to the row register enable signal ROW_ST, the output end and the row window start signal ROI_RS are connected to the input end of the first AND gate (8), and the output of the first AND gate (8) is connected to the row selection signal RS <n-1>The first and second AND gates (10) are connected to the input end of an OR gate (9), the output end of the OR gate (9) and the row window end signal ROW_ED are connected to the input end of a second AND gate (10), the output end of the second AND gate (10) is connected to the input end of a shift register (11), the clock of the shift register (11) is connected to the row clock CLKR, the reset end of the shift register (11) is connected to the row shift register reset signal RST_R, and the output end of the shift register (11) outputs a row selection signal RS <n>, and connected to the input terminal of the memory (7); the row selection signal RS <n> Used to select the Nth row of the array;< / n> < / n> The selection subcircuit (6) in the column selection circuit (3) is specifically: The enable end of the memory (7) is connected to the column register enable signal COL_ST, the output end and the column window start signal ROI_CS are connected to the input end of the first AND gate (8), and the output of the first AND gate (8) is connected to the column selection signal CS <n-1>The output end of the OR gate (9) and the column window end signal COL_ED are connected to the input end of the second AND gate (10), the output end of the second AND gate (10) is connected to the input end of the shift register (11), the clock of the shift register (11) is connected to the column clock CLKC, the reset end of the shift register (11) is connected to the column shift register reset signal RST_C, and the output end of the shift register (11) outputs the column selection signal CS <n>, and connected to the input terminal of the memory (7); the column selection signal CS <n> Used to select the Nth column of the array;< / n> < / n> In the column selection circuit (3), the output of the shift register (11) of the N-1th selection subcircuit is connected to the output end of the first AND gate (8) in the Nth selection subcircuit (6); In the row selection circuit (5), the output of the shift register (11) of the N-1th selection sub-circuit is connected to the output end of the first AND gate (8) in the Nth selection sub-circuit (6).

2. The readout circuit with arbitrary windowing function according to claim 1, It is characterized in that The signal preprocessing circuit (1) includes a plurality of triggers (14), the clocks of all the triggers (14) are connected together, the clock signal is CP, the input end of the trigger (14) directly receives external data WIN_DATA, when the clock signal is valid, the input data passes through the trigger (14), the timing is unified, and then the data is classified, the column start data DATACS, the column end data DATACE, the column clock data DATACCP and the data change signal REDATA are output and transmitted to the column control circuit (2), and the row start data DATARS, the row end data DATARE, the row clock data DATARCP and the data change signal REDATA are output and transmitted to the row control circuit (4); the external data WIN_DATA is the control data of the window, which includes the data of controlling the window size and position, and the clock frequency data.

3. The readout circuit with arbitrary windowing function according to claim 1, It is characterized in that The row control circuit (4) comprises a first frequency divider (15), a first counter comparator (16), a second counter comparator (17), a first D flip-flop (18), a second D flip-flop (19), and a third D flip-flop (20). The input end of the frequency divider (15) is DATARCP, and the clock signal is a base clock signal DCLK, which generates a row clock CLKR; the first counter comparator (16) has a row start data DATARS as input, a row clock CLKR as input clock, and a row register enable signal ROW_ST as output; the second counter comparator (17) has a row end data DATARE as input, a row clock CLKR as input clock, and a row window end signal ROW_ED as output; the first D flip-flop (18) has a row register enable signal ROW_ST as input, a row clock CLKR as input clock, and a shift register reset signal RST_R as output; the second D flip-flop (19) has a frame start signal FST as input clock, a row clock CLKR as input clock, and a row window start signal ROI_RS as output; The input of the third D flip-flop (20) is the data change signal REDATA, the input clock is the row clock CLKR, and the output is the row selection signal RS <0> .

4. The readout circuit with arbitrary windowing function according to claim 1, It is characterized in that The column control circuit (2) comprises a second frequency divider (21), a third counter comparator (22), a fourth counter comparator (23), a fourth D flip-flop (24), a fifth D flip-flop (25), and a sixth D flip-flop (26). The second frequency divider (21) has an input terminal DATACCP, a clock signal is a base clock signal DCLK, and generates a column clock CLKC; the third counter comparator (22) has an input terminal column start data DATACS, an input clock is a column clock CLKC, and an output is a column register enable signal COL_ST; the fourth counter comparator (23) has an input terminal column end data DATACE, an input clock is a column clock CLKC, and an output is a column window end signal COL_ED; the fourth D flip-flop (24) has an input terminal column register enable signal COL_ST, an input clock is a column clock CLKC, and an output is a column shift register reset signal RST_C; the fifth D flip-flop (25) has an input terminal column start signal CST, an input clock is a column clock CLKC, and an output is a column window start signal ROI_CS; The input of the sixth D flip-flop (26) is the data change signal REDATA, the input clock is the column clock CLKR, and the output is the column selection signal CS <0> .

5. The readout circuit with arbitrary windowing function according to claim 3 or 4, It is characterized in that The counting comparator comprises a counter (27) and a comparator (28); the input of the counter (27) is a clock CLKCT, the output of the counter (27) and the input WIN_DATA are connected to the input of the comparator (28); when the clock CLKCT is valid, the counter (27) starts counting; when the output of the counter (27) is consistent with the input external data WIN_DATA, the output of the comparator (28) is a high level.

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