Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are disclosed. The method of forming the semiconductor structure includes forming a gate structure on a semiconductor substrate, wherein the semiconductor substrate has a shallow trench isolation, an insulating liner and a conductor; forming a sacrificial layer on the gate structure; forming an insulating layer on the semiconductor substrate, a sidewall of the gate structure and a sidewall of the sacrificial layer; forming a spacer on the insulating layer, wherein the spacer is on the shallow trench isolation and the sidewall of the gate structure; forming an interlayer dielectric layer on the semiconductor substrate and the spacer; removing the sacrificial layer; and etching the interlayer dielectric layer, the insulating layer and the semiconductor substrate by pulsed plasma to form a first contact opening and a second contact opening, wherein a sidewall of the spacer is exposed from the first contact opening, and a polymer layer is formed on the sidewall of the spacer during the etching. Thus, the spacer can be protected from damage due to the intermittent switching frequency of the pulsed plasma.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for forming the same. Background Technology

[0002] Generally, when using continuous etching to form openings in dielectric, insulating, and semiconductor substrates, the plasma in the etching gas collides with the sidewalls of the dielectric layer within the openings. This plasma etching of the dielectric sidewalls leads to the etching of spacers beneath the dielectric layer, damaging the spacers and potentially rendering them unable to protect the gate sidewalls in subsequent processes. Furthermore, when using difluoromethane (CH2F2) as the etching gas to etch dielectric, insulating, and semiconductor substrates, insufficient flow of difluoromethane cannot prevent the spacers from being etched by the plasma during etching, resulting in spacer damage and insufficient protection for the gate. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor structure and a method for forming the same, in which the spacer can be protected from damage and provide sufficient protection due to the intermittent switching frequency characteristic of pulsed plasma.

[0004] One embodiment of the present invention is a semiconductor structure.

[0005] According to one embodiment of the present invention, a semiconductor structure includes a semiconductor substrate, an insulating pad, a gate structure, a spacer, an insulating layer, an interlayer dielectric layer, a first metal contact, and a second metal contact. The semiconductor substrate has shallow trench isolation. The insulating pad is located within the shallow trench isolation of the semiconductor substrate. The gate structure is located on the shallow trench isolation of the semiconductor substrate. The spacer is located on the shallow trench isolation and on the sidewall of the gate structure. The insulating layer is located on the semiconductor substrate and between the sidewall of the gate structure and the spacer. The interlayer dielectric layer is located on the semiconductor substrate and the spacer. The first metal contact is located within the interlayer dielectric layer and the insulating layer. The first metal contact contacts the sidewall of the spacer. The sidewall of the spacer extends in a vertical direction. The second metal contact is located within the shallow trench isolation, the insulating pad, the insulating layer, and the interlayer dielectric layer.

[0006] In one embodiment of the present invention, the height of the second metal contact is greater than the height of the first metal contact.

[0007] In one embodiment of the invention, the semiconductor structure further includes a conductor. The conductor is located in a shallow trench isolation and below an insulating pad. The top of the conductor is located in a second metal contact.

[0008] In one embodiment of the present invention, the semiconductor structure further includes a first dielectric layer. The first dielectric layer is located on the interlayer dielectric layer and the gate structure.

[0009] In one embodiment of the present invention, the semiconductor structure further includes a second dielectric layer. The second dielectric layer is located on the first dielectric layer.

[0010] In one embodiment of the present invention, the semiconductor structure further includes a third metal contact. The third metal contact is located on the gate structure and within the first dielectric layer and the second dielectric layer.

[0011] One embodiment of the present invention is a method for forming a semiconductor structure.

[0012] According to an embodiment of the present invention, a method for forming a semiconductor structure includes: forming a gate structure on a semiconductor substrate, wherein the semiconductor substrate has shallow trench isolation and an insulating pad and a conductor in the shallow trench isolation; forming a sacrificial layer on the gate structure; forming an insulating layer on the semiconductor substrate, on the sidewalls of the gate structure, and on the sidewalls of the sacrificial layer; forming a spacer on the insulating layer, wherein the spacer is located on the shallow trench isolation and on the sidewalls of the gate structure; forming an interlayer dielectric layer on the semiconductor substrate and on the spacer; removing the sacrificial layer; etching the interlayer dielectric layer, the insulating layer, and the semiconductor substrate with pulsed plasma to form a first contact opening and a second contact opening, wherein the sidewalls of the spacer are exposed from the first contact opening, and during etching, a polymer layer is formed on the sidewalls of the spacer and an etched polymer layer is formed; and forming a first metal contact and a second metal contact in the first contact opening and the second contact opening, respectively.

[0013] In one embodiment of the present invention, the polymer layer is formed using difluoromethane (CH2F2), and the flow rate of difluoromethane is in the range of 25 sccm to 35 sccm, and the switching frequency of the pulsed plasma is 50%.

[0014] In one embodiment of the present invention, the method further includes: forming a first dielectric layer on an interlayer dielectric layer, an insulating layer, and a gate structure; and forming a second dielectric layer on the first dielectric layer.

[0015] In one embodiment of the present invention, the method further includes: during the formation of the first contact opening and the second contact opening, etching the first dielectric layer and the second dielectric layer to form a third contact opening, wherein at least a portion of the top surface of the gate structure is exposed from the third contact opening; and during the formation of the first metal contact and the second metal contact, forming a third metal contact in the third contact opening.

[0016] In the above embodiments of the present invention, due to the intermittent switching frequency characteristic of pulsed plasma, when pulsed plasma is on, it can concentrate on etching downwards the interlayer dielectric layer, insulating layer, and semiconductor substrate. When pulsed plasma is off, it can reduce collisions with the interlayer dielectric layer on the semiconductor substrate in the first contact opening, thereby reducing lateral etching. This reduces the sidewalls of the spacer in the interlayer dielectric layer caused by pulsed plasma lateral etching, preventing damage to the spacer and providing sufficient protection for the gate structure in subsequent processes. Furthermore, when pulsed plasma etches the interlayer dielectric layer, insulating layer, and semiconductor substrate, in addition to forming a polymer layer on the sidewalls of the spacer, it can also ensure that the pulsed plasma can etch shallow trench isolation in the semiconductor substrate to form the second contact opening. The polymer layer formed on the sidewalls of the spacer can serve as a protective layer for the spacer. The polymer layer can act as a buffer layer, replacing the sidewalls of the spacer being etched by the pulsed plasma. In this way, the spacer can be prevented from being damaged, providing sufficient protection for the gate structure in subsequent processes. Attached Figure Description

[0017] An embodiment of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, according to standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0018] Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention is shown.

[0019] Figures 2 to 5 Draw Figure 1 Cross-sectional views of the semiconductor structure formation method at different steps.

[0020] Explanation of key figure labels:

[0021] 100, 100a, 100b, 100c - Semiconductor structure; 110 - Semiconductor substrate; 111 - Silicon region; 112 - Shallow trench isolation; 114 - Insulating pad; 116 - Conductor; 118 - Top; 120 - Gate structure; 121 - Sidewall; 122 - First gate electrode; 123 - Top surface; 124 - Gate dielectric; 126 - Second gate electrode; 130 - Insulating layer; 140 - Spacer; 142 - Sidewall; 150 - Interlayer dielectric layer; 16 0 - First dielectric layer, 170 - Second dielectric layer, 300 - Polymer layer, 510 - First metal contact, 520 - Second metal contact, 530 - Third metal contact, h1 - Height, h2 - Height, D1 - Vertical direction, O1 - First contact opening, O2 - Second contact opening, O3 - Third contact opening, P - Pulsed plasma, S1 - Step, S2 - Step, S3 - Step, S4 - Step, S5 - Step, S6 - Step, S7 - Step, S8 - Step. Detailed Implementation

[0022] The following disclosure provides numerous different implementations, or examples, for carrying out various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the subject matter. Of course, these examples are merely illustrative and are not intended to be limiting. Furthermore, element symbols and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself specify the relationship between the various implementations and / or configurations discussed.

[0023] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for descriptive purposes to describe the relationship between one element or feature and another, as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the drawings. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0024] Figure 1A flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present invention is shown. The method for forming the semiconductor structure includes the following steps. First, in step S1, a gate structure is formed on a semiconductor substrate, wherein the semiconductor substrate has shallow trench isolation and an insulating pad and a conductor in the shallow trench isolation. Next, in step S2, a sacrificial layer is formed on the gate structure. Then, in step S3, an insulating layer is formed on the semiconductor substrate, on the sidewalls of the gate structure, and on the sidewalls of the sacrificial layer. Subsequently, in step S4, a spacer is formed on the insulating layer, wherein the spacer is located on the shallow trench isolation and on the sidewalls of the gate structure. Next, in step S5, an interlayer dielectric layer is formed on the semiconductor substrate and on the spacer. Next, in step S6, the sacrificial layer is removed. Then, in step S7, the interlayer dielectric layer, the insulating layer, and the semiconductor substrate are etched with pulsed plasma to form a first contact opening and a second contact opening, wherein the sidewalls of the spacer are exposed from the first contact opening, and during etching, a polymer layer is formed on the sidewalls of the spacer and an etched polymer layer is formed. In subsequent step S8, a first metal contact and a second metal contact are formed in the first contact opening and the second contact opening, respectively. The above steps will be described in detail in the following description.

[0025] Figures 2 to 5 Draw Figure 1 Cross-sectional views of different steps in the semiconductor structure formation process. Also refer to... Figure 1 and Figure 2 In step S1, a gate structure 120 is formed on a semiconductor substrate 110, wherein the semiconductor substrate 110 has a shallow trench isolation 112 and an insulating pad 114 and a conductor 116 in the shallow trench isolation 112. The conductor 116 is located below the insulating pad 114. In some embodiments, the semiconductor substrate 110 may include a silicon region 111 and a silicon oxide region, and the shallow trench isolation 112 may be located in the silicon oxide region. The silicon region 111 may be located on one side of the shallow trench isolation 112 (e.g., the left side of the shallow trench isolation 112). The conductor 116 may include a conductive material, such as polysilicon, tungsten, or a combination of the above materials. The gate structure 120 may include a first gate electrode 122, a gate dielectric 124, and a second gate electrode 126. The first gate electrode 122 may be a floating gate, and the second gate electrode 126 may be a control gate. The gate structure 120 may be a flash memory. The gate dielectric 124 is located between the first gate electrode 122 and the second gate electrode 126. A first gate electrode 122, a gate dielectric 124, and a second gate electrode 126 are sequentially stacked on a semiconductor substrate 110 from bottom to top. The gate dielectric 124 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any suitable method. The first gate electrode 122 and the second gate electrode 126 may be formed by CVD, physical vapor deposition (PVD), ALD, or other suitable methods.

[0026] In step S2, a sacrificial layer is formed on the gate structure 120. In step S3, an insulating layer 130 is formed on the semiconductor substrate 110, on the sidewall 121 of the gate structure 120, and on the sidewall of the sacrificial layer. The insulating layer 130 is a contact etch stop layer. In step S4, a spacer 140 is formed on the insulating layer 130, wherein the spacer 140 is located on the shallow trench isolation 112 of the semiconductor substrate 110 and on the sidewall 121 of the gate structure 120. Furthermore, the insulating layer 130 is located between the sidewall 121 of the gate structure 120 and the spacer 140. The sidewall 142 of the spacer 140 extends along the vertical direction D1. The sacrificial layer on the gate structure 120 can prevent damage to the gate structure 120 due to the etching step during the formation of the insulating layer 130 and the spacer 140. In step S5, an interlayer dielectric layer 150 is formed on the semiconductor substrate 110 and the spacer 140. In step S6, the sacrificial layer on the gate structure 120 is removed. In some embodiments, the method further includes forming a first dielectric layer 160 on the interlayer dielectric layer 150, the insulating layer 130, and the gate structure 120, and forming a second dielectric layer 170 on the first dielectric layer 160. In this way, a result is obtained as shown... Figure 2 The semiconductor structure 100a of the semi-finished product shown is illustrated.

[0027] In some embodiments, the insulating pad 114, insulating layer 130, and spacer 140 may include insulating materials, such as nitrides, low-k dielectric materials, or combinations thereof. The interlayer dielectric layer 150, first dielectric layer 160, and second dielectric layer 170 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, or combinations thereof. Furthermore, the interlayer dielectric layer 150 may be a spin-on dielectric layer, formed by spin-on coating.

[0028] Figure 3 A cross-sectional view of semiconductor structure 100b is shown when pulsed plasma P is on. (See also...) Figure 1 and Figure 3 After completing steps S1 to S6 Figure 2The semiconductor structure 100a then proceeds to step S7. In step S7, the interlayer dielectric layer 150, the insulating layer 130, and the semiconductor substrate 110 are etched with pulsed plasma P to form a first contact opening O1 and a second contact opening O2, and the sidewall 142 of the spacer 140 may be exposed from the first contact opening O1. Since the pulsed plasma P etches along the vertical direction D1, the first contact opening O1 and the second contact opening O2 are formed along the vertical direction D1. Furthermore, due to the different etching selectivity, the depth of the second contact opening O2 is greater than the depth of the first contact opening O1. In addition, the pulsed plasma P has the characteristic of an intermittent switching frequency. In some embodiments, the intermittent switching frequency of the pulsed plasma P may be 50%. During the formation of the first contact opening O1 and the second contact opening O2, the pulsed plasma P etches the first dielectric layer 160 and the second dielectric layer 170 to form a third contact opening O3. At least a portion of the top surface 123 of the gate structure 120 is exposed from the third contact opening O3.

[0029] Figure 4 A cross-sectional view of semiconductor structure 100c is shown when pulsed plasma P is off. (See also...) Figure 1 and Figure 4 In step S7, during pulsed plasma P etching, the etching gas can form a polymer layer 300 on the sidewall 142 of the spacer 140, but this polymer layer 300 can be further etched. For example, when the pulsed plasma P is off and the sidewall 142 of the spacer 140 is exposed from the first contact opening O1, the etching gas can react with the sidewall 142 of the spacer 140, thereby forming a polymer layer 300 on the sidewall 142 of the spacer 140. The polymer layer 300 extends in the vertical direction D1. The formed polymer layer 300 can serve as a buffer layer. When the pulsed plasma P is switched on, the polymer layer 300 can be etched by the pulsed plasma P in place of the sidewall 142 of the spacer 140, so that the spacer 140 can be protected from damage and provide sufficient protection for the gate structure 120 in subsequent processes.

[0030] The etching gas is kept constantly on during pulsed plasma P etching, regardless of whether pulsed plasma P is on or off. In some embodiments, the etching gas forming polymer layer 300 may be difluoromethane (CH2F2), and the flow rate of difluoromethane may be in the range of 25 sccm to 35 sccm. For example, the material of spacer 140 may include nitride, and sufficient flow rate (e.g., 30 sccm) of difluoromethane may form polymer layer 300 on the sidewall 142 of spacer 140 via carbon-nitrogen (CN) bonds or carbon-hydrogen (CH) bonds. Polymer layer 300 may be etched by pulsed plasma P in place of the sidewall 142 of spacer 140 after pulsed plasma P is switched on, thereby reducing the etching of sidewall 142 of spacer 140. Furthermore, difluoromethane has a high etching rate for bottom nitrides (e.g., insulating layer 130 and insulating pad 114) and oxides (e.g., shallow trench isolation 112 in semiconductor substrate 110), thus ensuring that pulsed plasma P is etched into the shallow trench isolation 112 of semiconductor substrate 110 to form the second contact opening O2. Since difluoromethane has a low etching rate for the gate second electrode 126 and conductor 116, it is less likely to etch the gate second electrode 126 and conductor 116.

[0031] After difluoromethane forms a polymer layer 300 on the sidewall 142 of the spacer 140, the pulsed plasma P can be switched on to continue forming the first contact opening O1, the second contact opening O2, and the third contact opening O3, while simultaneously etching the polymer layer 300 on the sidewall 142 of the spacer 140. Then, the pulsed plasma P is switched off again, and difluoromethane continues to form the polymer layer 300 on the sidewall 142 of the spacer 140. This cycle is repeated, allowing the pulsed plasma P to etch the polymer layer 300 instead of directly etching the sidewall 142 of the spacer 140. This reduces the likelihood of the sidewall 142 of the spacer 140 being etched, preventing damage to the spacer 140 and providing sufficient protection for the gate structure 120 in subsequent processes.

[0032] Next, please refer to Figure 1 and Figure 5In step S8, a first metal contact 510 and a second metal contact 520 are formed in the first contact opening O1 and the second contact opening O2, respectively. The first metal contact 510 and the second metal contact 520 are formed along the vertical direction D1. The first metal contact 510 is located in the interlayer dielectric layer 150 and the insulating layer 130. The first metal contact 510 can contact the sidewall 142 of the spacer 140. The second metal contact 520 is located in the shallow trench isolation 112, the insulating gasket 114, the insulating layer 130, and the interlayer dielectric layer 150. Furthermore, the top 118 of the conductor 116 is located in the second metal contact 520. The height h2 of the second metal contact 520 is greater than the height h1 of the first metal contact 510. In some embodiments, a third metal contact 530 is formed in the third contact opening O3 during the formation of the first metal contact 510 and the second metal contact 520. The third metal contact 530 is formed along the vertical direction D1. The third metal contact 530 is located on the gate structure 120 and within the first dielectric layer 160 and the second dielectric layer 170. In this way, the following can be obtained: Figure 5 The semiconductor structure 100 shown is shown.

[0033] In summary, due to the intermittent switching frequency of pulsed plasma, when pulsed plasma is on, it can concentrate on etching downwards the interlayer dielectric layer, insulating layer, and semiconductor substrate. When pulsed plasma is off, it can reduce collisions with the interlayer dielectric layer on the semiconductor substrate in the first contact opening, thereby reducing lateral etching. This reduces the sidewalls of the spacers in the interlayer dielectric layer caused by pulsed plasma lateral etching, preventing damage to the spacers and providing sufficient protection for the gate structure in subsequent processes. Furthermore, during pulsed plasma etching of the interlayer dielectric layer, insulating layer, and semiconductor substrate, in addition to forming a polymer layer on the sidewalls of the spacers, it also ensures that the pulsed plasma can etch shallow trench isolation in the semiconductor substrate to form the second contact opening. The polymer layer formed on the sidewalls of the spacers can serve as a protective layer for the spacers. The polymer layer can act as a buffer layer, replacing the sidewalls of the spacers being etched by the pulsed plasma. In this way, the spacers can be prevented from being damaged, providing sufficient protection for the gate structure in subsequent processes.

[0034] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the embodiments of the invention. Those skilled in the art will understand that they can readily use the invention as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, characterized in that, Include: Semiconductor substrate having shallow trench isolation; An insulating pad is located in the shallow trench isolation of the semiconductor substrate; A gate structure is located on the shallow trench isolation of the semiconductor substrate; Spacers are located on the shallow trench isolation and on the sidewall of the gate structure; An insulating layer is located on the semiconductor substrate and between the sidewall of the gate structure and the spacer; An interlayer dielectric layer is located on the semiconductor substrate and the spacer, wherein during the etching of the interlayer dielectric layer, the insulating layer and the semiconductor substrate by pulsed plasma etching, a polymer layer is formed on the sidewall of the spacer and the polymer layer is etched. A first metal contact is located in the interlayer dielectric layer and the insulating layer, wherein the first metal contact contacts the sidewall of the spacer, and the sidewall of the spacer extends in a vertical direction; as well as The second metal contact is located in the shallow trench isolation, the insulating gasket, the insulating layer, and the interlayer dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The height of the second metal contact is greater than the height of the first metal contact.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: The conductor is located in the shallow trench isolation and below the insulating pad, with the top of the conductor located in the second metal contact.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: The first dielectric layer is located on the interlayer dielectric layer and the gate structure.

5. The semiconductor structure as described in claim 4, characterized in that, Also includes: The second dielectric layer is located on the first dielectric layer.

6. The semiconductor structure as described in claim 5, characterized in that, Also includes: A third metal contact is located on the gate structure and within the first dielectric layer and the second dielectric layer.

7. A method for forming a semiconductor structure, characterized in that, Include: A gate structure is formed on a semiconductor substrate, wherein the semiconductor substrate has shallow trench isolation and an insulating pad and a conductor in the shallow trench isolation; A sacrificial layer is formed on the gate structure; An insulating layer is formed on the semiconductor substrate, on the sidewall of the gate structure, and on the sidewall of the sacrificial layer; A spacer is formed on the insulating layer, wherein the spacer is located on the shallow trench isolation and on the sidewall of the gate structure; An interlayer dielectric layer is formed on the semiconductor substrate and on the spacer; Remove the sacrificial layer; The interlayer dielectric layer, the insulating layer, and the semiconductor substrate are etched by pulsed plasma to form a first contact opening and a second contact opening, wherein the sidewall of the spacer is exposed from the first contact opening, and during etching, a polymer layer is formed on the sidewall of the spacer and the polymer layer is etched. as well as A first metal contact and a second metal contact are formed in the first contact opening and the second contact opening, respectively.

8. The method as described in claim 7, characterized in that, The polymer layer is formed using difluoromethane, with a flow rate in the range of 25 sccm to 35 sccm, and the switching frequency of the pulsed plasma is 50%.

9. The method as described in claim 7, characterized in that, Also includes: A first dielectric layer is formed on the interlayer dielectric layer, the insulating layer, and the gate structure; and A second dielectric layer is formed on the first dielectric layer.

10. The method as described in claim 9, characterized in that, Also includes: During the formation of the first contact opening and the second contact opening, the first dielectric layer and the second dielectric layer are etched to form a third contact opening, wherein at least a portion of the top surface of the gate structure is exposed from the third contact opening; as well as During the formation of the first metal contact and the second metal contact, a third metal contact is formed in the third contact opening.

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