Dual dielectric layer field effect transistor and method of making the same
By employing a dual dielectric layer structure combining low-k and high-k dielectric layers in the field-effect transistor, the balance between mobility and operating voltage is solved, achieving improved performance of the field-effect transistor with high mobility and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2022-04-15
- Publication Date
- 2026-06-26
AI Technical Summary
In existing technologies, low-k dielectric layers improve mobility but increase power consumption, while high-k dielectric layers reduce operating voltage but affect carrier transport. It is difficult to form low-energy disorder at the semiconductor-dielectric layer interface, which limits device performance.
A double dielectric layer structure is adopted, combining a low-k dielectric layer and a high-k dielectric layer. The low-k dielectric layer is a polystyrene solution coated on the semiconductor layer, and the high-k dielectric layer is formed by atomic layer deposition to form an aluminum oxide layer, thus forming a field-effect transistor with a top-gate bottom contact structure.
It achieves a balance between high mobility and low operating voltage, reduces device power consumption, and improves device performance, especially in the 10-20 mg/mL polystyrene concentration range.
Smart Images
Figure CN115000301B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic materials and devices, specifically to a double-dielectric-layer field-effect transistor and its fabrication method. Background Technology
[0002] With the development of technology and the improvement of semiconductor manufacturing processes, the integration of semiconductor chips is increasing day by day, and the market's performance requirements for semiconductor devices are constantly increasing. How to improve device performance and reduce device power consumption has become an important problem that the electronics industry urgently needs to solve.
[0003] In recent years, with continuous research into transport mechanisms, engineers have discovered that the performance of field-effect transistors (FETs) is closely related to many factors, including gate voltage, semiconductor layer, source / drain electrodes, device structure, temperature, and external radiation. Among the performance parameters of organic field-effect transistors, mobility is of paramount importance. In a sense, under the same conditions, higher mobility represents a higher degree of device performance.
[0004] Chinese patent CN 102110776 B discloses a high-performance organic field-effect transistor and its fabrication method. It effectively controls and optimizes the morphology of the semiconductor layer by using a dielectric modification layer of a polystyrene and polyphenylene ether blend polymer, forming a crystalline film with varying grain sizes and texture, making the semiconductor layer smoother and thus improving the carrier transport performance of the organic semiconductor layer. However, as is known to those skilled in the art, both polystyrene and polyphenylene ether are low-k dielectric materials. While they can improve mobility, the operating voltage is a significant concern. If the operating voltage cannot be synchronously controlled, substantial power consumption will result, which is detrimental to the widespread application of field-effect transistors.
[0005] Currently, the most commonly used dielectric layers in organic thin-film transistors (TFTs) are of two types: low-k dielectric layers and high-k dielectric layers. While low-k dielectric layers can improve mobility, those skilled in the art know that higher operating voltages increase device power consumption. High-k dielectric layers can reduce operating voltage, but solely using high-k dielectric materials as the dielectric layer can cause significant energy disorder and density of states expansion at the semiconductor-dielectric interface, greatly affecting carrier transport and severely limiting device performance. Although capacitance can be increased by reducing thickness, the resulting leakage current cannot be ignored.
[0006] Therefore, if the advantages and disadvantages of low-k and high-k materials can be balanced so that the two materials work together, it is expected that polymer field-effect transistor materials with superior performance can be prepared, providing new ideas for the field of electronic materials and device fabrication. Summary of the Invention
[0007] The purpose of this invention is to solve the problems existing in the prior art and provide a double dielectric layer field-effect transistor and its fabrication method, which combines the advantages of low-k and high-k materials, so that the fabricated field-effect transistor not only has a high mobility but also effectively reduces the operating voltage.
[0008] The technical solution disclosed in this invention is as follows: a double dielectric layer field-effect transistor, which has a top-gate bottom contact structure, and from bottom to top includes a glass substrate, source and drain electrodes, a semiconductor layer, a dielectric layer and a gate. The dielectric layer includes a low-k dielectric layer in contact with the semiconductor layer below and a high-k dielectric layer above it. The low-k dielectric layer is formed by coating a low-k dielectric layer solution onto the semiconductor layer. The low-k dielectric layer solution is prepared by dissolving a low-k polymer polystyrene (Mw=35000, abbreviated as PS) in an organic solvent, and the concentration of polystyrene is 5-20 mg / mL.
[0009] Furthermore, the semiconductor layer material is prepared by dissolving a polymer of 1,4-dioxopyrrole and thiophene, DPPT-TT (Mw > 100 K, PDI < 3.0), in a high-boiling-point organic solvent. The structural formula of DPPT-TT is as follows:
[0010]
[0011] Preferably, the concentration of polystyrene in the low-k dielectric layer solution is 10-20 mg / mL.
[0012] The fabrication method of the above-mentioned double-dielectric-layer field-effect transistor is as follows:
[0013] (1) Solution preparation
[0014] DPPT-TT was dissolved in a high-boiling-point organic solvent to prepare a semiconductor solution;
[0015] Polystyrene was dissolved in an organic solvent to prepare a low-k dielectric layer solution;
[0016] The prepared semiconductor solution and low-k dielectric layer solution are dissolved by heating and set aside for later use.
[0017] (2) Substrate pretreatment: Clean the substrate and dry it;
[0018] (3) Fabrication of source and drain electrodes: A nickel layer and a gold layer are deposited on the substrate as source and drain electrodes. The nickel layer is in direct contact with the substrate, and the gold layer is on top of the nickel layer.
[0019] (4) Preparation of semiconductor layer thin film: Spin-coat the semiconductor solution prepared in step (1) onto the substrate of the pre-made active drain electrode, and anneal the solution to form a semiconductor layer thin film.
[0020] (5) Preparation of low-k dielectric layer: spin-coat the low-k dielectric layer solution prepared in step (1) onto the semiconductor thin film and anneal it to form a low-k dielectric layer;
[0021] (6) Preparation of high-k dielectric layer: Aluminum oxide layer is deposited on top of low-k dielectric layer as high-k dielectric layer using atomic layer deposition (ALD) technology;
[0022] (7) Gate fabrication: An aluminum layer is deposited on a high-k dielectric layer as the gate electrode.
[0023] Further, in step (1), the high-boiling-point organic solvent for dissolving DPPT-TT is dichlorobenzene, and the concentration of DPPT-TT is 7 mg / mL; the organic solvent for dissolving polystyrene is butyl acetate.
[0024] Furthermore, the nickel layer prepared in step (3) has a thickness of 4-5 nm and the gold layer has a thickness of 20-40 nm.
[0025] Furthermore, in step (4), when preparing the semiconductor thin film, the spin coating process is to first coat the film at a speed of 500 rpm for 5 seconds, and then coat it at a speed of 1000 rpm for 60 seconds to complete the process; the annealing process is carried out in an inert protective gas environment, with an annealing temperature of 250°C and an annealing time of 30 min. This process can ensure that the obtained semiconductor thin film has a uniform thickness.
[0026] Furthermore, in step (5), when preparing the low-k dielectric layer, the spin coating process is to first spin coat the material at a speed of 500 rpm for 5 seconds, and then spin coat the material at a speed of 2000 rpm for 60 seconds to complete the process; the annealing temperature is 80℃ and the annealing time is 2 hours. This process can ensure that the film is flat and dense.
[0027] Furthermore, the thickness of the high-k dielectric layer prepared in step (6) is 40 nm.
[0028] Furthermore, the thickness of the aluminum layer deposited in step (7) is 80-100 nm.
[0029] The beneficial effects of this invention are as follows:
[0030] 1. The field-effect transistor disclosed in this application uses a double dielectric layer structure to improve the performance of DA polymer (DPPT-TT) field-effect transistors. The two materials work synergistically to greatly reduce the operating voltage of DA polymer transistors while achieving high mobility, thus significantly improving device performance.
[0031] 2. This application uses the low trapping and low energy disorder characteristics of low-k polymer polystyrene to suppress the energy disorder caused by polarons in the high-k dielectric layer, thereby improving charge transport at the semiconductor-dielectric layer interface. The low-k dielectric layer placed between the high-k dielectric layer and the semiconductor layer can also enable the dielectric layer and the semiconductor layer to form a low-energy disorder interface contact. The presence of high-k oxide provides high capacitance, which can reduce the device operating voltage.
[0032] 3. By limiting the concentration of the low-k polymer PS to the range of 10-20 mg / mL, the device performance parameters are configured to be optimal. Under these conditions, the field-effect transistors prepared can achieve better performance in terms of threshold voltage, mobility, and on / off ratio. Attached Figure Description
[0033] Figure 1 These are schematic diagrams of the double-dielectric-layer field-effect transistors prepared in Examples 1-3;
[0034] Figure 2 This is a schematic diagram of the structure of the single-dielectric-layer field-effect transistor fabricated in Comparative Example 1;
[0035] Figure 3 This is a statistical graph showing the average threshold voltage of field-effect transistors under different PS concentrations;
[0036] Figure 4 This is a statistical chart of the average mobility of field-effect transistors under different PS concentrations;
[0037] Figure 5 This is a statistical chart of the average capacitance per unit area of field-effect transistors under different PS concentrations;
[0038] Figure 6 This is a statistical chart of the average on / off ratio of field-effect transistors under different PS concentrations;
[0039] Among them, 1-glass substrate, 2-source, 3-drain, 4-semiconductor layer, 5-low-k dielectric layer, 6-high-k dielectric layer, and 7-gate. Detailed Implementation
[0040] The following embodiments further illustrate the content of the present invention, but should not be construed as limiting the present invention. Any modifications and substitutions made to the methods, steps, or conditions of the present invention without departing from the essence of the invention are within the scope of the present invention.
[0041] Example 1: Fabrication of a double-dielectric-layer field-effect transistor
[0042] The field-effect transistor fabricated in this embodiment has a top-gate bottom-contact structure, including a glass substrate, source / drain electrodes, a semiconductor layer, a low-k dielectric layer, a high-k dielectric layer, and a gate. The fabrication sequence is from bottom to top (from glass substrate to gate). The glass substrate is a glass sheet; the source / drain electrodes are fabricated by vacuum evaporation (nickel and gold); the semiconductor layer is fabricated by spin coating; the low-k dielectric layer is formed by spin coating using a low-k polymer material PS; the high-k dielectric layer is an aluminum oxide layer fabricated by atomic layer deposition; and the gate is fabricated by vacuum evaporation (aluminum).
[0043] The specific preparation process is as follows:
[0044] (1) Preparation of semiconductor solution: The polymer DPPT-TT of 1,4-dioxodipyrrole and thiophene was prepared with dichlorobenzene at a mass-volume ratio of 7 mg / mL.
[0045] Preparation of low-k dielectric layer solution: Low-k polymer material polystyrene (PS, Mw = 35000) and butyl acetate (NBA) were prepared at a mass-volume ratio of 5 mg / mL;
[0046] Dissolution of the solution: Place the prepared semiconductor solution and low-k dielectric layer solution on a heating stage at 80°C and let them stand for 24 hours to dissolve. After dissolution, set aside for use.
[0047] (2) Substrate cleaning: Select a glass slide with a size of about 1.5cm×1.5cm as the substrate, and clean it with deionized water and ethanol for 5 minutes each, and clean it twice for a total of four times. Then dry it with a nitrogen gun.
[0048] (3) Fabrication of source and drain electrodes: A nickel layer with a channel length of 100 μm and a gold layer with a width of 1200 μm was deposited on the substrate using a stainless steel mask in a vacuum thermal evaporation method as the source and drain electrodes. The thickness of the nickel layer was 5 nm and the thickness of the gold layer was 20 nm. The nickel layer was in direct contact with the substrate and the gold layer was on top of the nickel layer.
[0049] (4) Preparation of semiconductor thin film: The semiconductor solution prepared in step (1) is spread on the substrate surface by pipetting. First, the coating is homogenized at 500 rpm for 5 seconds, and then homogenized at 1000 rpm for 60 seconds. After spin coating, the sample is placed on a heating plate at 250°C and heated and annealed in pure nitrogen for 30 minutes to ensure that the semiconductor thin film is uniform in thickness.
[0050] (5) Preparation of low-k dielectric layer: The low-k dielectric layer solution prepared in step (1) is spread on the surface of the semiconductor film by a pipette. First, the film is homogenized at 500 rpm for 5 seconds, and then homogenized at 2000 rpm for 60 seconds. After spin coating, the sample is heated and annealed at 80°C for 2 hours to ensure that the film is flat and dense.
[0051] (6) Preparation of high-k dielectric layer: The prepared sample is placed in the atomic layer deposition cavity, and an aluminum oxide layer with a thickness of 40 nm is prepared on the low-k dielectric layer as a high-k dielectric layer using atomic layer deposition technology (ALD technology).
[0052] (7) Gate fabrication: A 100 nm thick aluminum electrode was deposited on a high-k dielectric layer using a stainless steel mask by vacuum thermal evaporation.
[0053] Example 2: Fabrication of a double-dielectric-layer field-effect transistor
[0054] The only difference between Example 2 and Example 1 is that in step (1), the low-k dielectric layer solution is prepared by mixing low-k polymer material polystyrene and butyl acetate at a mass-volume ratio of 10 mg / mL and then using it for subsequent experiments. The other materials and preparation process are the same as in Example 1.
[0055] Example 3: Fabrication of a double-dielectric-layer field-effect transistor
[0056] The only difference between Example 3 and Example 1 is that in step (1), the low-k dielectric layer solution is prepared by mixing low-k polymer material polystyrene and butyl acetate at a mass-volume ratio of 20 mg / mL and then using it for subsequent experiments. The other materials and preparation process are the same as in Example 1.
[0057] Comparative Example 1: Fabrication of a single-dielectric-layer field-effect transistor
[0058] The field-effect transistor structure prepared in this comparative example differs from the field-effect transistor prepared in Example 1 in that it has only one low-k polymer layer as the dielectric layer.
[0059] The specific preparation process is as follows:
[0060] (1) Preparation of semiconductor solution: DPPT-TT and dichlorobenzene were prepared at a mass-volume ratio of 7 mg / mL;
[0061] Preparation of low-k dielectric layer solution: Polystyrene and butyl acetate, low-k polymer materials, are prepared at a mass-volume ratio of 60 mg / mL.
[0062] Dissolution of the solution: Place the prepared semiconductor solution and low-k dielectric layer solution on a heating stage at 80°C and let them stand for 24 hours to dissolve. After dissolution, set aside for use.
[0063] (2) Substrate cleaning: Select a glass slide with a size of about 1.5cm×1.5cm as the substrate, and clean it with deionized water and ethanol for 5 minutes each, and clean it twice for a total of four times. Then dry it with a nitrogen gun.
[0064] (3) Fabrication of source and drain electrodes: Nickel and gold with a channel length of 100 μm and a width of 1200 μm were deposited on the substrate by vacuum thermal evaporation using a stainless steel mask as source and drain electrodes. The thickness of nickel was 5 nm and the thickness of gold was 20 nm. Nickel was in direct contact with the substrate and gold was on top of nickel.
[0065] (4) Preparation of semiconductor thin film: The semiconductor solution prepared in step (1) is spread on the substrate surface by pipetting. First, the coating is homogenized at 500 rpm for 5 seconds, and then homogenized at 1000 rpm for 60 seconds. After spin coating, the sample is placed on a heating plate at 250°C and heated and annealed in pure nitrogen for 30 minutes to ensure that the semiconductor thin film is uniform in thickness.
[0066] (5) Preparation of low-k dielectric layer: The low-k dielectric layer solution prepared in step (1) is spread on the surface of the semiconductor film by a pipette. First, the film is homogenized at 500 rpm for 5 seconds, and then homogenized at 2000 rpm for 60 seconds. After spin coating, the sample is heated and annealed at 80°C for 2 hours to ensure that the film is flat and dense.
[0067] (6) Gate fabrication: A 100 nm thick aluminum electrode was deposited on a high-k dielectric layer using a stainless steel mask by vacuum thermal evaporation.
[0068] Related performance tests
[0069] contrast Figure 3 , Figure 4 , Figure 5 and Figure 6It is observed that the threshold voltage decreases with decreasing PS concentration in the low-k dielectric layer (from 20 mg / mL to 5 mg / mL). Note that the threshold voltage at 5 mg / mL PS concentration is higher than that at 10 mg / mL PS concentration. This is because at 5 mg / mL PS concentration, the dielectric layer formed during spin coating at 2000 rpm is extremely thin, and the semiconductor layer surface has a certain degree of roughness, thus suppressing dielectric properties to some extent, thereby affecting the threshold voltage. At PS concentrations of 10 mg / mL and 20 mg / mL, a significant reduction in the threshold voltage at 10 mg / mL is observed, while at 20 mg / mL, the mobility increases rapidly, even exceeding the mobility of the control group with a single dielectric layer and a PS concentration of 60 mg / mL. Therefore, within the range of 10 mg / mL to 20 mg / mL, there exists a parameter configuration with a low threshold voltage and high mobility, exhibiting excellent overall performance. The corresponding capacitance per unit area also conforms to the rule that capacitance decreases with increasing PS concentration. After comprehensive consideration, it was concluded that the optimal parameter configuration for device performance exists within the PS concentration range of 10 mg / mL and 20 mg / mL. The polymer field-effect transistors fabricated using this method achieve optimal threshold voltage, mobility, and on / off ratio.
[0070] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. However, the above description is merely a specific embodiment of the present invention, and the technical features of the present invention are not limited thereto. Any other embodiments derived by those skilled in the art without departing from the technical solution of the present invention should be covered within the patent scope of the present invention.
Claims
1. A double-dielectric-layer field-effect transistor, having a top-gate-bottom-contact structure, comprising, from bottom to top, a glass substrate, source / drain electrodes, a semiconductor layer, a dielectric layer, and a gate, characterized in that, The dielectric layer includes a low-k dielectric layer that is in contact with the semiconductor layer below and a high-k dielectric layer located above it; A low-k dielectric layer is formed by coating a low-k dielectric solution onto a semiconductor layer; The low-k dielectric layer solution is prepared by dissolving low-k polymer polystyrene in an organic solvent, with a polystyrene concentration of 10-20 mg / mL; The high-k dielectric layer is an aluminum oxide thin film layer; The semiconductor layer material is prepared by dissolving the polymer DPPT-TT of 1,4-dioxodipyrrole and thiophene in a high-boiling-point organic solvent. The structural formula of DPPT-TT is as follows: 。 2. The method for fabricating a double-dielectric-layer field-effect transistor as described in claim 1, characterized in that, Specifically, the steps include the following: (1) Solution preparation A semiconductor solution was prepared by dissolving DPPT-TT in a high-boiling-point organic solvent, with a concentration of 7 mg / mL. Polystyrene was dissolved in an organic solvent to prepare a low-k dielectric layer solution; The prepared semiconductor solution and low-k dielectric layer solution are dissolved by heating and set aside for later use. (2) Substrate pretreatment: Clean the substrate and dry it; (3) Fabrication of source and drain electrodes: A nickel layer and a gold layer are deposited on the substrate as source and drain electrodes. The nickel layer is in direct contact with the substrate, and the gold layer is on top of the nickel layer. (4) Preparation of semiconductor thin film: The semiconductor solution prepared in step (1) is spin-coated onto the substrate of the pre-fabricated active drain electrode. The spin-coating process is to first spin coat at a speed of 500 rpm for 5 seconds, and then spin coat at a speed of 1000 rpm for 60 seconds to complete the process. The semiconductor thin film is formed by annealing. The annealing process is carried out in an inert protective gas environment. The annealing temperature is 250℃ and the annealing time is 30 min. (5) Preparation of low-k dielectric layer: The low-k dielectric layer solution prepared in step (1) is spin-coated onto the semiconductor thin film. The spin-coating process is to first spin coat at a speed of 500 rpm for 5 seconds, and then spin coat at a speed of 2000 rpm for 60 seconds to complete the process. The low-k dielectric layer is formed by annealing at a temperature of 80°C for 2 hours. (6) Preparation of high-k dielectric layer: Aluminum oxide thin film is deposited on top of low-k dielectric layer as high-k dielectric layer using atomic layer deposition technology; (7) Gate fabrication: An aluminum layer is deposited on a high-k dielectric layer as the gate electrode.
3. The method for fabricating a double-dielectric-layer field-effect transistor as described in claim 2, characterized in that, In step (1), the high-boiling-point organic solvent for dissolving DPPT-TT is dichlorobenzene, and the organic solvent for dissolving polystyrene is butyl acetate.
4. The method for fabricating a double-dielectric-layer field-effect transistor as described in claim 2, characterized in that, The nickel layer prepared in step (3) has a thickness of 4-5 nm and the gold layer has a thickness of 20-40 nm.
5. The method for fabricating a double-dielectric-layer field-effect transistor as described in claim 2, characterized in that, The thickness of the high-k dielectric layer prepared in step (6) is 40 nm.
6. The method for fabricating a double-dielectric-layer field-effect transistor as described in claim 2, characterized in that, The thickness of the aluminum layer deposited in step (7) is 80-100 nm.