A kind of arc function generator and crystal oscillator

Abstract

The present invention provides an arc function generator and a crystal oscillator, comprising: an arc function generating circuit, an arc function adjusting circuit and a linear function generating and adjusting circuit; the arc function generating circuit is used to generate an arc signal, the arc function adjusting circuit is used to adjust the size and direction of the arc signal, the linear function generating and adjusting circuit is used to generate a linear signal and adjust the size and direction of the linear signal, the adjusted linear signal is added to the adjusted arc signal and output; the arc function generator is suitable for temperature compensation of a constant temperature crystal oscillator to solve the problem that a cubic function voltage is not suitable for temperature compensation of a constant temperature crystal oscillator.

Description

Technical Field

[0001] The invention relates to the technical field of crystal oscillators, and in particular to an arc function generator and a crystal oscillator suitable for temperature compensation of a constant temperature crystal oscillator. Background Art

[0002] With the rapid development of high-speed wired digital communication systems, the wired transmission rate needs to be continuously improved, and at the same time, higher requirements are placed on the system bit error rate. This places higher requirements on the quality of the reference clock of the communication system. The crystal oscillator can generate a clock signal with high frequency stability, so for the communication system, the signal generated by the crystal oscillator is generally selected as the reference clock of the system. Compared with other types of crystal oscillators, the constant temperature crystal oscillator has a higher output frequency stability, but the constant temperature bath temperature of the constant temperature crystal oscillator is not absolutely constant, but has a small temperature fluctuation with the change of ambient temperature. In this temperature dynamic fluctuation range of about a few degrees Celsius, the crystal oscillator frequency and temperature roughly present a semi-arc relationship. It is necessary to perform temperature compensation on the crystal frequency in this small temperature fluctuation range of the constant temperature bath, so as to further improve the stability of the output frequency of the constant temperature crystal oscillator.

[0003] Since the resonant frequency of a quartz crystal changes with ambient temperature in a cubic function relationship, a temperature-compensated crystal oscillator usually generates a voltage that changes with temperature in a cubic function relationship. This voltage is combined with a varactor to compensate for frequency changes in the form of a voltage-controlled crystal oscillator. However, since the temperature fluctuation range in the constant temperature bath is very small when the constant temperature crystal oscillator is working stably, the crystal frequency changes with the temperature in the constant temperature bath in an approximately quadratic function relationship or a semi-arc relationship. At this time, the cubic function voltage of the temperature-compensated crystal oscillator is no longer suitable for temperature compensation of the constant temperature crystal oscillator. At the same time, the cubic voltage function generation circuit brings huge area and power consumption overhead, and increases the complexity of circuit design.

[0004] According to the above, how to design an approximate quadratic function generator or an arc function generator to provide a temperature compensation technology for a constant temperature crystal oscillator is a problem that those skilled in the art currently need to solve. Summary of the invention

[0005] The purpose of the present invention is to design an arc function generator and a crystal oscillator. The arc function generator is suitable for temperature compensation of a constant temperature crystal oscillator to solve the problem that the cubic function voltage mentioned in the background technology is not suitable for temperature compensation of a constant temperature crystal oscillator.

[0006] The present invention is achieved through the following technical solutions:

[0007] An arc function generator comprises: an arc function generating circuit, an arc function adjusting circuit and a linear function generating and adjusting circuit; the arc function generating circuit is used to generate an arc signal, the arc function adjusting circuit is used to adjust the size and direction of the arc signal, the linear function generating and adjusting circuit is used to generate a linear signal and adjust the size and direction of the linear signal, and the adjusted linear signal is added to the adjusted arc signal for output;

[0008] The arc function generating circuit comprises: PMOS transistors MP0, MP1, MP2 and MP3, and NMOS transistors MN0, MN1 and MN2;

[0009] The drain of MP0 is connected to the gate of MN0, the drain of MN0, the gate of MN1 and the drain of MP2; the drain of MP1 is connected to the drain of MN1, the drain of MN2, the gate of MN2 and the drain of MP3; the gate of MP1 is connected to the gate of MP2, the source of MP0 is connected to the source of MP1, the source of MP2 is connected to the source of MP3, the source of MN0 is connected to the source of MN1 and the source of MN2, and the gate of MP0 is connected to the input reference signal V REFH , MP3 gate terminal input reference signal V REFL .

[0010] Preferably, the arc function adjustment circuit comprises: PMOS transistors MP10, MP11, MP12 and MP13, and NMOS transistors MN3 and MN4;

[0011] The gate terminal of MP10 is connected to the drain terminal of MP10, the gate terminal of MP11 and the source terminal of MP12, the drain terminal of MP11 is connected to the source terminal of MP13, the drain terminal of MP12 is connected to the drain terminal of MN3 and the source terminal of MN4, the drain terminal of MP13 is connected to the drain terminal of MN4, the gate terminal of MN3 is connected to the gate terminal of MN2, the source terminal of MN3 is connected to the source terminal of MN0, and the gate terminals of MP12, MP13 and MN4 are connected to the input voltage signal DIR0.

[0012] Furthermore, a resistor R1 is included, one end of the resistor R1 is connected to the source end of MN0, and the other end of the resistor R1 is connected to the drain end of MP13.

[0013] Preferably, the linear function generation and adjustment circuit comprises: PMOS transistors MP4, MP14, MP15, MP16, MP17 and MP18, and NMOS transistors MN5, MN6 and MN7;

[0014] The gate terminal of MP4 is connected to the drain terminal of MP4 and the gate terminal of MP14, the gate terminal of MN5 is connected to the drain terminal of MN5, the gate terminal of MN6 and the drain terminal of MP14, the drain terminal of MN6 is connected to the drain terminal of MP17 and the source terminal of MN7, the gate terminal of MP15 is connected to the drain terminal of MP15, the gate terminal of MP16 and the source terminal of MP17, the drain terminal of MP16 is connected to the source terminal of MP18, the drain terminal of MP18 is connected to the drain terminal of MN7, the source terminal of MN5 and the source terminal of MN6 are both connected to the source terminal of MN0, the gate terminal of MP17, the gate terminal of MP18 and the gate terminal of MN7 are connected to the input voltage signal DIR1, and the gate terminal of MP4 is connected to the input current signal I IN .

[0015] Furthermore, the arc function generating circuit also includes an input current-voltage conversion circuit, which is used to convert the input current into a voltage and output the voltage to the arc function generating circuit.

[0016] Furthermore, the input current-voltage conversion circuit includes a PMOS transistor MP8 and a resistor R0; the drain terminal of MP8 is connected to the gates of MP1 and MP2 and one end of the resistor R0; the gate terminal of MP8 is connected to the gate terminal of MP4, and the other end of the resistor R0 is connected to the source terminal of MN0.

[0017] Preferably, the arc function generating circuit further comprises a constant current source, which provides a current source for MP0, MP1, MP2, MP3, MN0, MN1 and MN2.

[0018] Further, the constant current source includes PMOS transistors MP5, MP6, MP7 and MP9;

[0019] The gate terminal of MP5 is connected to the drain terminal of MP5 and is connected to the gate terminal of MP6, the gate terminal of MP7, the gate terminal of MP9 and the source terminal of MN0. The drain terminal of MP6 is connected to the drain terminal of MN0. The drain terminal of MP7 is connected to the source terminals of MP0 and MP1. The drain terminal of MP9 is connected to the source terminals of MP2 and MP3. The gate terminal of MP5 is connected to the input reference current I REF .

[0020] A crystal oscillator, characterized by comprising the arc function generator.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The arc function generating circuit of the present invention comprises PMOS transistors MP0, MP1, MP2 and MP3, NMOS transistors MN0, MN1 and MN2; the input voltage signal range is V REFL <V IN <V REFH , when V IN With V REFH When the difference is large, the difference between the leakage current of MP1 and MP0, I1, is proportional to V INApproximately a quadratic function relationship, when V IN From V REFL Change to V REFH The sum of the difference between the leakage currents of MP1 and MP0 I1, the difference between the leakage currents of MP2 and MP3 I2 and V IN It presents an arc relationship with an opening downward, which means that the sum of I1 and I2 is equal to I IN The arc function generator of the present invention has the advantages of simple circuit structure, low power consumption and small area. Compared with the traditional function generator, it can obtain arc families with various concave-convex shapes and slope directions and has a simpler circuit structure, which greatly simplifies the complexity of the design and improves the reliability of the circuit, and can meet various application requirements for arc functions.

[0023] Furthermore, a resistor R1 is provided to convert the voltage signal finally generated into a current signal for output.

[0024] Furthermore, the present invention provides an input current-voltage conversion circuit, so that current can be used as an input signal, and the current is converted into a voltage and then output to the arc function generating circuit.

[0025] Furthermore, the present invention provides a constant current source for adjusting the constant term of the function generator.

[0026] The invention comprises a crystal oscillator of an arc function generator and can utilize the arc function generator to perform accurate temperature compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Attached Figure 1 The circuit structure diagram of the arc function generator in the present invention is shown in FIG.

[0029] Attached Figure 2 For the embodiment of the present invention, when V IN From V REFL Change to V REFH The corresponding branch current;

[0030] Attached Figure 3 For the embodiment of the present invention, when VIN From V REFL Change to V REFH Corresponding to I1 and I2 currents;

[0031] Attached Figure 4 The sum of I1 and I2 in the embodiment of the present invention is subtracted by the current mirror. MP6 The final current flows through MN2;

[0032] Attached Figure 5 Schematic diagram of input and output of an arc function generator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to further understand the present invention, the present invention is described below in conjunction with embodiments. These descriptions are only to further explain the features and advantages of the present invention and are not intended to limit the claims of the present invention.

[0034] The most notable feature of the present invention is that an approximate arc function generator is designed, which no longer uses the temperature simulation compensation network of the existing crystal oscillator. The network is realized by generating a high-order Chebyshev temperature function or a cubic function. The compensation method is applicable to temperature compensation within the full temperature range of the temperature-compensated crystal oscillator, but is not applicable to temperature compensation of the constant temperature crystal oscillator, and the circuit implementation is complex and the area and power consumption are large. The function generator designed by the present invention no longer directly uses the compensation method of the temperature-compensated crystal oscillator, but designs an arc function generator that can meet the compensation requirements of the constant temperature crystal oscillator, thereby significantly reducing the complexity of the circuit design and saving the power consumption, area, cost, etc. of the circuit.

[0035] See also Figure 1 The arc function generator described in the present invention includes an arc function generating and adjusting circuit and a linear function generating and adjusting circuit.

[0036] The arc function generation and adjustment circuit includes PMOS transistors MP0, MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, NMOS transistors MN0, MN1, MN2, MN3, MN4, resistor R0, input reference voltage V REFH 、V REFL , input reference current I REF , input current signal I IN , input node voltage signals DIR0 and DIR1. MP5, MP6, MP7, and MP9 form a current mirror, and the gate terminal of MP5 is connected to the drain terminal and is connected to the input reference current I REF, and connected to the gate terminals of MP6, MP7, and MP9. The drain terminal of MP6 is connected to the drain terminal and gate terminal of MN0. The drain terminal of MP7 is connected to the source terminals of MP0 and MP1. The drain terminal of MP9 is connected to the source terminals of MP2 and MP3. MP4, MP8, and MP14 form a current mirror. The gate terminal and drain terminal of MP4 are connected and the input current signal I is connected. IN The drain of MP0 is connected to the gate of MN0, MN0, MN1 and MP2, and the drain of MP1 is connected to the drain of MN1, MN2, MN2, MP3 and MN3. The gate of MP0 is connected to the input reference signal V REFH , MP3 gate terminal input reference signal V REFL MP10 and MP11 form a current mirror, the gate terminal of MP10 is connected to the drain terminal and connected to the gate terminal of MP11 and the source terminal of MP12, the drain terminal of MP11 is connected to the source terminal of MP13, the drain terminal of MP12 is connected to the drain terminal of MN3 and the source terminal of MN4, the drain terminal of MP13 is connected to the drain terminal of MN4, and the input voltage signal DIR0 is connected to the gate terminal of MP12, the gate terminal of MP13, and the gate terminal of MN4.

[0037] The linear function generation and adjustment circuit comprises PMOS transistors MP14, MP15, MP16, MP17, MP18, and NMOS transistors MN5, MN6, and MN7. MN5 and MN6 form a current mirror, the gate terminal of MN5 is connected to the drain terminal of MN5, the gate terminal of MN6, and the drain terminal of MP14, the drain terminal of MN6 is connected to the drain terminal of MP17 and the source terminal of MN7, MP15 and MP16 form a current mirror, the gate terminal of MP15 is connected to the drain terminal of MP15, the gate terminal of MP16, and the source terminal of MP17, the drain terminal of MP16 is connected to the source terminal of MP18, the drain terminal of MP18 is connected to the drain terminal of MN7, and the input voltage signal DIR1 is connected to the gate terminal of MP17, the gate terminal of MP18, and the gate terminal of MN7.

[0038] The VCC node is connected to the source terminals of MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP14, MP15, and MP16 respectively, and the GND node is connected to the source terminals of MN0, MN1, MN2, MN3, MN5, and MN6, as well as the other terminal of R0 and R1. The DC current source IB is connected to the drain terminal of MP18, the drain terminal of MN7, the drain terminal of MP13, the drain terminal of MN4, and the resistor R1.

[0039] The voltage signal V IN By input current I IN Flows through resistor R0, and the input voltage signal range is V REFL <V IN <V REFH, input reference voltage V REFL With V REFH The voltage reference module can provide an unlimited generation form, I REF and IB can be generated in any form provided by the current reference.

[0040] In the arc function generator, I1 is the difference between the leakage currents of MP1 and MP0, and I2 is the difference between the leakage currents of MP2 and MP3. For the first differential pair, MP0 and MP1 are 1:1 in size and have V REFL <V IN <V REFH , V IN With V REFH When they are close to each other, MP0 and MP1 both work in the saturation region, and the difference in their drain currents has the following relationship (1):

[0041]

[0042] Where: μ n is the channel electron mobility; Cox is the gate oxide capacitance per unit area; W / L is the width and length of MP0 and MP1 tubes; I SS is the tail current of the differential pair; I MP0 is the leakage current of MP0; I MP1 is the leakage current of MP1; V IN is the input voltage; V REFH For fixed voltage.

[0043] because When x<<1, according to the equivalent infinitesimal substitution principle, equation (1) can be replaced by equation (2).

[0044]

[0045] For the parameters in formula (2) Therefore, I1 and V IN It shows a cubic function relationship. When V IN With V REFH When the difference is large, MP1 works in the saturation region and MP0 works in the subthreshold region. At this time, the leakage currents of the two are expressed as equations (3) and (4):

[0046]

[0047] Where: μ n is the channel electron mobility; Cox is the gate oxide capacitance per unit area; W / L is the width and length of the MP1 input tube; V GS,MP1 is the voltage difference between the gate and source of MP1; I MP1 is the leakage current of MP1; V REFH For fixed voltage.

[0048]

[0049] Where: I0 is proportional to the W / L of MP0; ξ>1 is a non-ideal factor; V T =kT / q is the thermal voltage, k is the Boltzmann constant, T is the temperature, and q is the electron charge; V GS,MP0 is the voltage difference between the gate and source of MP0; I MP0 is the leakage current of MP0.

[0050] Since MP0 operates in the subthreshold region, its current is negligible compared to the leakage current of MP1. IN With V REFH When the difference is large, the difference between the two currents I1 and V IN It is approximately a quadratic function relationship. For the MP2 and MP3 differential input pairs, there is a 1:1 relationship in size and V REFL <V IN <V REFH , similarly, we can get I2 and V IN 、V REFL The voltage difference between them. IN From V REFL Change to V REFH , the sum of I1, I2 and V IN It presents an arc relationship with an opening downward, which means that the sum of I1 and I2 is equal to I IN It presents an arc-shaped relationship with an opening downward, and the final current I OUT isI IN The sum of the linear relationship plus the arc relationship can produce a family of arcs with different concavities and slope directions.

[0051] The working process corresponding to the specific embodiment of the present invention is described as follows.

[0052] See also Figure 1 The circuit of the present invention cooperates with other peripheral circuit modules to form an arc function generator. Assuming that the ratio of all current mirrors is 1:1, when V IN From V REFL Change to V REFH For the corresponding branch currents, please refer to Figure 2 As shown, the MP0 current gradually increases and finally stabilizes at I REF / 2, the current of MP1 gradually decreases and finally stabilizes at I REF / 2, MP2 current gradually decreases and finally stabilizes at 0, MP3 current gradually decreases and finally stabilizes at I REF The currents of MP0 and MP1 are subtracted through the current mirror to become I1, and the currents of MP2 and MP3 are subtracted through the current mirror to become I2. IN From V REFL Change to V REFHFor the corresponding I1 and I2 currents, please refer to Figure 3 As shown, the current I1 gradually changes from I REF The current I1 gradually increases from 0 to I REF The sum of I1 and I2 is subtracted by the current mirror. MP6 The final current flowing through MN2 is Figure 4 As shown, the sum of I1 and 12 is in the input interval V REFL ~V REFH It is arc-shaped.

[0053] When the linear function term and the constant term are combined, a family of arcs with different concavities and slope directions can be obtained, showing the output current I R1 with I IN See the relationship Figure 5 As shown. The input signal form is not limited to the present invention, it can be current or voltage, and the two can be converted to each other. The input and output can adjust the amplitude and slope direction respectively through the current mirror ratio and the control signal DIR1, and the concave and convex direction can be adjusted by the control signal DIR0.

[0054] V REFL and V REFH Used to limit the input amplitude, IB is only used to adjust the DC point, I REF It is only used to provide reference current. The above parameters V are not limited to the specific implementation of the present invention. REFL 、V REFH ,I REF , IB and the proportional relationship of the current mirror. The modification, equivalent replacement and improvement of the above-mentioned implementation mode should be included in the protection scope of the technical solution, and the present invention is not limited to the application scenario.

[0055] The above examples and illustrations do not limit the product form and style of the present invention, and do not constitute any limitation to the present invention. Obviously, different changes and improvements can be made to its circuit under the concept of the present invention, but these are all protected by the present invention.

Claims

1. An arc function generator, characterized in that: include: Arc function generating circuit, arc function adjusting circuit and linear function generating and adjusting circuit; The arc function generating circuit is used to generate an arc signal, the arc function adjusting circuit is used to adjust the size and direction of the arc signal, the linear function generating and adjusting circuit is used to generate a linear signal and adjust the size and direction of the linear signal, and the adjusted linear signal is added to the adjusted arc signal for output; The arc function generating circuit comprises: PMOS transistors MP0, MP1, MP2 and MP3, and NMOS transistors MN0, MN1 and MN2; The drain of MP0 is connected to the gate of MN0, the drain of MN0, the gate of MN1 and the drain of MP2; the drain of MP1 is connected to the drain of MN1, the drain of MN2, the gate of MN2 and the drain of MP3; the gate of MP1 is connected to the gate of MP2, the source of MP0 is connected to the source of MP1, the source of MP2 is connected to the source of MP3, the source of MN0 is connected to the source of MN1 and the source of MN2, and the gate of MP0 is connected to the input reference signal V REFH , MP3 gate terminal input reference signal V REFL ; The arc function adjustment circuit includes: PMOS transistors MP10, MP11, MP12 and MP13, and NMOS transistors MN3 and MN4; The gate terminal of MP10 is connected to the drain terminal of MP10, the gate terminal of MP11 and the source terminal of MP12, the drain terminal of MP11 is connected to the source terminal of MP13, the drain terminal of MP12 is connected to the drain terminal of MN3 and the source terminal of MN4, the drain terminal of MP13 is connected to the drain terminal of MN4, the gate terminal of MN3 is connected to the gate terminal of MN2, the source terminal of MN3 is connected to the source terminal of MN0, and the gate terminals of MP12, MP13 and MN4 are connected to the input voltage signal DIR0; It also includes a resistor R1, one end of the resistor R1 is connected to the source end of MN0, and the other end is connected to the drain end of MP13; The linear function generation and adjustment circuit includes: PMOS transistors MP4, MP14, MP15, MP16, MP17 and MP18, and NMOS transistors MN5, MN6 and MN7; The gate terminal of MP4 is connected to the drain terminal of MP4 and the gate terminal of MP14, the gate terminal of MN5 is connected to the drain terminal of MN5, the gate terminal of MN6 and the drain terminal of MP14, the drain terminal of MN6 is connected to the drain terminal of MP17 and the source terminal of MN7, the gate terminal of MP15 is connected to the drain terminal of MP15, the gate terminal of MP16 and the source terminal of MP17, the drain terminal of MP16 is connected to the source terminal of MP18, the drain terminal of MP18 is connected to the drain terminal of MN7, the source terminal of MN5 and the source terminal of MN6 are both connected to the source terminal of MN0, the gate terminal of MP17, the gate terminal of MP18 and the gate terminal of MN7 are connected to the input voltage signal DIR1, and the gate terminal of MP4 is connected to the input current signal I IN .

2. The arc function generator according to claim 1, characterized in that The arc function generating circuit also includes an input current-voltage conversion circuit, which is used for converting the input current into a voltage and outputting the voltage to the arc function generating circuit.

3. The arc function generator according to claim 2, characterized in that The input current-voltage conversion circuit includes a PMOS transistor MP8 and a resistor R0; the drain terminal of MP8 is connected to the gate terminals of MP1 and MP2 and one end of the resistor R0; the gate terminal of MP8 is connected to the gate terminal of MP4, and the other end of the resistor R0 is connected to the source terminal of MN0.

4. The arc function generator according to claim 1, characterized in that The arc function generating circuit also includes a constant current source, which provides a current source for MP0, MP1, MP2, MP3, MN0, MN1 and MN2.

5. The arc function generator according to claim 4, characterized in that The constant current source includes PMOS transistors MP5, MP6, MP7 and MP9; The gate terminal of MP5 is connected to the drain terminal of MP5 and is connected to the gate terminal of MP6, the gate terminal of MP7, the gate terminal of MP9 and the source terminal of MN0. The drain terminal of MP6 is connected to the drain terminal of MN0. The drain terminal of MP7 is connected to the source terminals of MP0 and MP1. The drain terminal of MP9 is connected to the source terminals of MP2 and MP3. The gate terminal of MP5 is connected to the input reference current I REF .

6. A crystal oscillator, characterized in that: The invention comprises the arc function generator as described in any one of claims 1 to 5.

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