Circuit for entering chip into test mode and method for determining whether chip enters test mode

Abstract

The application provides a circuit and a determination method for a chip entering a test mode, the circuit comprising: a switch connected between an input pin of the chip and a preset pin, a signal adjusting unit and a transmission unit; the signal adjusting unit and the transmission unit are connected with the input pin of the chip respectively; the signal adjusting unit is used for adjusting the signal of the input pin according to a received preset pulse signal; and the transmission unit is used for transmitting the signal of the input pin to an output end when an enabling signal is received, so that the chip enters the test mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and in particular to a circuit for a chip to enter a test mode and a method for determining that a chip enters a test mode. BACKGROUND

[0002] With the development of society, chips are becoming more and more common in people's lives. There are a large number of terminal devices such as mobile phones, computers, and smart speakers that use chips to support corresponding functions. Chips are attracting more and more attention due to their small size, large-scale integration, and high processing performance.

[0003] Before being delivered to customers, chips need to pass a final test before leaving the factory. The coverage rate of the test is a guarantee that the chip will not have problems when used by customers. Currently, circuit probing (CP) is generally used to increase the test, that is, the test is performed before the wafer is packaged to ensure that each die after wafer cutting meets the characteristics or design specification of the device.

[0004] Although wafer testing can cover almost all chip test items, in actual application, the die after wafer testing needs to be packaged and wired, which can introduce parasitic capacitance, inductance, and resistance to the chip pins. For chips that are sensitive to parasitics, the parameters of the previously tested chips may deviate, thereby affecting normal functions. SUMMARY

[0005] To this end, the present application provides a circuit for a chip to enter a test mode and a method for determining that a chip enters a test mode, which can enable the die after packaging and wiring to enter a test mode for testing, thereby avoiding the problem that the parasitic capacitance, inductance, and resistance introduced after packaging and wiring cause the chip parameters to deviate, resulting in the chip being unable to be used normally.

[0006] To achieve the above object, embodiments of the present application provide the following technical solutions:

[0007] The first aspect of the present application discloses a circuit for a chip to enter a test mode, comprising: a switch connected between an input pin of the chip and a predetermined pin, a signal adjustment unit, and a transmission unit;

[0008] The signal adjustment unit and the transmission unit are respectively connected to the input pin of the chip.

[0009] The signal adjustment unit is configured to adjust the signal of the input pin according to a received predetermined pulse signal.

[0010] The transmission unit is configured to transmit the signal of the input pin to an output end when an enable signal is received, so that the chip enters a test mode.

[0011] Optionally, in the circuit for entering the test mode of the chip, if the preset pin is a power pin of the chip, the signal adjusting unit comprises a first resistor and a first switch tube.

[0012] One end of the first resistor is connected with the input pin of the chip as an input end of the signal adjusting unit.

[0013] The other end of the first resistor is connected with a second end of the first switch tube, a control end of the first switch tube receives the preset pulse signal, and a first end of the first switch tube is grounded.

[0014] Optionally, in the circuit for entering the test mode of the chip, the first switch tube is an NMOS tube.

[0015] Optionally, in the circuit for entering the test mode of the chip, if the preset pin is a ground pin of the chip, the signal adjusting unit comprises a second resistor, a first inverter and a second switch tube.

[0016] One end of the second resistor is connected with the input pin of the chip as an input end of the signal adjusting unit.

[0017] The input end of the first inverter receives the preset pulse signal, and an output end of the first inverter is connected with a control end of the second switch tube.

[0018] The second end of the second switch tube is connected with the other end of the second resistor, and a first end of the second switch tube is connected with an input power supply.

[0019] Optionally, in the circuit for entering the test mode of the chip, the preset pin is a ground pin of the chip, and the second switch tube is a PMOS tube.

[0020] Optionally, in the circuit for entering the test mode of the chip, the transmission unit comprises a transmission gate, one end of the transmission gate is connected with the input pin of the chip as an input end of the transmission unit, the other end of the transmission gate is an output end of the transmission unit, and a control end of the transmission gate receives the enable signal.

[0021] The second aspect of the present application discloses a determination method for entering a test mode of a chip, applied to the circuit for entering the test mode of the chip as disclosed in any one of the first aspect, and the method comprises:

[0022] Determining a preset pin that needs to be connected with the input pin of the chip;

[0023] determining whether the output of the transmission unit in the circuit for entering the chip into the test mode satisfies a preset determination condition corresponding to the preset pin;

[0024] if the determination result is yes, it is determined that the chip enters the test mode;

[0025] if the determination result is no, it is determined that the chip does not enter the test mode.

[0026] Optionally, in the determination method for entering the chip into the test mode, if the preset pin is a power pin of the chip, the output of the transmission unit in the circuit for entering the chip into the test mode satisfies a preset determination condition corresponding to the preset pin, and the preset determination condition includes:

[0027] if the signal adjustment unit in the circuit for entering the chip into the test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is high;

[0028] if the signal adjustment unit in the circuit for entering the chip into the test mode receives a preset pulse signal as a multiple pulse signal, the output of the transmission unit is high during each pulse signal.

[0029] Optionally, in the determination method for entering the chip into the test mode, if the preset pin is a ground pin of the chip, the output of the transmission unit in the circuit for entering the chip into the test mode satisfies a preset determination condition corresponding to the preset pin, and the preset determination condition includes:

[0030] if the signal adjustment unit in the circuit for entering the chip into the test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is low;

[0031] if the signal adjustment unit in the circuit for entering the chip into the test mode receives a preset pulse signal as a multiple pulse signal, the output of the transmission unit is low during each pulse signal.

[0032] Optionally, in the determination method for entering the chip into the test mode, after the preset pin to be connected to the input pin of the chip is determined, the method further includes:

[0033] inputting a preset determination signal to the input pin of the chip;

[0034] determining whether the output of the transmission unit in the circuit for entering the chip into the test mode is the same as the pulse width of the preset determination signal;

[0035] if the determination result is yes, it is determined that the chip enters the test mode;

[0036] if the determination result is no, it is determined that the chip does not enter the test mode.

[0037] Based on the above chip entering test mode circuit provided by the application, the circuit comprises a switch connected with the input pin of the chip and a preset pin, a signal adjusting unit and a transmission unit; the signal adjusting unit and the transmission unit are connected with the input pin of the chip respectively; the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal; and the transmission unit is used for transmitting the signal of the input pin to the output end when the enable signal is received, so that the chip enters the test mode. That is, the application can make the bare chip after packaging and wiring enter the test mode for testing, so as to avoid the problem that the parasitic capacitance, inductance and resistance introduced after packaging and wiring cause the deviation of the chip parameters, and the chip cannot be used normally. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0039] Figure 1 A peripheral circuit diagram of a chip entering test mode circuit provided by the embodiment of the present application;

[0040] Figure 2 An internal circuit diagram of a chip entering test mode circuit provided by the embodiment of the present application;

[0041] Figure 3 A peripheral circuit diagram of another chip entering test mode circuit provided by the embodiment of the present application;

[0042] Figure 4 An internal circuit diagram of another chip entering test mode circuit provided by the embodiment of the present application;

[0043] Figure 5 A flowchart of a chip entering test mode determination method provided by the embodiment of the present application;

[0044] Figure 6 A flowchart of another chip entering test mode determination method provided by the embodiment of the present application;

[0045] Figure 7 A pin schematic diagram of a chip provided by the embodiment of the present application. DETAILED DESCRIPTION

[0046] With reference to the drawings and embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts are within the scope of the present application.

[0047] The chip test mode circuit provided by the embodiments of the present application can enable the bare chip after packaging and wire bonding to enter the test mode for testing, so as to avoid the problem that the parasitic capacitance, inductance and resistance introduced after packaging and wire bonding cause the chip parameters to deviate, and the chip cannot be normally used.

[0048] Please refer to Figure 1 and Figure 2 , or Figure 3 and Figure 4 The chip test mode circuit can include: a switch (S1 in Figure 1 , S2 in Figure 2 ) connecting the input pin of the chip and the preset pin, a signal adjusting unit and a transmission unit.

[0049] It should be noted that the switch connecting the input pin of the chip and the preset pin can be arranged in the periphery of the chip, that is, the case shown in Figure 1 or Figure 3 .

[0050] The signal adjusting unit and the transmission unit are respectively connected with the input pin of the chip.

[0051] It should be noted that the signal adjusting unit and the transmission unit can be arranged in the internal circuit of the chip, that is, the case shown in Figure 2 or Figure 4 .

[0052] The signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal.

[0053] In actual application, as shown in Figure 1 , if the preset pin is the power pin VDD of the chip, as shown in Figure 2 , the signal adjusting unit can include: a first resistor R1 and a first switch tube MN1. One end of the first resistor R1 is connected with the input pin IN of the chip as the input end of the signal adjusting unit; the other end of the first resistor R1 is connected with the second end of the first switch tube MN1, the control end of the first switch tube MN1 receives the preset pulse signal INIT_PULSE, and the first end of the first switch tube MN1 is grounded.

[0054] Specifically, the first switch tube MN1 can be an NMOS tube; a first end of the first switch tube MN1 is a source, that is, an end with an arrow in the figure; a second end of the first switch tube MN1 is a drain, that is, an end without an arrow in the figure; and a control end of the first switch tube MN1 is a gate.

[0055] However, as Figure 3 shown, if the preset pin is a ground pin GND of the chip, as Figure 4 shown, the signal adjusting unit can include a second resistor R2, a first inverter QI, and a second switch tube MP1. One end of the second resistor R2 is connected to the input end of the signal adjusting unit and connected to the input pin IN of the chip; the input end of the first inverter QI receives a preset pulse signal INIT_PULSE, the output end of the first inverter QI is connected to the control end of the second switch tube MP1; the second end of the second switch tube MP1 is connected to the other end of the second resistor R2, and the first end of the second switch tube MP1 is connected to the input power supply VDD.

[0056] Specifically, the second switch tube MP1 can be a PMOS tube; a first end of the second switch tube MP1 is a source, that is, an end with an arrow in the figure; a second end of the second switch tube MP1 is a drain, that is, an end without an arrow in the figure; and a control end of the second switch tube MP1 is a gate.

[0057] It should be noted that the preset pulse signal can be a single pulse signal for chip power-on initialization, or a collection of multiple single pulse signals, which can be determined according to specific application environments and user requirements, and all fall within the protection scope of the present application.

[0058] The transmission unit is configured to, when receiving the enable signal, transmit the signal of the input pin to the output end, so as to make the chip enter the test mode.

[0059] In actual application, as Figure 2 or Figure 4 shown, the transmission unit can include a transmission gate buffer, one end of the transmission gate buffer is connected to the input end of the transmission unit and connected to the input pin IN of the chip; the other end of the transmission gate buffer is connected to the output end of the transmission unit, and the control end of the transmission gate receives the enable signal EN.

[0060] When the control end of the transmission gate buffer receives the enable signal EN as a high level, that is, EN = 1, the transmission gate buffer transmits the signal at the input end to the output end.

[0061] Based on the above principle, the circuit for the chip to enter the test mode provided in the embodiment includes: a switch connected between the input pin of the chip and the preset pin, a signal adjusting unit and a transmission unit; wherein the signal adjusting unit and the transmission unit are connected with the input pin of the chip respectively; the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal; and the transmission unit is used for transmitting the signal of the input pin to the output end when the enable signal is received, so as to make the chip enter the test mode. That is, the application can make the bare chip after packaging and wiring enter the test mode for testing, so as to avoid the problem that the parasitic capacitance, inductance and resistance introduced after packaging and wiring cause the chip parameters to deviate, resulting in the problem that the chip cannot be used normally.

[0062] It is worth noting that the circuit for the chip to enter the test mode provided in the embodiment of the application also does not need to separately set a test pin on the chip, but can make the chip enter the test mode through the circuit by multiplexing the pins carried by the chip itself, so as to perform subsequent testing on the chip, thereby avoiding the problem that the special setting of the test pin causes the increase of the size of the chip circuit and the increase of the cost. In addition, the circuit for the chip to enter the test mode provided in the application can also enter the test mode under fewer pins, for example, Figure 7 The chip shown in the figure only has the input pin IN, the output pin OUT, the power supply pin VDD and the ground pin GND, and compared with wafer testing, the chip test coverage can be improved.

[0063] Based on the circuit for the chip to enter the test mode provided in the above embodiment, another embodiment of the application further provides a determination method for the chip to enter the test mode. The method can be applied to the circuit for the chip to enter the test mode as described in any of the above embodiments. Please refer to Figure 5 The method can include the following steps:

[0064] S100, determining the preset pin that needs to be connected with the input pin of the chip.

[0065] The preset pin includes: the power supply pin and the ground pin of the chip; of course, it is not limited to this, but can also be determined according to the specific application environment and user demand, and the application does not make specific limitation thereon, which all belong to the protection scope of the application.

[0066] S102, judging whether the output of the transmission unit in the circuit for the chip to enter the test mode satisfies the preset determination condition corresponding to the preset pin.

[0067] In actual application, if the preset pin is the power supply pin of the chip, the output of the transmission unit in the circuit for the chip to enter the test mode satisfies the preset determination condition corresponding to the preset pin, which can be as follows:

[0068] a1. If the signal adjustment unit in the circuit where the chip enters test mode receives a preset pulse signal that is a single pulse signal, then the output of the transmission unit will be high level.

[0069] a2. If the signal adjustment unit in the circuit where the chip enters the test mode receives a preset pulse signal that is a multi-pulse signal, then the output of the transmission unit will be high during each pulse signal period.

[0070] However, if the preset pin is the chip's ground pin, then the output of the transmission unit in the circuit where the chip enters test mode will satisfy the preset judgment condition corresponding to the preset pin, as follows:

[0071] b1. If the signal adjustment unit in the circuit where the chip enters test mode receives a preset pulse signal that is a single pulse signal, then the output of the transmission unit will be low.

[0072] b2. If the signal adjustment unit in the circuit where the chip enters the test mode receives a preset pulse signal that is a multi-pulse signal, then the output of the transmission unit will be low during each pulse signal period.

[0073] If the judgment result is yes, that is, it is determined that the output of the transmission unit in the circuit where the chip enters the test mode meets the preset judgment condition corresponding to the preset pin, then step S104 is executed; if the judgment result is no, that is, it is determined that the output of the transmission unit in the circuit where the chip enters the test mode does not meet the preset judgment condition corresponding to the preset pin, then step S106 is executed.

[0074] S104: The chip has been determined to enter test mode.

[0075] In practical applications, if the output of the transmission unit in the circuit that determines that the chip has entered the test mode meets the preset judgment condition corresponding to the preset pin, that is, when the preset pin is the chip's power supply pin, the signal adjustment unit in the circuit that determines that the chip has entered the test mode receives a preset pulse signal as a single pulse signal, and the output of the transmission unit is high level; or, the signal adjustment unit in the circuit that determines that the chip has entered the test mode receives a preset pulse signal as a multi-pulse signal, then the output of the transmission unit is high level during each pulse signal period, and the chip can be determined to have entered the test mode.

[0076] However, when the preset pin is the chip's ground pin, the signal adjustment unit in the circuit that the chip enters the test mode receives a single pulse signal from the preset pulse signal, and the output of the transmission unit is low; or, the signal adjustment unit in the circuit that the chip enters the test mode receives a multi-pulse signal from the preset pulse signal, and the output of the transmission unit is low during each pulse signal, which can determine that the chip has entered the test mode.

[0077] S106. It is determined that the chip has not entered the test mode.

[0078] In actual application, if it is judged that the output of the transmission unit in the circuit for entering the chip into the test mode does not satisfy the preset judging condition corresponding to the preset pin, i.e., when the preset pin is the power pin of the chip, the signal adjusting unit in the circuit for entering the chip into the test mode receives the preset pulse signal as a single pulse signal, and the output of the transmission unit is at low level; or, the signal adjusting unit in the circuit for entering the chip into the test mode receives the preset pulse signal as a multi-pulse signal, and the output of the transmission unit is at low level during each pulse signal, it can be judged that the chip does not enter the test mode.

[0079] When the preset pin is the ground pin of the chip, the signal adjusting unit in the circuit for entering the chip into the test mode receives the preset pulse signal as a single pulse signal, and the output of the transmission unit is at high level; or, the signal adjusting unit in the circuit for entering the chip into the test mode receives the preset pulse signal as a multi-pulse signal, and the output of the transmission unit is at high level during each pulse signal, it can be judged that the chip does not enter the test mode.

[0080] Based on the above principle, the method for judging whether the chip enters the test mode provided in the embodiment can judge whether the output of the transmission unit in the circuit for entering the chip into the test mode satisfies the preset judging condition corresponding to the preset pin after determining the preset pin which needs to be connected with the input pin of the chip; if the judgment result is yes, it is judged that the chip enters the test mode; if the judgment result is no, it is judged that the chip does not enter the test mode, i.e., through the above judging method, it can be judged whether the circuit for entering the chip into the test mode can send the chip into the test mode in the power-on initialization stage.

[0081] Optionally, in another embodiment provided in the application, after the step S100 of determining the preset pin which needs to be connected with the input pin of the chip, please refer to Figure 6 , the method for judging whether the chip enters the test mode can further include the following step:

[0082] S200, inputting a preset judging signal to the input pin of the chip.

[0083] In actual application, a strong square wave signal with a period far less than the pulse width of the preset pulse signal can be inputted to the input pin of the chip by the outside during the preset pulse signal; or, a strong square wave signal with a period far less than the pulse width of the preset pulse signal can be inputted to the input pin of the chip by the outside during the starting test stage.

[0084] It should be noted that the pulse width of the preset judging signal can be determined according to the specific application environment and user demand, which is not limited in the application and belongs to the protection scope of the application.

[0085] S202, judging whether the output of the transmission unit in the circuit for judging whether the chip enters the test mode is the same as the pulse width of the preset judgment signal.

[0086] In actual application, when the transmission unit transmits the signal of the input pin of the chip to its output end during the preset pulse signal, whether the chip enters the test mode can be determined by judging whether the output of the transmission unit in the circuit for judging whether the chip enters the test mode is the same as the pulse width of the preset judgment signal.

[0087] If the result of the judgment is yes, that is, the output of the transmission unit in the circuit for judging whether the chip enters the test mode is the same as the pulse width of the preset judgment signal, step S204 is executed; if the result of the judgment is no, that is, the output of the transmission unit in the circuit for judging whether the chip enters the test mode is not the same as the pulse width of the preset judgment signal, step S206 is executed.

[0088] S204, judging that the chip enters the test mode.

[0089] In actual application, if the output of the transmission unit in the circuit for judging whether the chip enters the test mode is the same as the pulse width of the preset judgment signal, it indicates that the signal adjustment unit in the circuit for judging whether the chip enters the test mode cannot adjust the signal of the input pin of the chip, and it can be determined that the chip enters the test mode.

[0090] S206, judging that the chip does not enter the test mode.

[0091] In actual application, if the output of the transmission unit in the circuit for judging whether the chip enters the test mode is not the same as the pulse width of the preset judgment signal, it indicates that the signal adjustment unit in the circuit for judging whether the chip enters the test mode can adjust the signal of the input pin of the chip, and it can be determined that the chip does not enter the test mode.

[0092] Based on the circuit for judging whether the chip enters the test mode provided in the above embodiment, assuming that the circuit for judging whether the chip enters the test mode can be specifically as shown in Figure 1 and 2 , the method for judging whether the chip enters the test mode has the following implementation process.

[0093] When the chip is in the normal working mode, the signal of the input pin IN enters the internal circuit (Ana_circuit) through path 2. Figure 2 When the chip is in the test mode, the signal of the input pin IN enters the internal circuit (Ana_circuit) through path 1.

[0094] When the power-on initialization process is in progress, the enable signal is high, at this time, the signal passes through the output end (OUT_DIG) of the transmission gate buffer and is output to the internal logic circuit, and path 2 is closed. Whether the chip enters the test mode after the power-on initialization is completed can be determined by collecting the high and low signals of the input pin IN.

[0095] During power-on initialization, the chip generates a pulse signal (INIT_PULSE) of a certain width. The purpose of this signal is to lock the level of the input pin IN. When this pulse signal is high (during latching), the switching transistor MN1 is turned on, and the signal of the input pin is pulled down through the resistor R1.

[0096] If the input pin IN is not pulled up before initialization, that is, the switch connecting the input pin IN of the chip to the power supply pin VDD is disconnected, then during the latching period, because the pulse signal is pulled down through the resistor R1, the output signal of the transmission gate buffer (OUT_DIG) is low level "0", and the chip does not enter the test mode at this time.

[0097] If the chip's external input pin IN is pulled up before power-on initialization, that is, the switch connecting the chip's input pin IN and the power supply pin VDD is closed, then during latching, the pulse signal is pulled down through resistor R1. Since the external pull-up is a strong pull-up and the internal pull-down through resistor R1 is a weak pull-down, the output signal of the transmission gate buffer (OUT_DIG) is a high level "1", at which point the chip enters test mode.

[0098] It should be noted that once the chip enters test mode, other chip pins, such as input and output pins, can be reused for further testing and verification. To exit test mode, simply power on the chip again without applying a pull-up to the input pin IN before powering on.

[0099] Furthermore, after the chip enters normal operating mode after power-on initialization, the pulse signal remains low and the enable signal remains low. At this time, path 1 is closed, and the input pin IN is not pulled down, which will not affect the normal operation of the chip.

[0100] And assuming the circuit for the chip to enter test mode can be specifically as follows: Figure 3 and 4 As shown. The circuit for the chip to enter test mode in this example is a variation of the above example. The specific implementation process for determining whether the chip enters test mode is as follows:

[0101] When the chip is in normal operating mode, the signal from the input pin IN enters the internal circuit through path 2. Figure 4 (Ana_circuit in the context of this).

[0102] During power-on initialization, the enable signal is high. At this time, the signal is output through path 1 through the output terminal (OUT_DIG) of the transmission gate buffer and enters the internal logic circuit. Path 2 is closed. The test mode can be determined by sampling the high and low levels of the signal on the input pin IN.

[0103] In the power-on initialization process, a pulse signal (INIT_PULSE) of a certain width is generated inside the chip, and the purpose of the signal is to lock the high and low levels of the input pin IN. In the pulse signal, the switch tube MP1 is turned on when the signal is high (during latching), and at this time the input pin IN signal is pulled up through the resistor R1.

[0104] If the input pin IN is not pulled down by the chip periphery before initialization, that is, the switch connecting the input pin IN of the chip and the ground pin GND is open, then during latching, the signal output by the output end (OUT_DIG) of the transmission gate buffer is high "1" because the pulse signal is pulled up through the resistor R1, and at this time the chip does not enter the test mode.

[0105] If the input pin IN is pulled down by the chip periphery before power-on initialization, that is, the switch connecting the input pin IN of the chip and the ground pin GND is closed, then during latching, the signal output by the output end (OUT_DIG) of the transmission gate buffer is low "0" because the pulse signal is pulled up through the resistor R1, and the external pull-down is strong and the internal pull-up through the resistor R1 is weak, and at this time the chip enters the test mode.

[0106] In addition to the above-mentioned method of determining whether the chip enters the test mode, a plurality of pulse signals can also be used to detect the high and low levels of the output of the transmission gate buffer, and when it is detected that the output signal of the transmission gate buffer during the plurality of pulses is all high or all low, it can be determined that the chip enters the test mode.

[0107] In addition, a strong square wave signal with a period much smaller than the pulse width of the pulse signal can also be input externally to the input pin IN during the pulse, and when it is detected that the output of the transmission gate is a square wave signal with both high and low, it is determined that the chip enters the test mode.

[0108] The features described in the various embodiments in the specification can be substituted or combined with each other, and the same or similar parts among the various embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. Especially, for the system or system embodiments, since they are basically similar to the method embodiments, they are described more simply, and the relevant parts can be referred to the part of the method embodiments. The above described system and system embodiments are only illustrative, and the units described as separate components can be or can not be physically separated, and the components shown as units can be or can not be physical units, i.e. they can be located in one place or distributed to multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to the actual needs. Those skilled in the art can understand and implement without creative labor.

[0109] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0110] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0111] It is also to be noted that, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Furthermore, the terms "comprising," "containing," or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

1. A circuit for entering a chip into a test mode, characterized by The circuit comprises: a switch connecting the input pin of the chip with the preset pin, a signal adjusting unit and a transmission unit; the signal adjusting unit and the transmission unit are connected with the input pin of the chip respectively; the signal adjusting unit is used for adjusting the signal of the input pin according to the received preset pulse signal; the preset pulse signal is a single pulse signal or a collection of multiple single pulse signals for chip power-on initialization; the transmission unit is used for transmitting the signal of the input pin to an output end when receiving an enable signal, so as to make the chip enter a test mode; the output condition of the transmission unit is related to the type of the preset pin; when the preset pin is a power pin, the output of the transmission unit is high level; when the preset pin is a ground pin, the output of the transmission unit is low level.

2. The circuit for chip bring-up test mode of claim 1, wherein, If the preset pin is the power pin of the chip, the signal adjusting unit comprises a first resistor and a first switch tube; one end of the first resistor is connected with the input pin of the chip as an input end of the signal adjusting unit; the other end of the first resistor is connected with the second end of the first switch tube, the control end of the first switch tube receives the preset pulse signal, and the first end of the first switch tube is grounded.

3. The circuit for chip bring-up test mode of claim 2, wherein, The first switch tube is an NMOS tube.

4. The circuit for chip bring-up test mode of claim 1, wherein, If the preset pin is the ground pin of the chip, the signal adjusting unit comprises a second resistor, a first inverter and a second switch tube; one end of the second resistor is connected with the input pin of the chip as an input end of the signal adjusting unit; the input end of the first inverter receives the preset pulse signal, and the output end of the first inverter is connected with the control end of the second switch tube; the second end of the second switch tube is connected with the other end of the second resistor, and the first end of the second switch tube is connected with an input power supply.

5. The circuit for chip bring-up test mode of claim 4, wherein, The preset pin is the ground pin of the chip, and the second switch tube is a PMOS tube.

6. The circuit for chip bring-up test mode of claim 1, wherein, The transmission unit comprises a transmission gate, one end of the transmission gate is connected with the input pin of the chip as an input end of the transmission unit, the other end of the transmission gate is an output end of the transmission unit, and the control end of the transmission gate receives the enable signal.

7. A method of determining entry into a test mode of a chip, characterized by The method for making the chip enter the test mode by using the circuit of any one of claims 1-6 comprises: determining the preset pin which needs to be connected with the input pin of the chip; judging whether the output of the transmission unit in the circuit for making the chip enter the test mode meets the preset judgment condition corresponding to the preset pin; if the judgment result is yes, it is determined that the chip enters the test mode; if the judgment result is no, it is determined that the chip does not enter the test mode.

8. The method of claim 7, wherein the chip is determined to be in the test mode when the first signal is in the first state and the second signal is in the second state. If the preset pin is the power pin of the chip, the output of the transmission unit in the circuit for making the chip enter the test mode meets the preset judgment condition corresponding to the preset pin, which comprises: if the signal adjusting unit in the circuit for making the chip enter the test mode receives a single pulse signal as the preset pulse signal, the output of the transmission unit is high level; If the signal adjustment unit in the circuit for the chip to enter the test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is low.

9. The method of claim 7, wherein the chip entry test mode is determined by a value of a signal. If the preset pin is a ground pin of the chip, the output of the transmission unit in the circuit for the chip to enter the test mode satisfies a preset judgment condition corresponding to the preset pin, which includes: If the signal adjustment unit in the circuit for the chip to enter the test mode receives a preset pulse signal as a single pulse signal, the output of the transmission unit is low; If the signal adjustment unit in the circuit for the chip to enter the test mode receives a preset pulse signal as a multiple pulse signal, the output of the transmission unit is high during each pulse signal.

10. The method of claim 7, wherein the chip entry test mode is determined by a test mode signal. After determining the preset pin that needs to be connected with the input pin of the chip, the method further includes: inputting a preset judgment signal to the input pin of the chip; judging whether the output of the transmission unit in the circuit for the chip to enter the test mode is the same as the pulse width of the preset judgment signal; if the judgment result is yes, it is determined that the chip enters the test mode; if the judgment result is no, it is determined that the chip does not enter the test mode.

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