Voltage Sequence Data Caching Method and System

Abstract

The present invention provides a voltage sequence data caching method and system, the method comprising: caching original voltage data; separating control instruction data and voltage sequence data in the original voltage data and caching them separately; performing a read operation on the voltage sequence data based on the control instruction data after preset bit-splitting processing, reordering the voltage sequence data and performing a write operation, and outputting new voltage sequence data. The present invention separates and caches channel data and control instructions for voltage data streams with different channel data and control instructions, reorders the separated data according to the position and state of the control instructions, and outputs the voltage sequence data corresponding to each channel, thereby increasing the readability and operability of the voltage sequence data.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a voltage sequence data caching method and system. Background Art

[0002] In the field of data processing, data caching is a common data processing method. For a single type of data stream, simple storage and reading are sufficient to meet the general requirements of data processing.

[0003] As data types become increasingly complex, data caching technology becomes more and more popular, and data streams are changing from single to diversified. For some specific diversified data streams, traditional data caching methods can no longer meet the application scenarios of diversified data streams.

[0004] Therefore, a new data caching method needs to be proposed for specific data streams. Summary of the invention

[0005] The present invention provides a voltage sequence data caching method and system, which are used to solve the defect that there is no targeted data caching method for specific voltage data in the prior art.

[0006] In a first aspect, the present invention provides a voltage sequence data caching method, comprising:

[0007] Cache raw voltage data;

[0008] Separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately;

[0009] The voltage sequence data is read based on the control instruction data after the preset bit-splitting processing, the voltage sequence data is reordered and written, and new voltage sequence data is output.

[0010] According to the voltage sequence data caching method provided by the present invention, the caching of original voltage data also includes:

[0011] The original voltage data is acquired.

[0012] According to the voltage sequence data caching method provided by the present invention, the caching of original voltage data comprises:

[0013] The original voltage data corresponding to the media access control address MAC address received through the Ethernet port is cached in the random access memory RAM inside the chip.

[0014] According to the voltage sequence data caching method provided by the present invention, the control instruction data and the voltage sequence data in the original voltage data are separated and cached separately, including:

[0015] Extract the control instruction data, respectively obtain the number of data before each control instruction data in the original voltage data, concatenate each control instruction data with the corresponding number of data, and cache them in RAM respectively;

[0016] The voltage values ​​and delay values ​​of each channel in the voltage sequence data are cached in a first-in-first-out FIFO memory in the original order.

[0017] According to the voltage sequence data caching method provided by the present invention, the control instruction data and the voltage sequence data in the original voltage data are separated and cached separately, and further includes:

[0018] If the voltage sequence data includes several voltage sequence data after the last control instruction data, the preset padding control instruction and the corresponding number of data are used for bit splicing and cached in the RAM.

[0019] According to the voltage sequence data caching method provided by the present invention, the control instruction data after the preset bit-splitting processing is used to read the voltage sequence data, re-order the voltage sequence data and perform a write operation, and output new voltage sequence data, including:

[0020] Sequentially read the control instruction data after bit-splitting processing in the RAM and the corresponding data length in the FIFO memory;

[0021] Based on the switch states of each channel and the voltage values ​​of each channel in the control instruction data, the voltage sequence data is valued and reordered to obtain the voltage sequence data after the write operation;

[0022] The voltage sequence after the write operation is stored in a plurality of RAMs according to each channel to obtain the new voltage sequence data.

[0023] In a second aspect, the present invention further provides a voltage sequence data cache system, comprising:

[0024] A cache module, used to cache raw voltage data;

[0025] A separation module, used for separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately;

[0026] The processing module is used to perform a read operation on the voltage sequence data based on the control instruction data after the preset bit-splitting processing, re-order the voltage sequence data and perform a write operation, and output new voltage sequence data.

[0027] In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the voltage sequence data caching methods described above are implemented.

[0028] In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the voltage sequence data caching methods described above.

[0029] In a fifth aspect, the present invention further provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned voltage sequence data caching methods are implemented.

[0030] The voltage sequence data caching method and system provided by the present invention adopt separate caching channel data and control instructions for voltage data streams with different channel data and control instructions, reorder the separated data according to the position and status of the control instructions, and output the voltage sequence data corresponding to each channel, thereby increasing the readability and operability of the voltage sequence data. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 This is one of the flow charts of the voltage sequence data caching method provided by the present invention;

[0033] Figure 2 This is the second flow chart of the voltage sequence data caching method provided by the present invention;

[0034] Figure 3 It is a schematic diagram of an embodiment of voltage sequence data cache provided by the present invention;

[0035] Figure 4 It is a structural schematic diagram of the voltage sequence data cache system provided by the present invention;

[0036] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] The present invention is aimed at the voltage sequence data of multiple channels in the chip, and the voltage sequence data includes the voltage data itself, the delay setting control instruction, the channel control instruction, the start and end control instruction and other data. The voltage sequence data includes multiple data types, and the traditional data caching method for caching single data cannot be used. Therefore, the present invention proposes a new voltage sequence data caching method.

[0039] Figure 1 FIG. 1 is one of the flow charts of the voltage sequence data caching method provided by the present invention, such as Figure 1 As shown, including:

[0040] S1, caches raw voltage data;

[0041] S2, separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately;

[0042] S3, performing a read operation on the voltage sequence data based on the control instruction data after the preset bit-splitting processing, reordering the voltage sequence data and performing a write operation, and outputting new voltage sequence data.

[0043] Specifically, firstly, all the voltage data with control instructions are cached in the original order, and then the two major parts of control instruction data and voltage sequence data are separated and cached again without disrupting the original order of the voltage data.

[0044] Here, the content of the control instruction data cache records the number of data preceding the control instruction in the sequence in addition to the instruction. When performing a read operation, the corresponding voltage sequence cache data is segmented according to the number of data recorded in each control instruction data cache, and read one segment at a time, and the order cannot be changed. Then, the read voltage sequence data is reordered according to the switch state of each channel in each control instruction data and the channel number of the data in the voltage sequence to form a voltage sequence for each channel, and the new voltage sequence data finally obtained is output.

[0045] The present invention caches and sorts specific voltage sequence data, adopts a separate cache and reordering method, separates cache channel data and control instructions, and reorders the separated data according to the position and state of the control instructions to form multiple groups of new voltage sequence data.

[0046] Based on the above embodiment, the cached raw voltage data further includes:

[0047] The original voltage data is acquired.

[0048] Specifically, Figure 2 As shown, the original voltage data is first collected, the collected original voltage data is cached, and then the cached original voltage data is separated to obtain control instruction data and voltage sequence data, which are cached separately. Furthermore, the control instruction data is read by the read controller, so that the voltage sequence data is reordered and valued according to the control information of the control instruction data, and the voltage sequence data output by multiple channels is obtained.

[0049] The present invention adopts separate cache channel data and control instructions for voltage data streams with different channel data and control instructions, reorders the separated data according to the position and state of the control instructions, and outputs voltage sequence data corresponding to each channel, thereby increasing the readability and operability of the voltage sequence data.

[0050] Based on the above embodiment, the cached raw voltage data includes:

[0051] The original voltage data corresponding to the media access control address MAC address received through the Ethernet port is cached in the random access memory RAM inside the chip.

[0052] It should be noted that the present invention uses hexadecimal to represent data and instructions, wherein there are 12 types of instructions. In each instruction data, the upper 4 bits give the instruction type, and the lower 20 bits correspond to the specific data of the instruction. The data format is as follows:

[0053] 000000 empty command;

[0054] Xabcde sets the voltage of the Xth channel, and the voltage is specified by abcde;

[0055] C000ab starts the voltage output, and the channel number is specified by the lower 8 bits of data ab. For example, 10000111 means starting the four channels 1, 2, 3, and 8.

[0056] Dabcde waits for abcde clock cycles (the clock frequency is subject to the specific design);

[0057] F00000 ends the operation.

[0058] Taking a simple set of raw voltage data as an example, according to the above data format, it includes: [0x000000, 0xD0000a (wait 10 clock cycles), 0x10ffff (set 1 channel voltage), 0x2ddddd (set 2 channel voltage), 0xC00003 (output 1 and 2 channels), 0xDfffff (wait 0xfffff clock cycles), 0xD000dd (wait 0xdd clock cycles), 0x100000 (set 1 channel voltage), 0x2eeeee (set 2 channel voltage), 0xC00001 (output 1 channel), 0xD000ff (wait 0xff clock cycles), 0xF00000 (end instruction)].

[0059] like Figure 3 As shown, firstly, the data packet corresponding to the MAC (Media Access Control Address) address is received through the Ethernet port, and the collected raw data is cached in the RAM (Random Access Memory) inside the chip, as shown in FIG. Figure 3 As shown in step (1) in the above example.

[0060] The present invention adopts a hexadecimal data format to represent voltage sequence data, effectively distinguishes data types such as instruction data, delayed instruction data and voltage data, and facilitates subsequent grouping and data extraction and caching.

[0061] On the basis of the above embodiment, the step of separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately includes:

[0062] Extract the control instruction data, respectively obtain the number of data before each control instruction data in the original voltage data, concatenate each control instruction data with the corresponding number of data, and cache them in RAM respectively;

[0063] The voltage values ​​and delay values ​​of each channel in the voltage sequence data are cached in a first-in-first-out FIFO memory in the original order.

[0064] The step of separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately further includes:

[0065] If the voltage sequence data includes several voltage sequence data after the last control instruction data, the preset padding control instruction and the corresponding number of data are used for bit splicing and cached in the RAM.

[0066] Specifically, after the original voltage data is cached, the data needs to be separated, and the control instructions and the number of data before the current instruction are pieced together and stored in the RAM, such as Figure 3 As shown in step (2), still taking the voltage data sequence of 12 data in the above embodiment as an example, the control instructions 0xC00003 (output channels 1 and 2) and 0xC00001 (output channel 1) are extracted.

[0067] Since there are 4 data before the 0xC00003 instruction, the count value 4 and the control instruction 0XC00003 are stored in RAM, and {0XC00003, 4} is obtained. Similarly, there are 4 data before 0xC00001, and the count value 4 and the control instruction 0XC00001 are stored in RAM, and {0XC00001, 4} is obtained. Here, since there are two data after the control instruction 0XC00001, and the control instruction is not included, the present invention adopts the setting of the default instruction 0XC00000, and adds the remaining number of data, and the splicing obtains {0XC00000, 2}, that is, the state of all channels is 0. At the same time, the remaining channel voltage values ​​and delay values ​​are stored in the FIFO (First Input First Output) memory in the original order. The FIFO memory is divided into a write-only area and a read-only area. The read operation and the write operation can be performed asynchronously. The data written in the write area is read out from the read end area in the order of writing, which is similar to a buffer that absorbs the speed difference between the write end and the read end.

[0068] The present invention simplifies the format of the voltage data sequence by performing bit-splitting processing on the control instructions in the voltage data sequence, and uses empty control instructions to complete the data sequence, so as to facilitate the subsequent read and write operations and correct processing of reordering.

[0069] On the basis of the above embodiment, the control instruction data after the preset bit-splitting processing is used to read the voltage sequence data, re-order the voltage sequence data and write it into the corresponding random access memory RAM, and output new voltage sequence data, including:

[0070] Sequentially read the control instruction data after bit-splitting processing in the RAM and the corresponding data length in the FIFO memory;

[0071] Based on the switch states of each channel and the voltage values ​​of each channel in the control instruction data, the voltage sequence data is valued and reordered to obtain the voltage sequence data after the write operation;

[0072] The voltage sequence after the write operation is stored in a plurality of RAMs according to each channel to obtain the new voltage sequence data.

[0073] Specifically, Figure 3 As shown in step (3), a read operation is performed to sequentially read out the control instructions and the number of recorded data in the RAM, as well as the corresponding data length in the FIFO. The reading order is RAM data first, then FIFO data.

[0074] The read voltage sequence data is reordered and stored in multiple RAMs according to the switch status of each channel and the voltage value of each channel in the control instruction, such as Figure 3 As shown in step (4), since the second control instruction is 0XC00001, corresponding to reading the value of channel 1, the 0X2eeeee voltage value of the second channel is not output. Here, a similar low-level process is used to discard the value, while the remaining delay control instructions are still output normally, and the voltage sequence data of the two channels in step (5) are obtained, which are:

[0075] 1 channel voltage sequence: 0xD0000a, 0x10ffff, 0xDfffff, 0xD000dd, 0x100000, 0xD000ff.

[0076] 2-channel voltage sequence: 0xD0000a, 0x2ddddd, 0xDfffff, 0xD000dd, 0xD000ff.

[0077] Finally, the corresponding voltage data sequence is output according to each channel.

[0078] The present invention obtains the switch status of each channel and the voltage value of each channel in the control instruction data after bit-splitting processing, and independently obtains the corresponding voltage values ​​of the original voltage data according to each channel, thereby realizing the acquisition of independent voltage data sequences by channel. Compared with the traditional unified caching of a single data stream, the effectiveness and systematicness of data caching are improved.

[0079] The following is a complete example to describe in detail the implementation method of the present invention for caching and sorting voltage sequence data. Figure 3 The various steps in the process include:

[0080] (1) Receive data packets corresponding to the MAC address through the Ethernet port and cache the collected raw data into the RAM inside the chip;

[0081] (2) Separate the original data, and store the control instruction and the number of data before the current instruction in RAM. For example, if there are 4 data before the instruction 0XC00003, the count value 4 and the control instruction 0XC00003 are stored in RAM. The last {0XC00000, 2} means that when there is no control instruction at the end of the data, the default instruction is 0XC00000, that is, the state of all channels is 0. At the same time, the remaining channel voltage values ​​and delay values ​​are stored in the FIFO memory in the original order;

[0082] (3) Execute a read operation to read out the control instructions and the number of recorded data in the RAM and the corresponding data length in the FIFO in sequence. The reading order is RAM data first, then FIFO data.

[0083] (4) The read voltage sequence data are reordered and stored in multiple RAMs according to the switch status of each channel and the voltage value of each channel in the control instruction. Since the second control instruction is 0XC00001, the corresponding output is 1 channel, so the 0X2eeeee voltage value of the second channel is not output, but the delay instruction is output normally, and finally the voltage sequence data of 2 channels are obtained;

[0084] (5) Finally, each channel independently outputs the corresponding voltage sequence data.

[0085] The voltage sequence data caching system provided by the present invention is described below. The voltage sequence data caching system described below and the voltage sequence data caching method described above can be referred to each other.

[0086] Figure 4 Schematic diagram of the structure of the voltage sequence data cache system provided by the present invention. Figure 4 As shown, it includes: a cache module 41, a separation module 42 and a processing module 43, wherein:

[0087] The cache module 41 is used to cache the original voltage data; the separation module 42 is used to separate the control instruction data and the voltage sequence data in the original voltage data and cache them separately; the processing module 43 is used to read the voltage sequence data based on the control instruction data after preset bit-splitting processing, reorder the voltage sequence data and perform write operations, and output new voltage sequence data.

[0088] The present invention adopts separate cache channel data and control instructions for voltage data streams with different channel data and control instructions, reorders the separated data according to the position and state of the control instructions, and outputs voltage sequence data corresponding to each channel, thereby increasing the readability and operability of the voltage sequence data.

[0089] Based on the above embodiment, the system further includes an acquisition module 44, and the acquisition module 44 is used to collect and acquire the original voltage data.

[0090] The present invention adopts separate cache channel data and control instructions for voltage data streams with different channel data and control instructions, reorders the separated data according to the position and state of the control instructions, and outputs voltage sequence data corresponding to each channel, thereby increasing the readability and operability of the voltage sequence data.

[0091] On the basis of the above embodiment, the cache module 41 is specifically used to cache the original voltage data corresponding to the media access control address MAC address received through the Ethernet port into the random access memory RAM inside the chip.

[0092] The present invention adopts a hexadecimal data format to represent voltage sequence data, effectively distinguishes data types such as instruction data, delayed instruction data and voltage data, and facilitates subsequent grouping and data extraction and caching.

[0093] On the basis of the above embodiment, the separation module 42 includes a first separation submodule 421, a second separation submodule 422 and a finishing submodule 423, wherein:

[0094] The first separation submodule 421 is used to extract the control instruction data, respectively obtain the number of data before each control instruction data in the original voltage data, piece together each control instruction data with the corresponding number of data, and cache them in RAM respectively; the second separation submodule 422 is used to cache the voltage values ​​and delay values ​​of each channel in the voltage sequence data in the original order into a first-in-first-out FIFO memory; the padding submodule 423 is used to use the preset padding control instruction and the corresponding number of data to piece together if the last control instruction data in the voltage sequence data also includes several voltage sequence data, and cache them in RAM.

[0095] The present invention simplifies the format of the voltage data sequence by performing bit-splitting processing on the control instructions in the voltage data sequence, and uses empty control instructions to complete the data sequence, so as to facilitate the subsequent read and write operations and correct processing of reordering.

[0096] Based on the above embodiment, the processing module 43 includes: a reading submodule 431, a writing submodule 432 and a processing submodule 433, wherein:

[0097] The reading submodule 431 is used to read the control instruction data that has been processed by bit-splitting in the RAM and the corresponding data length in the FIFO memory in sequence; the writing submodule 432 is used to take values ​​and reorder the voltage sequence data based on the switch status of each channel and the voltage value of each channel in the control instruction data to obtain the voltage sequence data after the write operation; the processing submodule 433 is used to store the voltage sequence after the write operation into multiple RAMs according to each channel to obtain the new voltage sequence data.

[0098] The present invention obtains the switch status of each channel and the voltage value of each channel in the control instruction data after bit-splitting processing, and independently obtains the corresponding voltage values ​​of the original voltage data according to each channel, thereby realizing the acquisition of independent voltage data sequences by channel. Compared with the traditional unified caching of a single data stream, the effectiveness and systematicness of data caching are improved.

[0099] Figure 5 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 5 As shown, the electronic device may include: a processor 510, a communication interface 520, a memory 530 and a communication bus 540, wherein the processor 510, the communication interface 520 and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call the logic instructions in the memory 530 to execute the voltage sequence data caching method, which includes: caching the original voltage data; separating the control instruction data and the voltage sequence data in the original voltage data and caching them respectively; performing a read operation on the voltage sequence data based on the control instruction data after the preset bit-splitting processing, reordering the voltage sequence data and performing a write operation, and outputting new voltage sequence data.

[0100] In addition, the logic instructions in the above-mentioned memory 530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0101] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the voltage sequence data caching method provided by the above-mentioned methods, which includes: caching the original voltage data; separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately; reading the voltage sequence data based on the control instruction data after preset bit-splitting processing, reordering the voltage sequence data and performing a write operation, and outputting new voltage sequence data.

[0102] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the voltage sequence data caching method provided by the above-mentioned methods, the method comprising: caching original voltage data; separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately; performing a read operation on the voltage sequence data based on the control instruction data after preset bit-splitting processing, reordering the voltage sequence data and performing a write operation, and outputting new voltage sequence data.

[0103] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage sequence data caching method, characterized in that: include: Cache raw voltage data; Separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately; Performing a read operation on the voltage sequence data based on the control instruction data after the preset bit-splitting processing, reordering the voltage sequence data and performing a write operation, and outputting new voltage sequence data; The separating and caching the control instruction data and the voltage sequence data in the original voltage data separately includes: Extract the control instruction data, respectively obtain the number of data before each control instruction data in the original voltage data, concatenate each control instruction data with the corresponding number of data, and cache them in RAM respectively; The voltage values ​​and delay values ​​of each channel in the voltage sequence data are cached in a first-in-first-out FIFO memory in the original order.

2. The voltage sequence data caching method according to claim 1, characterized in that: The cached raw voltage data also includes: The original voltage data is acquired.

3. The voltage sequence data caching method according to claim 1 or 2, characterized in that: The cached raw voltage data includes: The original voltage data corresponding to the media access control address MAC address received through the Ethernet port is cached in the random access memory RAM inside the chip.

4. The voltage sequence data caching method according to claim 1, characterized in that: The step of separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately further comprises: If the voltage sequence data includes several voltage sequence data after the last control instruction data, the preset padding control instruction and the corresponding number of data are used for bit splicing and cached in the RAM.

5. The voltage sequence data caching method according to claim 1, characterized in that: The control instruction data after the preset bit-splitting processing is used to read the voltage sequence data, reorder the voltage sequence data and perform a write operation, and output new voltage sequence data, including: Sequentially read the control instruction data after bit-splitting processing in the RAM and the corresponding data length in the FIFO memory; Based on the switch states of each channel and the voltage values ​​of each channel in the control instruction data, the voltage sequence data is valued and reordered to obtain the voltage sequence data after the write operation; The voltage sequence after the write operation is stored in a plurality of RAMs according to each channel to obtain the new voltage sequence data.

6. A voltage sequence data caching system, characterized in that: include: A cache module, used for caching raw voltage data; A separation module, used for separating the control instruction data and the voltage sequence data in the original voltage data and caching them separately; A processing module, used for performing a read operation on the voltage sequence data based on the control instruction data after the preset bit-splitting processing, reordering the voltage sequence data and performing a write operation, and outputting new voltage sequence data; The separation module is specifically used for: Extract the control instruction data, respectively obtain the number of data before each control instruction data in the original voltage data, concatenate each control instruction data with the corresponding number of data, and cache them in RAM respectively; The voltage values ​​and delay values ​​of each channel in the voltage sequence data are cached in a first-in-first-out FIFO memory in the original order.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the voltage sequence data caching method according to any one of claims 1 to 5 are implemented.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the voltage sequence data caching method according to any one of claims 1 to 5 are implemented.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the voltage sequence data caching method according to any one of claims 1 to 5 are implemented.

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