A Detection Method for Deep-Level Defect States in Large-Size Wafers

Abstract

The present invention provides a method for detecting deep-level defect states in a large-size wafer. The detection method includes: providing a wafer to be detected; etching a plurality of non-connected etching regions on the bottom surface of the wafer to be detected, and the unetched regions on the bottom surface of the wafer to be detected are separated into a plurality of unetched regions by the etching regions; forming a bottom metal layer on the bottom surface of the wafer to be detected; forming a patterned top metal layer on the top surface of the wafer to be detected; measuring the deep-level transient capacitance spectrum curve of the wafer to be detected, and using the deep-level transient capacitance spectrum curve to make an Arrhenius curve to obtain the energy level position and concentration information of the deep-level defects in the wafer to be detected. The method for detecting deep-level defect states in a large-size wafer according to the present invention can solve the problems that the existing measurement technology cannot accurately detect the defect states of deep levels in a large-size wafer, and it is also difficult to detect the concentration and energy level position of the defect states.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for detecting deep-level defect states in large-size wafers. Background Art

[0002] Silicon is the main material for integrated circuits. With the continuous reduction of the semiconductor manufacturing process, higher and higher requirements are put forward for the quality and size of silicon. The wafers mainly have specifications such as 2 inches (50 mm), 3 inches (75 mm), 4 inches (100 mm), 6 inches (150 mm), 8 inches (200 mm), and 12 inches (300 mm). The larger the size (diameter) of the wafer, the more chips can be fabricated on each wafer, and the cost per unit chip is reduced.

[0003] During the crystal pulling process of silicon, some impurities or defects will inevitably be introduced, and these impurity defects will form defect state energy levels in the forbidden band. These deep-level defect states have an important impact on the performance of materials and devices. For example, if the deep-level defect states in the forbidden band capture electrons and cannot release them in time, it will seriously affect the reliability of silicon devices; therefore, it is necessary to sample and detect the defect states in the wafer during the wafer production process. However, the larger the size of the wafer, the higher the difficulty of detecting the deep-level defect states.

[0004] Taking the 300-mm large-size wafer as an example, the means for defect characterization include: SEM detection after HCl etching, etching and development after copper modification, morphological characterization after thermal oxidation, transient capacitance detection methods, etc. However, these characterization methods cannot accurately detect the defect states with deeper energy levels, and it is also difficult to measure the concentration and energy level positions.

[0005] Taking the traditional transient capacitance detection method as an example, during measurement, a Schottky junction is formed with one surface of the wafer to be detected, and an ohmic junction is formed with the other surface to form a Schottky diode structure. The leakage current of this Schottky diode is large, and the transient capacitance voltage will be quickly released through the leakage current, and a complete transient capacitance spectrum curve cannot be formed; moreover, the large leakage current also affects the magnitude of the measurement voltage during measurement and the temperature range during measurement, and deeper energy level defects cannot be accurately detected.

[0006] Therefore, how to accurately detect the energy level positions and concentrations of deep-level defects through an effective measurement method is of great significance for studying the influence of deep-level defects on 300-mm large-size wafer materials and devices. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for detecting deep-level defect states in large-sized wafers, which is used to solve the problems that the existing energy-level defect state measurement technology for large-sized wafers cannot accurately detect the deep-level defect states in the wafers, and it is also difficult to detect the concentration and energy-level positions of the defect states.

[0008] To achieve the above object and other related objects, the present invention provides a method for detecting deep-level defect states in large-sized wafers, and the detection method includes the following steps:

[0009] The detection method includes the following steps:

[0010] Provide a wafer to be detected;

[0011] Etch the bottom surface of the wafer to be detected to form a plurality of non-connected etched areas. The unetched areas on the bottom surface of the wafer to be detected are divided into a plurality of unetched areas by the etched areas. The surface roughness of the etched areas is greater than that of the unetched areas;

[0012] Form a bottom metal layer on the bottom surface of the wafer to be detected. Among them, the bottom metal layer located in the etched area is in ohmic contact with the wafer to be detected, and the bottom metal layer located in the unetched area is in Schottky contact with the wafer to be detected;

[0013] Form a patterned top metal layer on the top surface of the wafer to be detected. Among them, the top metal layer is in Schottky contact with the wafer to be detected;

[0014] Measure the deep-level transient capacitance spectrum curve of the wafer to be detected, make an Arrhenius curve using the deep-level transient capacitance spectrum curve, and obtain the energy-level position and concentration information of the deep-level defects of the wafer to be detected therefrom.

[0015] Optionally, define N of the etched areas and K of the unetched areas adjacent thereto as a test group, and the bottom metal layers covered on each test group are not connected to each other; where N is an integer greater than or equal to 1, and K is an integer greater than or equal to 1.

[0016] Optionally, the etched areas are strip-shaped, and the width of each etched area is between 0.01 mm and 1 mm.

[0017] Optionally, the bottom metal layer located in the unetched area is in contact with the wafer to be detected to form a bottom Schottky junction, and the top metal layer is in contact with the wafer to be detected to form a top Schottky junction. The barrier height of the bottom Schottky junction is different from the barrier height of the top Schottky junction.

[0018] Optionally, the diameter of the wafer to be detected is greater than or equal to 300 mm.

[0019] Optionally, the method for obtaining the energy level position and concentration information of the deep-level defects of the wafer to be detected includes:

[0020] Providing a deep-level transient spectroscopy test device;

[0021] Setting the test voltage of the deep-level transient spectroscopy test device to be less than the turn-on voltage of the top Schottky junction of the wafer to be detected, and measuring a majority-carrier trap deep-level transient capacitance spectrum curve based on the deep-level transient spectroscopy test device;

[0022] Setting the test voltage of the deep-level transient spectroscopy test device to be greater than the turn-on voltage of the top Schottky junction of the wafer to be detected, and measuring a deep-level transient capacitance spectrum curve common to minority-carrier traps and majority-carrier traps based on the deep-level transient spectroscopy test device;

[0023] Performing envelope analysis on the majority-carrier trap deep-level transient capacitance spectrum curve and the deep-level transient capacitance spectrum curve common to minority-carrier traps and majority-carrier traps to obtain a minority-carrier trap deep-level transient capacitance spectrum curve;

[0024] Using the majority-carrier trap deep-level transient capacitance spectrum curve and the minority-carrier trap deep-level transient capacitance spectrum curve to plot an Arrhenius curve, and obtaining the energy level position and concentration information of the deep-level defects of the wafer to be detected therefrom.

[0025] Optionally, the Arrhenius curve satisfies the following equation:

[0026]

[0027] In the formula, e n is the thermal emission rate of electrons emitted from the deep level, T is the temperature, K is a constant, σ n is the capture cross section, E C is the conduction band energy level, E T is the defect state energy level, and k is the Boltzmann constant.

[0028] Optionally, performing temperature scanning on the wafer to be detected at different temperatures, and measuring a deep-level transient capacitance spectrum curve of the distribution of deep-level defects with temperature; wherein, the temperature ranges from 50K to 500K.

[0029] Optionally, in the step of measuring the deep-level transient capacitance spectrum curve common to minority-carrier traps and majority-carrier traps, the test voltage ranges from 2V to 10V.

[0030] As described above, a method for detecting deep-level defect states in a large-sized wafer according to the present invention forms ohmic contacts and Schottky contacts on the bottom surface of the wafer to be detected, and forms Schottky contacts on the top surface of the wafer to be detected. The top Schottky junctions and bottom Schottky junctions located on the two surfaces respectively form a double Schottky diode structure. The leakage current of the double Schottky diode structure is low, enabling the measurement method of the present invention to measure deeper-level defect states; and the low leakage current also enables the measurement method of the present invention to measure at a higher measurement voltage, reducing the interference of low-level defect states on the measurement results; at the same time, the low leakage current broadens the measurement temperature range during measurement, making the electron excitation probability in deep-level defects higher, and enabling more accurate information about the concentration and energy level position of deep-level defect states to be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It shows a schematic flow chart of the method for detecting deep-level defect states in the large-sized wafer according to the present invention.

[0032] Figure 2 It shows a schematic structural diagram of the wafer to be detected according to the present invention.

[0033] Figure 3 It shows a schematic structural diagram of the wafer to be detected after forming an etched area and an unetched area according to the present invention.

[0034] Figure 4 It shows a schematic structural diagram of the wafer to be detected after forming a bottom metal layer according to the present invention.

[0035] Figure 5 It shows a schematic structural diagram of the wafer to be detected after forming a patterned top metal layer according to the present invention.

[0036] Figure 6 It shows a deep-level transient capacitance spectrum curve obtained by detecting using the traditional transient capacitance detection method in Comparative Example 1.

[0037] Figure 7 It shows a deep-level transient capacitance spectrum curve obtained by detecting using the detection method of the present invention in Comparative Example 1.

[0038] Figure 8 It shows an Arrhenius curve made by detecting using the detection method of the present invention in Comparative Example 1.

[0039] Figure 9 It shows a deep-level transient capacitance spectrum curve obtained by detecting using the traditional transient capacitance detection method in Comparative Example 2.

[0040] Figure 10 It shows a deep-level transient capacitance spectrum curve obtained by detecting using the detection method of the present invention in Comparative Example 2.

[0041] Figure 11 Shown is the Arrhenius curve obtained by using the detection method of the present invention in Comparative Example 2.

[0042] Description of Component Labels

[0043] 100 Wafer to be detected

[0044] 110 Bottom surface

[0045] 111 Etching area

[0046] 112 Unetched area

[0047] 120 Top surface

[0048] 200 Bottom surface metal layer

[0049] 201 Bottom surface ohmic junction

[0050] 202 Bottom surface Schottky junction

[0051] 300 Patterned top surface metal layer

[0052] 301 Top surface Schottky junction Detailed Implementation Modes

[0053] The following specific examples illustrate the implementation modes of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0055] For convenience of description, spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "on", etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers. As used herein, "between... and..." means including the endpoint values.

[0056] In the context of the present application, the structure in which the described first feature is "above" the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0057] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0058] Refer to Figure 1 , this embodiment provides a method for detecting deep-level defect states in large-size wafers, and the detection method includes steps 1) to 5).

[0059] Step 1): As Figure 2 shown, provide a wafer 100 to be detected.

[0060] In this embodiment, the material of the wafer 100 to be detected is silicon, its bandgap is only 1.1 eV, and the critical breakdown field strength is 0.3 MV / cm. Silicon is a narrow-bandgap material, and this detection method belongs to the detection of deep-level defect states in narrow-bandgap materials.

[0061] Specifically, the diameter of the wafer 100 to be detected is greater than or equal to 300 mm.

[0062] In this embodiment, the larger the size of the wafer 100 to be detected, the more difficult it is to characterize the defect states in its material. The size of the wafer to be detected applicable to the detection method in this embodiment is at least greater than or equal to 300 mm.

[0063] Step 2): Etch a plurality of non-connected etch regions 111 on the bottom surface 110 of the wafer 100 to be detected. The unetched regions on the bottom surface 110 of the wafer to be detected are separated by the etch regions into a plurality of unetched regions 112, and the surface roughness of the etch regions 111 is greater than the surface roughness of the unetched regions 112.

[0064] In this embodiment, as Figure 3 shown, define one of the surfaces of the wafer 100 to be detected as the bottom surface 110 and the other surface as the top surface 120; the bottom surface 110 is etched using an etching process to form etch pits, so that the surface roughness of the etch regions 111 is greater than that of the unetched regions 112. The etching process method used can be wet chemical etching, capacitively coupled plasma etching, inductively coupled plasma etching, and mechanical physical etching, etc.

[0065] Specifically, the etching region 111 is in a strip shape, and the width of each etching region 111 is between 0.01 mm and 1 mm.

[0066] In this embodiment, on the left and right sides of each etching region 111 are respectively an unetched region 112 (the unetched region is also in a strip shape). On the left and right sides of the unetched region 112 are respectively an etching region 111. The etching regions 111 and the unetched regions 112 are spaced apart from each other and arranged in an array. The width of each etching region and each unetched region is between 0.01 mm and 1 mm. The depth of the pits etched in the etching region is between 100 nm and 10 μm.

[0067] Step 3): As Figure 4 shown, a bottom metal layer 200 is formed on the bottom surface 110 of the wafer 100 to be detected. Among them, the bottom metal layer 200 located in the etching region 111 is in ohmic contact with the wafer 100 to be detected, and the bottom metal layer 200 located in the unetched region 112 is in Schottky contact with the wafer 100 to be detected.

[0068] In this embodiment, the bottom metal layer 200 located in the etching region 111 contacts the wafer 100 to be detected to form a bottom ohmic junction 201, and the bottom metal layer 200 located in the unetched region 112 contacts the wafer 100 to be detected to form a bottom Schottky junction 202. Among them, the method for forming the bottom metal layer 200 may include, but is not limited to, methods such as magnetron sputtering, molecular beam epitaxy, and electron beam evaporation. The thickness of the formed bottom metal layer 200 is between 50 nm and 1000 nm, and its material may include, but is not limited to, Au, Ag, Al, Ti, Ni, W, TiN, Cu, and alloys of these metals.

[0069] Specifically, N etching regions 111 and K unetched regions 112 adjacent to them are defined as a test group, and the bottom metal layers 200 covered on each test group are not connected to each other; where N is an integer greater than or equal to, and K is an integer greater than or equal to.

[0070] In this embodiment, the bottom metal layer 200 can be etched, and the etched bottom metal layer 200 is divided into different regions, and different regions are not connected to each other to achieve isolation; or in the step of forming the bottom metal layer 200, a mask layer can be used to cover the bottom metal layer above the test group, and no bottom metal layer or an isolation wall structure is formed in the interval regions between each test group to achieve isolation.

[0071] Step 4): As Figure 5As shown, a patterned top metal layer 300 is formed on the top surface 120 of the wafer 100 to be detected. Among them, a Schottky contact is formed between the top metal layer 300 and the wafer 100 to be detected.

[0072] In this embodiment, the patterned top metal layer 300 contacts the wafer 100 to be detected to form a plurality of non-connected top Schottky junctions 301. The plurality of top Schottky junctions 301 are arranged in an array and correspond to the test groups on the bottom surface of the wafer to be detected up and down. As Figure 5 shown, each top Schottky junction 301 corresponds to at least one test group. The bottom Schottky junction 202 in the test group, the silicon material, and the top Schottky junction 301 together form a double Schottky contact diode with a three-layer structure. The double Schottky contact diode structure can effectively reduce the leakage current generated during measurement. Moreover, each top Schottky junction 301 and its corresponding test group together constitute a detection area. Measuring different detection areas can obtain the deep-level defects in different areas of the wafer 100 to be detected. Among them, the method of patterning the top metal layer 300 sequentially includes a coating process, a coating process, an exposure process, and an etching process.

[0073] Specifically, the barrier heights of the bottom Schottky junction 202 and the top Schottky junction 301 can be the same or different. When the barrier heights of the bottom Schottky junction 202 and the top Schottky junction 301 are different, the turn-on voltages of the Schottky junctions on both sides are different, and the higher turn-on voltage of the Schottky junction makes the set value of the test voltage during testing higher.

[0074] In this embodiment, the barrier height of the bottom Schottky junction 201 is different from the barrier height of the top Schottky junction 301. As an example, the barrier height of the bottom Schottky junction 201 can be made different from the barrier height of the top Schottky junction 301 by selecting different metal materials, or the barrier height of the bottom Schottky junction 201 can be made different from the barrier height of the top Schottky junction 301 by doping. Preferably, different metals are selected for the bottom metal layer and the top metal layer so that the barrier height of the bottom Schottky junction 201 is different from the barrier height of the top Schottky junction 301.

[0075] Step 5): Measure the deep-level transient capacitance spectrum curve of the wafer 100 to be detected, and use the deep-level transient capacitance spectrum curve to make an Arrhenius curve to obtain the energy level position and concentration information of the deep-level defects of the wafer 100 to be detected.

[0076] In this embodiment, during measurement, the bottom Schottky junction 202 and the bottom ohmic junction 201 in the bottom metal layer 200 are grounded, and the top Schottky junction 301 in the top metal layer 300 is connected to the test voltage interface. The double Schottky contact diode structure can effectively reduce the leakage current generated during measurement. The grounded bottom ohmic junction 201 can ensure that the change in the measured capacitance value during measurement is caused by deep-level defects. The deep-level transient capacitance spectrum can be measured by methods such as standard deep-level transient capacitance spectrum, Laplace transform deep-level transient capacitance spectrum, Fourier transform deep-level transient capacitance spectrum, constant capacitance deep-level transient voltage spectrum, double-pulse deep-level transient capacitance spectrum, etc.

[0077] Specifically, the method for obtaining the energy level position and concentration information of the deep-level defects of the to-be-detected wafer 100 includes: step 51) to step 55).

[0078] Step 51): Provide a deep-level transient spectrum test device.

[0079] In this embodiment, the deep-level transient spectrum test device can be a deep-level transient spectrum tester or an electrical probe station. During measurement, temperature scanning is performed on the to-be-detected wafer at different temperatures, and the deep-level transient capacitance spectrum curve of the deep-level defects with respect to temperature distribution is measured; among them, the lowest temperature for scanning should be ≥50K, and the highest temperature for scanning should be ≤500K.

[0080] Step 52): Set the test voltage of the deep-level transient spectrum test device to be less than the turn-on voltage of the top Schottky junction 301 of the to-be-detected wafer 100, and measure the majority carrier trap deep-level transient capacitance spectrum curve based on the deep-level transient spectrum test device.

[0081] In this embodiment, after the metal material of the top metal layer 300 is selected, the Schottky junction turn-on voltage at different temperatures can be calculated through its barrier height with the silicon material, and further the temperature range during measurement can be selected. Set the test voltage to be less than the turn-on voltage (the Schottky junction turn-on voltage corresponding to the highest measurement temperature), and measure the majority carrier trap deep-level transient capacitance spectrum curve.

[0082] Moreover, because the bottom Schottky junction 202, the silicon material, and the top Schottky junction 301 form a double Schottky contact diode structure with small leakage current, during high-temperature interval testing (the magnitude of the leakage current is positively correlated with the temperature magnitude), the potential between the capacitor plates formed at both ends of the to-be-detected wafer drops slowly, making the formed capacitance spectrum curve complete; moreover, the higher the temperature, the higher the probability that electrons in deeper-level defect states are excited, and the more accurately the deep-level defect states can be measured.

[0083] Step 53): Set the test voltage of the deep level transient spectroscopy test device to be greater than the turn-on voltage of the Schottky junction 301 on the top surface of the wafer 100 to be detected, and measure the deep level transient capacitance spectrum curve common to the minority carrier traps and the majority carrier traps based on the deep level transient spectroscopy test device.

[0084] In this embodiment, set the test voltage to be greater than the turn-on voltage (the turn-on voltage of the Schottky junction corresponding to the lowest measurement temperature); because the bottom Schottky junction 202, the silicon material, and the top Schottky junction 301 form a double Schottky contact diode structure with a small leakage current, during measurement, when the test voltage is set to be relatively large, the potential between the capacitor plates formed at both ends of the wafer to be detected can be maintained in the high voltage range for a longer time, and deep level information can be obtained better (eliminating the interference of shallow level information). As an example, in the step of measuring the deep level transient capacitance spectrum curve common to the minority carrier traps and the majority carrier traps, the test voltage is between 2V and 10V (including both end values).

[0085] Step 54): Perform envelope analysis on the deep level transient capacitance spectrum curve of the majority carrier traps and the deep level transient capacitance spectrum curve common to the minority carrier traps and the majority carrier traps to obtain the deep level transient capacitance spectrum curve of the minority carrier traps.

[0086] Step 55): Use the deep level transient capacitance spectrum curve of the majority carrier traps and the deep level transient capacitance spectrum curve of the minority carrier traps to plot an Arrhenius curve, and obtain the energy level position and concentration information of the deep level defects of the wafer 100 to be detected therefrom.

[0087] Specifically, the Arrhenius curve satisfies the following equation:

[0088]

[0089] In the formula, e n is the thermal emission rate of electrons from the deep level, T is the temperature, K is a constant, σ n is the capture cross-section, E C is the conduction band energy level, E T is the defect state energy level, and k is the Boltzmann constant.

[0090] In this embodiment, the energy level position of the defect state can be obtained by using the slope of the Arrhenius curve, the capture cross-section of the defect state can be obtained from the intercept, and the concentration of the defect state can be obtained from the peak intensity of the deep level transient capacitance spectrum.

[0091] To better demonstrate the beneficial effects of the method for detecting deep level defect states in a large-sized wafer described in this embodiment, this embodiment also provides two comparative examples for illustration.

[0092] Comparative Example 1

[0093] In this comparative example: The size of the wafer 100 to be detected is 300 mm.

[0094] Using the traditional transient capacitance detection method, a top surface metal Ni layer with a thickness of 100 nm is formed on the upper surface of the wafer 100 to be detected. The top surface metal Ni layer is in Schottky contact with the silicon material. After the entire lower surface of the wafer 100 to be detected is etched, a bottom surface metal AL layer with a thickness of 100 nm is formed. The bottom surface metal Ni layer is in ohmic contact with the silicon material. The measurement is carried out by the standard deep level transient capacitance spectroscopy technique. The applied measurement voltages are 0.2 V and 5 V respectively. The temperature scanning range during measurement is 50 K to 300 K. Two measurements are carried out using the two parameters of 264 Hz and 352 Hz. The deep level transient capacitance spectroscopy curves of the wafer 100 to be detected obtained from the two measurements are as Figure 6 shown. Its signal curve is irregular and has large fluctuations, and the Arrhenius curve cannot be obtained from this test curve;

[0095] Using the detection method of deep level defect states provided in this embodiment, the top surface metal layer 300 uses metal Ni with a thickness of 100 nm, and the width of each top surface electrode 301 is 1 mm; the bottom surface metal layer 200 uses metal AL with a thickness of 100 nm, the width of the bottom surface ohmic junction is 0.1 mm, and the width of the bottom surface Schottky junction 202 is 0.1 mm; each top surface Schottky junction 301 corresponds to 5 bottom surface ohmic junctions and 5 bottom surface Schottky junctions 202. The temperature scanning range during measurement is 50 K to 300 K. The applied measurement voltages are 0.2 V and 5 V respectively. Two measurements are carried out using the two parameters of 264 Hz and 352 Hz. The deep level transient capacitance spectroscopy curves of the wafer 100 to be detected obtained from the two measurements are as Figure 7 shown, showing a regular deep level signal curve, and the Arrhenius curve can be calculated therefrom (as Figure 8 shown).

[0096] Comparative Example 2

[0097] In this comparative example: The size of the wafer 100 to be detected is 300 mm.

[0098] Using the traditional transient capacitance detection method, a top surface metal Ni layer with a thickness of 150 nm is formed on the upper surface of the wafer 100 to be detected. The top surface metal Ni layer is in Schottky contact with the silicon material. After the entire lower surface of the wafer 100 to be detected is etched, a bottom surface metal AL layer with a thickness of 150 nm is formed. The bottom surface metal AL layer is in ohmic contact with the silicon material. The measurement is carried out by the standard deep level transient capacitance spectroscopy technique. The applied measurement voltages are 0.2 V and 6 V respectively. The temperature scanning range during measurement is 50 K to 300 K. Two measurements are carried out using the two parameters of 176 Hz and 264 Hz. The deep level transient capacitance spectroscopy curves of the wafer 100 to be detected obtained from the two measurements are asFigure 9 As shown, its signal curve is irregular, with large fluctuations in the curve, and the Arrhenius curve cannot be obtained from this test curve;

[0099] Using the detection method for deep-level defect states provided in this embodiment for detection, the top metal layer 300 uses metal Ni with a thickness of 150 nm, and the width of each top electrode 301 is 1 mm; the bottom metal layer 200 uses metal AL with a thickness of 150 nm, the width of the bottom ohmic contact is 0.1 mm, and the width of the bottom Schottky junction 202 is 0.1 mm; each top Schottky junction 301 corresponds to 5 bottom ohmic contacts and 5 bottom Schottky junctions 202. During measurement, the temperature scanning range is 50 K to 300 K, and the applied measurement voltages are 0.2 V and 6 V respectively. Two measurements are performed using the two parameters of 176 Hz and 264 Hz. The deep-level transient capacitance spectra curves of the wafer 100 to be detected in the two measurements are as Figure 10 shown, and moreover, even when the test frequency (352 Hz) is increased, a regular deep-level signal curve can still be obtained, and based on this, the Arrhenius curve can be calculated (as Figure 11 shown).

[0100] In summary, for the detection method of deep-level defect states in a large-size wafer of the present invention, by forming an ohmic contact and a Schottky contact on the bottom surface of the wafer to be detected, and forming a Schottky contact on the top surface of the wafer to be detected, the top Schottky junction and the bottom Schottky junction located on the two surfaces together form a double Schottky diode structure. The leakage current of the double Schottky diode structure is low, enabling the measurement method of the present invention to measure defect states at deeper energy levels; and the low leakage current also enables the measurement method of the present invention to perform measurements at a higher measurement voltage, reducing the interference of low-level defect states on the measurement results; at the same time, the low leakage current broadens the measurement temperature range during measurement, making the electron excitation probability in deep-level defects higher, and enabling more accurate information about the concentration and energy level position of deep-level defect states to be obtained. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0101] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A detection method for deep-level defect states in large-size wafers, characterized in that, The detection method includes the following steps: Provide a wafer to be detected; Etch the bottom surface of the wafer to be detected to form a plurality of non-connected etched regions. The unetched regions on the bottom surface of the wafer to be detected are divided into a plurality of unetched regions by the etched regions. The surface roughness of the etched regions is greater than that of the unetched regions; Form a bottom metal layer on the bottom surface of the wafer to be detected. Among them, the bottom metal layer located in the etched region is in ohmic contact with the wafer to be detected, and the bottom metal layer located in the unetched region is in Schottky contact with the wafer to be detected; Form a patterned top metal layer on the top surface of the wafer to be detected. Among them, the top metal layer is in Schottky contact with the wafer to be detected; Measure the deep level transient capacitance spectrum curve of the wafer to be detected, use the deep level transient capacitance spectrum curve to make an Arrhenius curve, and obtain the energy level position and concentration information of the deep level defects of the wafer to be detected from it.

2. The detection method of deep-level defect states in large-size wafers according to claim 1, wherein Define N of the etched regions and K unetched regions adjacent to them as a test group, and the bottom metal layers covered on each test group are not connected to each other; where N is an integer greater than or equal to 1, and K is an integer greater than or equal to 1.

3. The detection method of deep-level defect states in large-size wafers according to claim 1 or 2, characterized in that, The etched regions are strip-shaped, and the width of each etched region is between 0.01 mm and 1 mm.

4. The detection method of deep-level defect states in large-size wafers according to claim 1, characterized in that The bottom metal layer located in the unetched region contacts the wafer to be detected to form a bottom Schottky junction, the top metal layer contacts the wafer to be detected to form a top Schottky junction, and the barrier height of the bottom Schottky junction is different from the barrier height of the top Schottky junction.

5. The detection method of deep-level defect states in large-size wafers according to claim 1, wherein, The diameter of the wafer to be detected is greater than or equal to 300 mm.

6. The detection method of deep-level defect states in large-size wafers according to claim 1, wherein, The method for obtaining the energy level position and concentration information of the deep level defects of the wafer to be detected includes: Provide a deep level transient spectroscopy test device; Set the test voltage of the deep level transient spectroscopy test device to be less than the turn-on voltage of the top Schottky junction of the wafer to be detected, and measure the deep level transient capacitance spectrum curve of the majority carrier trap based on the deep level transient spectroscopy test device; Set the test voltage of the deep level transient spectroscopy test device to be greater than the turn-on voltage of the top Schottky junction of the wafer to be detected, and measure the deep level transient capacitance spectrum curve common to the minority carrier trap and the majority carrier trap based on the deep level transient spectroscopy test device; Perform envelope analysis on the deep level transient capacitance spectrum curve of the majority carrier trap and the deep level transient capacitance spectrum curve common to the minority carrier trap and the majority carrier trap to obtain the deep level transient capacitance spectrum curve of the minority carrier trap; Use the deep level transient capacitance spectrum curve of the majority carrier trap and the deep level transient capacitance spectrum curve of the minority carrier trap to make an Arrhenius curve, and obtain the energy level position and concentration information of the deep level defects of the wafer to be detected from it.

7. The detection method of deep-level defect states in large-size wafers according to claim 6, characterized in that, The Arrhenius curve satisfies the following equation: where, e n is the thermal emission rate of electrons emitted from deep energy levels, T is the temperature, K is a constant, σ n is the capture cross section, E C is the conduction band energy level, E T is the defect state energy level, and k is the Boltzmann constant.

8. The detection method of deep-level defect states in large-size wafers according to claim 6, characterized in that, Perform temperature scanning on the wafer to be detected at different temperatures, and measure the deep level transient capacitance spectrum curve of the deep level defects varying with temperature; where the temperature is between 50 K and 500 K.

9. The detection method of deep energy level defect states in large-sized wafers according to claim 6, wherein In the steps of measuring the deep level transient capacitance spectra curves of both minority carrier traps and majority carrier traps, the test voltage is between 2V and 10V.

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