Camera device and electronic equipment

Abstract

The present disclosure relates to an imaging device and an electronic device. A imaging device that is easy to perform pooling processing is provided. In the imaging device, a pixel area includes a plurality of pooling modules and an output circuit, the pooling module includes a pooling circuit and a comparison module, the pooling circuit includes a plurality of pixels and an operation circuit, and the comparison module includes a plurality of comparison circuits and a determination circuit. The pixel can obtain a first signal through photoelectric conversion, and multiply the first signal at an arbitrary magnification to generate a second signal. The pooling circuit generates a third signal by adding a plurality of second signals through an operation circuit, and the comparison module outputs the largest third signal to the determination circuit by comparing the plurality of third signals. The determination circuit has a function of determining the largest third signal and binarizing it, and generates a fourth signal. The pooling module performs pooling processing according to the number of pixels, and outputs the data subjected to the pooling processing.

Description

[0001] This application is a divisional application of the application filed on June 5, 2018, with PCT application number PCT / IB2018 / 053999, which entered the Chinese national phase on December 12, 2019, with national application number 201880039316.8, and invention name “Camera device and electronic equipment” Technical Field

[0002] One embodiment of the present invention relates to an imaging device and an electronic device.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, a method, or a manufacturing method. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

[0004] In addition, in this specification, etc., a semiconductor device refers to an element, circuit, or device that can work by utilizing semiconductor characteristics. As an example, semiconductor elements such as transistors and diodes are semiconductor devices. As another example, a circuit including a semiconductor element is a semiconductor device. As another example, a device having a circuit including a semiconductor element is a semiconductor device. Background Art

[0005] With the development of information technologies such as IoT (Internet of Things) and AI (Artificial Intelligence), the amount of data to be processed tends to increase. In order to use information technologies such as IoT and AI in electronic devices, it is necessary to manage a large amount of data in a distributed manner.

[0006] In image processing systems for vehicle-mounted electronic devices and image processing systems for monitoring moving objects, attention has been paid to improving the speed of image recognition processing using AI. For example, Patent Document 1 discloses a technique for providing a camera with a computing function.

[0007] [Prior technical literature]

[0008] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2016-123087 Summary of the invention

[0010] Technical problem to be solved by the invention

[0011] As technology develops, it is possible to easily capture high-quality images in an imaging device including a solid-state imaging element such as a CMOS image sensor. It is required that a higher-intelligence function be installed in the next-generation imaging device.

[0012] In order to identify objects from image data, advanced image processing is required. In advanced image processing, various analysis processes such as filtering and comparison operations are used to analyze images. In the analysis process used for image processing, the more pixels are processed, the more operations are required, and the more operations are required, the longer the processing time is. For example, in vehicle-mounted image processing systems, there is a problem that the increase in processing time affects safety. In addition, in image processing systems, there is a problem that the more operations are required, the greater the power consumption.

[0013] In view of the above problems, one of the purposes of one embodiment of the present invention is to provide a camera device with a novel structure. In addition, one of the purposes of one embodiment of the present invention is to provide a camera device with a pooling processing function of a neural network. In addition, one of the purposes of one embodiment of the present invention is to provide a camera device with a novel structure capable of suppressing the amount of calculation and shortening the processing time. In addition, one of the purposes of one embodiment of the present invention is to provide a camera device with a novel structure capable of reducing power consumption.

[0014] Note that the recording of these purposes does not prevent the existence of other purposes. In addition, one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes are obvious from the description of the specification, drawings, claims, etc., and can be extracted from the description of the specification, drawings, claims, etc.

[0015] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purpose does not prevent the existence of other purposes. In addition, other purposes are purposes that are not mentioned above but will be described in the following description. A person skilled in the art can derive and appropriately extract the purpose not mentioned above from the description of the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above-mentioned descriptions and / or other purposes.

[0016] Solutions to technical problems

[0017] One embodiment of the present invention is a camera device including a pixel area and a first circuit, wherein the pixel area includes a pooling module and an output circuit, the pooling module includes multiple pooling circuits and a comparison module, the pooling circuit includes multiple pixels and an operation circuit, the comparison module includes multiple comparison circuits and a determination circuit, the pixel has a function of obtaining a first signal through photoelectric conversion, the pixel has a function of multiplying the first signal at an arbitrary magnification to generate a second signal, the pooling circuit has a function of adding multiple second signals through an operation circuit to generate a third signal, the comparison module has a function of selecting the largest third signal by comparing multiple third signals and outputting it to the determination circuit, the determination circuit has a function of determining the largest third signal and binarizing it to generate a fourth signal, the first circuit controls the timing of outputting the fourth signal to the output circuit, the pooling module performs pooling processing according to the number of pixels, and the pooling module outputs the fourth signal generated by the pooling processing.

[0018] In the camera device of the above structure, it is preferred that it further includes a second circuit, a third circuit, a first wiring, a second wiring and a third wiring, wherein the pixel includes a first output terminal, the operation circuit includes a first transistor, a second transistor and a third transistor, the second circuit is electrically connected to a plurality of pixels extending in a row direction through the first wiring, the third circuit is electrically connected to a plurality of pixels extending in a column direction through the second wiring, the third wiring is electrically connected to one of the source and the drain of the first transistor, one of the source and the drain of the second transistor and one of the source and the drain of the third transistor, and the gate of the first transistor is electrically connected to the other of the source and the drain of the first transistor and the gate of the second transistor , the gate of the third transistor and the first output terminal of the pixel included in the pooling circuit, the third circuit has a function of outputting a selection signal to the second wiring, the second circuit has a function of setting the pixel to an arbitrary magnification through the first wiring, the first transistor has the same channel length as the second transistor and the third transistor, the second transistor has a function of outputting a third signal that adds multiple second signals by having the same width as the channel width of the first transistor, and the third transistor has a length obtained by dividing the channel width of the first transistor by the number of pixels included in the pooling circuit, thereby having a function of outputting a fifth signal of a size obtained by dividing the size of the third signal by the number of pixels.

[0019] In the camera device of the above structure, preferably, the comparison module includes a first comparison circuit, a second comparison circuit and a current mirror circuit, the first comparison circuit includes fourth to ninth transistors, a first input terminal, a second input terminal, a second output terminal and a fourth wiring, the second output terminal of the first comparison circuit is electrically connected to the first input terminal of the second comparison circuit through the current mirror circuit, the first input terminal is electrically connected to one of the source and drain of the fifth transistor, one of the source and drain of the seventh transistor, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor, the second input terminal is electrically connected to one of the source and drain of the eighth transistor, one of the source and drain of the sixth transistor, the gate of the seventh transistor, the gate of the eighth transistor and the gate of the ninth transistor, the second output terminal is electrically connected to one of the source and drain of the fourth transistor and one of the source and drain of the ninth transistor, the fourth to ninth transistors have the same channel length, and the channel width of the fourth transistor is preferably the same as the channel width of the fifth transistor. The channel width of the sixth transistor is preferably twice that of the fifth transistor, the fourth to sixth transistors form a first current mirror circuit, the channel width of the ninth transistor is preferably the same as the channel width of the eighth transistor, the channel width of the seventh transistor is preferably twice that of the eighth transistor, the seventh to ninth transistors form a second current mirror circuit, the first input terminal of the first comparison circuit is supplied with the sixth signal, the second input terminal of the first comparison circuit is supplied with the seventh signal, the second output terminal of the first comparison circuit outputs the larger one of the sixth signal and the seventh signal as the eighth signal, the first input terminal of the second comparison circuit is supplied with the eighth signal, the second input terminal of the second comparison circuit is supplied with the ninth signal, the second output terminal of the second comparison circuit outputs the larger one of the eighth signal and the ninth signal as the tenth signal to the determination circuit, the determination circuit has a function of determining the tenth signal and binarizing it, and generating the fourth signal, and the first circuit has a function of controlling the timing of outputting the fourth signal to the output circuit.

[0020] In the imaging device having the above configuration, it is preferable that the plurality of pixels are arranged in a matrix and that a light-shielded region exists between adjacent pixels.

[0021] In the camera device of the above structure, preferably, the pixel also includes a photoelectric conversion element, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor and a first capacitor, one electrode of the photoelectric conversion element is electrically connected to one of the source and the drain of the tenth transistor, the other of the source and the drain of the tenth transistor is electrically connected to one of the source and the drain of the eleventh transistor, one of the source and the drain of the eleventh transistor is electrically connected to the gate of the twelfth transistor, the gate of the twelfth transistor is electrically connected to an electrode of the first capacitor, one of the source and the drain of the twelfth transistor is electrically connected to the first output terminal, the other electrode of the first capacitor is electrically connected to one of the source and the drain of the thirteenth transistor, the other of the source and the drain of the thirteenth transistor is electrically connected to the first wiring, the gate of the thirteenth transistor is electrically connected to the second wiring, and the tenth transistor and the twelfth transistor contain metal oxide in the channel formation region.

[0022] In the imaging device having the above structure, the metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0023] In the imaging device having the above configuration, it is preferable that the photoelectric conversion element contains selenium or a compound containing selenium.

[0024] Effects of the Invention

[0025] In view of the above problems, one embodiment of the present invention can provide a camera device with a novel structure. In addition, one embodiment of the present invention can provide a camera device with a pooling processing function of a neural network. In addition, one embodiment of the present invention can provide a camera device with a novel structure that can suppress the amount of calculation and shorten the processing time. In addition, one of the purposes of one embodiment of the present invention is to provide a camera device with a novel structure that can reduce power consumption.

[0026] Note that the effects of one embodiment of the present invention are not limited to the above effects. The above effects do not prevent the existence of other effects. In addition, other effects are effects that are not mentioned above but will be described in the following description. A person skilled in the art can derive and appropriately extract the effects that are not mentioned above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above effects and / or other effects. Therefore, one embodiment of the present invention sometimes does not include the effects listed above depending on the circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] [ Figure 1 ]A block diagram illustrating a camera device.

[0028] [ Figure 2 ]A block diagram illustrating a camera device.

[0029] [ Figure 3 ](A) A block diagram illustrating an imaging device. (B) A circuit diagram illustrating an imaging device.

[0030] [ Figure 4 ]A circuit diagram illustrating a pixel.

[0031] [ Figure 5 ](A) A block diagram illustrating the imaging device. (B) A timing diagram illustrating the operation of the imaging device.

[0032] [ Figure 6 ]A block diagram illustrating a camera device.

[0033] [ Figure 7 ]A circuit diagram illustrating a pixel.

[0034] [ Figure 8 ]A diagram illustrating the structure of pixels of an imaging device.

[0035] [ Fig. 9 ]A diagram illustrating the structure of pixels of an imaging device.

[0036] [ Fig.10 ]A diagram illustrating the structure of pixels of an imaging device.

[0037] [ Fig.11 ](A) A diagram illustrating the structure of a pixel of an imaging device. (B) A cross-sectional view showing the structure of an imaging device.

[0038] [ Fig.12 ]A diagram illustrating the structure of pixels of an imaging device.

[0039] [ Fig.13 ]A diagram illustrating the structure of pixels of an imaging device.

[0040] [ Fig.14 ] A three-dimensional diagram of the package and module that accommodate the camera device.

[0041] [ Fig.15 ]A diagram showing a structural example of an electronic device. DETAILED DESCRIPTION

[0042] (Implementation Method 1)

[0043] In this embodiment, refer to Figures 1 to 7 An imaging device that efficiently performs pooling processing using a neural network is described.

[0044] First, refer to Figure 1A block diagram illustrating the camera device 10. The camera device 10 includes a pixel region, a driver 11, a driver 12, a driver 13, a plurality of wirings 111, a plurality of wirings 112 (not shown), and a plurality of wirings 113a (not shown). The pixel region includes a plurality of pooling modules 200, a plurality of analog-to-digital conversion circuits 250, and an output circuit 251. The pooling module 200 includes a plurality of pooling circuits 210 and a comparison module 220, and the pooling circuit 210 includes a plurality of pixels 100 and an operation circuit 212 (not shown). The comparison module 220 includes a plurality of comparison circuits 230 (not shown) and a determination circuit 221 (not shown).

[0045] The pixel 100 can convert light into an electrical signal to obtain a first signal, and the pixel 100 can multiply the first signal by an arbitrary magnification to generate a second signal. The first signal and the second signal are output as currents. The arbitrary magnification refers to the value of the weight data used for the pooling process of the neural network.

[0046] The pooling circuit 210 may generate the third signal by adding the plurality of second signals through the operation circuit 212. In addition, the operation circuit 212 may average the plurality of second signals to generate the fifth signal.

[0047] The comparison module 220 may select the largest third signal by comparing the plurality of third signals, and output the largest third signal to the determination circuit 221. The determination circuit 221 may determine the largest third signal and binarize it, and generate a fourth signal.

[0048] The pooling module 200 may perform pooling processing according to the number of pixels included in the pooling module 200. That is, the pooling module 200 may obtain a first signal from a plurality of pixels included in the pooling module 200, perform pooling processing on the first signal to generate a fourth signal, and output the fourth signal.

[0049] The driver 11 can control the timing of outputting the fourth signal to the output circuit 251 according to the selection signal supplied to the wiring 111. Although not shown in the figure, the output circuit 251 can output the fourth signal to the neural network that controls the camera device 10. When the first data is pooled using the camera device 10, data of the features of the extracted data is input to the neural network. Therefore, the neural network only needs to process the features of the extracted data, thereby reducing the amount of data to be processed. Therefore, the data transfer time from the camera element to the neural network is reduced, and the amount of calculation of the neural network can be reduced. By reducing the amount of calculation of the neural network, power consumption can be reduced.

[0050] The pooling module 200 preferably includes a plurality of pooling circuits 210 . Figure 1An example is shown in which the pooling module 200 includes four pooling circuits 210. The number of pooling circuits 210 included in the pooling module 200 can be greater than 1 and less than n (n is a natural number greater than 2). When there are multiple pooling circuits, it is easy to extract the characteristics of the data. In addition, when the number of pixels in the pooling circuit 210 increases, the compression rate of the data becomes higher, thereby reducing the amount of calculation of the neural network. Therefore, the power consumption of the neural network is further reduced.

[0051] exist Figure 2 , an example of a pooling circuit 210 is described with reference to a block diagram. The pooling circuit 210 includes a plurality of pixels 100, an operation circuit 212, a switch 203, a switch 204, a plurality of wirings 112, a plurality of wirings 113a, a wiring 114, a wiring 115, and a wiring 210a. The pixel 100 includes a first output terminal, and the operation circuit 212 includes a transistor 212a, a transistor 212b, and a transistor 212c. Note that the description Figure 2 The illustrated example of pooling circuit 210 includes four pixels.

[0052] The driver 12 is electrically connected to a plurality of pixels 100 extending in the row direction via a wiring 112 , and the driver 13 is electrically connected to a plurality of pixels 100 extending in the column direction via a wiring 113 a .

[0053] The wiring 114 is electrically connected to one of the source and drain of the transistor 212a, one of the source and drain of the transistor 212b, and one of the source and drain of the transistor 212c. The gate of the transistor 212a is electrically connected to the other of the source and drain of the transistor 212a, the gate of the transistor 212b, and the gate of the transistor 212c. The gate of the transistor 212a is also electrically connected to the output terminal 100a of the plurality of pixels 100 included in the pooling circuit 210.

[0054] The other of the source and drain of transistor 212b is electrically connected to one electrode of switch 203, and the other of the source and drain of transistor 212c is electrically connected to one electrode of switch 204. The other electrode of switch 203 is electrically connected to the other electrode of switch 204 and comparison module 220 via wiring 210a.

[0055] The driver 13 can output a selection signal to the wiring 113a. The driver 12 can set the pixel 100 to an arbitrary magnification as weight data through the wiring 112. The transistor 212a has the same channel length as the transistor 212b and the transistor 212c, and the transistor 212b has the same channel width as the transistor 212a, thereby outputting a third signal that adds multiple second signals. The transistor 212c has a channel width obtained by dividing the channel width of the transistor 212a by the number of pixels 100 included in the pooling circuit 210, thereby outputting a fifth signal of a size obtained by dividing the size of the third signal by the number of pixels 100. The third signal and the fifth signal are controlled by current. The switch 203 and the switch 204 are preferably in a complementary relationship.

[0056] The switch 203 and the switch 204 are controlled by a first switching signal supplied to the wiring 115 . Figure 2 An example is shown in which a p-channel transistor is used for the switch 203 and an n-channel transistor is used for the switch 204 .

[0057] When the first switching signal is “L”, the pooling circuit 210 may output the third signal to the comparison module 220 through the wiring 210 a .

[0058] When the first switching signal is “H”, the pooling circuit 210 may output the fifth signal to the comparison module 220 through the wiring 210 a .

[0059] For example, in an in-vehicle image processing system, it is necessary to instantly determine the surrounding conditions of a high-speed moving vehicle. Therefore, by using the camera device 10 having the pooling module 200 exclusively for detecting features from the image data, the amount of calculation can be suppressed and the processing time can be shortened.

[0060] Notice, Figure 2 An example of supplying different weight data to each pixel 100 included in the pooling circuit 210 is shown. In addition, weight data can be supplied to the pooling circuit 210 or the pooling module 200 as a unit. Therefore, the wiring 112 and the wiring 113a can be electrically connected to each other as a unit of the pooling circuit 210 or the pooling module 200. By reducing the wiring 112 and the wiring 113a, the integration of the imaging device 10 can be improved.

[0061] exist Figure 3In FIG. 2A , an example of a comparison module 220 is described with reference to a block diagram. The comparison module 220 includes a plurality of comparison circuits 230, a plurality of current mirror circuits 222, and a determination circuit 221. Each comparison circuit 230 includes an input terminal 231a, an input terminal 231b, and an output terminal 231c. The determination circuit 221 includes an input terminal 221a, an input terminal 221b, and an output terminal 221c. The current mirror circuit 222 includes an input terminal 224a and an output terminal 224b.

[0062] exist Figure 3 FIG. 2A shows an example in which output signals are supplied from four pooling circuits 210 to the comparison module 220. In addition, the comparison module 220 is electrically connected to four different pooling circuits 210 through wiring 210a(i, j) to wiring 210a(i+1, j+1). It is preferred to have a comparison circuit 230 according to the number of input signals. Figure 3 In the example shown in FIG. 2A , the comparison module 220 includes a comparison circuit 230 a , a comparison circuit 230 b , a comparison circuit 230 c , a current mirror circuit 222 a , a current mirror circuit 222 b , and a determination circuit 221 .

[0063] Next, a connection example of the comparison circuit 230a, the comparison circuit 230b, the comparison circuit 230c, the current mirror circuit 222a, the current mirror circuit 222b, and the determination circuit 221 is described. The input terminal 231a of the comparison circuit 230a is electrically connected to the wiring 210a(i, j), the input terminal 231b is electrically connected to the wiring 210a(i+1, j), the output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222a, and the output terminal 224b of the current mirror circuit 222a is electrically connected to the input terminal 231a of the comparison circuit 230b.

[0064] The input terminal 231b of the comparison circuit 230b is electrically connected to the wiring 210a(i, j+1), the output terminal 231c is electrically connected to the input terminal 224a of the current mirror circuit 222b, and the output terminal 224b of the current mirror circuit 222b is electrically connected to the input terminal 231a of the comparison circuit 230c. The input terminal 231b of the comparison circuit 230c is electrically connected to the wiring 210a(i+1, j+1), and the output terminal 231c is electrically connected to the input terminal 221a of the determination circuit 221.

[0065] The current mirror circuit 222 includes a transistor 223a and a transistor 223b. The transistor 223a and the transistor 223b are preferably p-channel transistors. One of the source and the drain of the transistor 223a is electrically connected to one of the source and the drain of the transistor 223b and the wiring 114. The gate of the transistor 223a is electrically connected to the other of the source and the drain of the transistor 223a and the gate of the transistor 223b.

[0066] The input terminal 231a of the comparison circuit 230a is supplied with the signal a1 through the wiring 210a(i, j). The input terminal 231b is supplied with the signal a2 through the wiring 210a(i+1, j). The larger one of the signal a1 and the signal a2 is output from the output terminal 231c as the signal a3, and the signal is supplied to the input terminal 224a of the current mirror circuit 222a. The signal a3 passes through the current mirror circuit 222a to become the signal b1 of the same magnitude as the signal a3, and the signal b1 is supplied to the output terminal 224b of the current mirror circuit. Therefore, the input terminal 231a of the comparison circuit 230b is supplied with the signal b1 of the same magnitude as the signal a3. Note that the directions of the signal a3 and the signal b1 are different.

[0067] The input terminal 231b of the comparison circuit 230b is supplied with the signal b2 through the wiring 210a(i, j+1), and the larger one of the signal b1 and the signal b2 is output from the output terminal 231c as the signal b3. The input terminal 231a of the comparison circuit 230c is supplied with the signal c1 through the current mirror circuit 222b, the input terminal 231b is supplied with the signal c2 through the wiring 210a(i+1, j+1), and the larger one of the signal c1 and the signal c2 is output from the output terminal 231c as the signal c3 to the determination circuit 221. Each of the signals a1, a2, a3, b1, b2, b3, c1, c2, and c3 is preferably an analog signal.

[0068] Therefore, the determination circuit 221 determines the signal c3 input to the input terminal 221a and binarizes it to generate a fourth signal, which can be output to the output terminal 221c. The driver 11 can control the timing of outputting the fourth signal to the output circuit 251 through the wiring 211 according to the selection signal supplied to the wiring 111.

[0069] exist Figure 3 FIG. 2B is a circuit diagram of the comparison circuit 230 . The comparison circuit 230 includes transistors 241 to 246 , an input terminal 231 a , an input terminal 231 b , an output terminal 231 c , and a wiring 232 .

[0070] The input terminal 231a is electrically connected to one of the source and drain of the transistor 242, one of the source and drain of the transistor 244, the gate of the transistor 241, the gate of the transistor 242, and the gate of the transistor 243. The input terminal 231b is electrically connected to one of the source and drain of the transistor 245, one of the source and drain of the transistor 243, the gate of the transistor 244, the gate of the transistor 245, and the gate of the transistor 246. The output terminal 231c is electrically connected to one of the source and drain of the transistor 241 and one of the source and drain of the transistor 246. The wiring 232 is electrically connected to the other of the source and drain of the transistors 241 to 246.

[0071] Furthermore, the transistors 241 to 246 have the same channel length.

[0072] In addition, the channel width of the transistor 241 is preferably the same as the channel width of the transistor 242, and the channel width of the transistor 243 is preferably twice the channel width of the transistor 242. The transistors 241 to 243 form a first current mirror circuit.

[0073] In addition, the channel width of the transistor 246 is preferably the same as the channel width of the transistor 245, and the channel width of the transistor 244 is preferably twice the channel width of the transistor 245. The transistors 244 to 246 form a second current mirror circuit.

[0074] Next, the operation of the comparison circuit 230 will be described. Note that the input terminal 231a and the input terminal 231b are supplied with current as analog signals, and the output terminal 231c sinks current as an analog signal. For example, when the signal input to the input terminal 231a is larger than the signal input to the input terminal 231b, the signal supplied to the input terminal 231b is absorbed by the transistor 243. As a different example, when the signal input to the input terminal 231b is larger than the signal input to the input terminal 231a, the signal input to the input terminal 231a is absorbed by the transistor 244. Therefore, the output terminal 231c can absorb a signal having the same magnitude as the larger one of the signals input to the input terminal 231a or the input terminal 231b through any one of the first current mirror circuit and the second current mirror circuit.

[0075] Note that when the magnitude of the input signals of the input terminal 231a and the input terminal 231b is the same, the magnitude of the signal absorbed by the transistor 242 and the transistor 245 is about half of the signal. Therefore, the output terminal 231c absorbs the signal of the magnitude obtained by combining the signals of the transistor 241 and the transistor 246. Thus, the output terminal 231c can absorb the signal of the same magnitude as the input terminal 231a and the input terminal 231b. The wiring 232 is preferably a low potential capable of absorbing the signal.

[0076] Therefore, in Figure 3 In the figure (A), as the signal c3, the largest signal among the signals a1, a2, b2, and c2 supplied to the comparison module 220 is supplied to the determination circuit 221. The determination circuit 221 can determine the signal c3 and binarize it, and generate a fourth signal. The driver 11 can supply the selection signal to the determination circuit 221 through the wiring 111 and output the determination result in the output circuit 251.

[0077] exist Figure 4 , an example of a pixel 100 is described with reference to a circuit diagram. The pixel 100 includes a photoelectric conversion element 101, a transistor 102, a transistor 103, a capacitor 104, a transistor 105, a transistor 106, and an output terminal 100a. In addition, the pixel 100 is electrically connected to a wiring 112, a wiring 113a, a wiring 113b, a wiring 117, a wiring 118, and a wiring 119.

[0078] One electrode of the photoelectric conversion element 101 is electrically connected to one of the source and drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to one of the source and drain of the transistor 103, the gate of the transistor 105, and one electrode of the capacitor 104. One of the source and drain of the transistor 105 is electrically connected to the output terminal 100a, and the other electrode of the capacitor 104 is electrically connected to one of the source and drain of the transistor 106. The other of the source and drain of the transistor 106 is electrically connected to the wiring 112, and the gate of the transistor 106 is electrically connected to the wiring 113a. The gate of the transistor 102 is electrically connected to the wiring 113b. The gate of the transistor 103 is electrically connected to the wiring 113c. The other of the source and drain of the transistor 103 is electrically connected to the wiring 118. The other electrode of the photoelectric conversion element 101 is electrically connected to the wiring 117. The other of the source and drain of the transistor 105 is electrically connected to the wiring 119.

[0079] The node FN is formed by connecting the other of the source and the drain of the transistor 102, one of the source and the drain of the transistor 103, the gate of the transistor 105, and one electrode of the capacitor 104. Note that a structure in which the capacitor 104 is not provided may be employed.

[0080] The transistor 103 can be turned on by a signal supplied to the wiring 113c. Thus, the node FN can be initialized by a reset potential supplied to the wiring 118. The transistor 102 can be turned on by a signal supplied to the wiring 113b. Therefore, the photoelectric conversion element 101 can be updated using imaging data obtained by photoelectrically converting the data of the node FN by the transistor 102. In addition, the transistor 102 can be turned off by a signal supplied to the wiring 113b. The node FN can hold the imaging data by turning off the transistor 102. That is, the first signal refers to the current flowing when the imaging data is supplied to the gate of the transistor 105.

[0081] Figure 4 Although an example in which an n-channel transistor is used as the transistor 105 is shown, a p-channel transistor may also be used. Note that when the transistor 105 is an n-channel transistor, the potential supplied to the wiring 119 is preferably a low potential, and when the transistor 105 is a p-channel transistor, the potential supplied to the wiring 119 is also preferably a low potential.

[0082] In addition, transistor 106 can be turned on according to a signal supplied to wiring 113a. Weight data can be supplied to capacitor 104 from wiring 112 through transistor 106. Preferably, node FN is a floating node when transistor 102 and transistor 103 are in an off state. Therefore, transistors 102 and 103 preferably use transistors with small off-state current. Transistors with small off-state current preferably use transistors (OS transistors) containing metal oxide in the channel formation region. OS transistors will be described in detail in Implementation 2.

[0083] The image data held in the node FN is added with weight data through the capacitor 104. That is, the gate of the transistor 105 is supplied with a data voltage obtained by adding weight data to the image data. Therefore, the transistor 105 can perform multiplication at an arbitrary multiple of the weight data using the resistance of the transistor 105. That is, the second signal refers to the current flowing when the data voltage obtained by adding weight data to the image data is supplied to the gate of the transistor 105.

[0084] exist Figure 5 In FIG. 2 , an example of the working method of the pooling module 200 is described. Figure 5 In FIG. 1A , for simplicity, an example is described in which the pooling module 200 includes four pooling circuits 210 and a comparison module 220. In addition, an example is shown in which the pooling circuit 210 includes four pixels. However, there is no limitation on the number of pooling modules 200 included in the imaging device 10.

[0085] Figure 5 Figure (B) shows Figure 5 (A) is a timing diagram of an example of the working method of the pooling module 200. Although not shown in the figure, Figure 5 The timing chart shown in FIG. 1 (B) shows an example in which an L signal is supplied to the wiring 115 and the pooling circuit 210 performs an addition process on the first signals of the plurality of pixels 100 .

[0086] In T1, the H signal is supplied to the wiring 113c, turning on the transistor 103 included in each pixel 100. Therefore, the node FN is reset by the potential supplied to the wiring 118. In addition, the wiring 113a is supplied with a selection signal, and the initial value Res of the weight data is supplied via the wiring 112.

[0087] In T2, an H signal is supplied to the wiring 113b, and each pixel 100 performs photoelectric conversion (sensing) by the photoelectric conversion element 101, and the node FN is updated using the image data.

[0088] In T3, an L signal is supplied to wiring 113b to determine the imaging data of node FN. In addition, a selection signal is supplied to wiring 113a(1), and weight data of pixel 100(1), pixel 100(2), pixel 100(5), and pixel 100(6) are set through wiring 112(1) to wiring 112(4).

[0089] In T4, a selection signal is supplied to the wiring 113a(2), and weight data of the pixel 100(3), the pixel 100(4), the pixel 100(7), and the pixel 100(8) are set through the wiring 112(1) to the wiring 112(4).

[0090] In T5, a selection signal is supplied to the wiring 113a(3), and weight data of the pixel 100(9), pixel 100(10), pixel 100(13), and pixel 100(14) are set through the wiring 112(1) to the wiring 112(4). In addition, the pooling circuit 210(1,1) outputs a data signal a1 in which the weight data is added to the image data to the wiring 210a(1,1). In addition, the pooling circuit 210(2,1) outputs a signal a2 in which the weight data is added to the image data to the wiring 210a(2,1).

[0091] In T6, a selection signal is supplied to the wiring 113a(4), and weight data of the pixel 100(11), the pixel 100(12), the pixel 100(15), and the pixel 100(16) are set through the wiring 112(1) to the wiring 112(4).

[0092] At T7, the pooling circuit 210 (1, 1) outputs a data signal b2 obtained by adding weight data to the image data to the wiring 210a (1, 2). Also, the pooling circuit 210 (2, 2) outputs a signal c2 obtained by adding weight data to the image data to the wiring 210a (2, 2).

[0093] In T8, the comparison module 220 detects the largest signal among a1, a2, b2, and c2. The determination circuit 221 included in the comparison module 220 determines the detected largest signal and binarizes it, and outputs the digital signal out to the wiring 211. The digital signal out is supplied to the output circuit 251. In order to facilitate processing in the neural network, the output circuit 251 combines the digital signal out and outputs it as digital data of an arbitrary data width.

[0094] exist Figure 6 In the block diagram, the Figure 2 Examples of pooling circuit 210 in different configurations. Figure 6 of Figure 2 The differences are that the pooling circuit 210 includes a plurality of wirings 113d, a wiring 211a, and a wiring 211b; and the pixel 100 includes an output terminal 100b.

[0095] The wiring 113d is electrically connected to a plurality of pixels extending in the column direction. The wiring 211a is electrically connected to the output terminal 100b of the pixel 100 extending in the row direction. The imaging data is output to the wiring 211a or the wiring 211b. The imaging data is output to the analog-to-digital conversion circuit 250 through the wiring 211a and the wiring 211b.

[0096] Figure 7 Description has Figure 4 Examples of pixels 100 with different structures. Figure 7 of Figure 4 The difference lies in the inclusion of transistor 107 and transistor 108 .

[0097] The gate of the transistor 107 is electrically connected to the node FN. One of the source and the drain of the transistor 107 is electrically connected to one of the source and the drain of the transistor 108. The other of the source and the drain of the transistor 108 is electrically connected to the output terminal 100b. The gate of the transistor 108 is electrically connected to the wiring 113d. The other of the source and the drain of the transistor 107 is electrically connected to the wiring 119.

[0098] The transistor 107 can flow a current according to the potential of the imaging data held in the node FN. The transistor 108 can output the imaging data to the output terminal 100b according to the selection signal supplied to the wiring 113d. Note that when weight data is set in the capacitor 104, the multiplication result obtained by adding the weight data to the imaging data and according to the resistance of the transistor 105 is output.

[0099] The camera device 10 can easily perform pooling processing by including the pooling module 200. Therefore, by reducing the amount of data transmitted to the neural network and the amount of calculation, power consumption can be reduced.

[0100] As described above, the structure and method described in this embodiment can be used in combination with the structure and method described in other embodiments as appropriate.

[0101] (Implementation Method 2)

[0102] In this embodiment, refer to Figures 8 to 14 The photoelectric conversion element 101 used in the image pickup device 10 will be described.

[0103] <Configuration Example of Pixel Circuit>

[0104] Figure 8 (A) shows the structure of a pixel having the above-mentioned pixel circuit. Figure 8 FIG. 5 (A) shows an example in which a pixel has a stacked structure of layers 61 and 62 .

[0105] Layer 61 includes the photoelectric conversion element 101. Figure 8 As shown in FIG. 5(C) , the photoelectric conversion element 101 may be a stack of a layer 65 a , a layer 65 b , and a layer 65 c .

[0106] Figure 8 The photoelectric conversion element 101 shown in FIG. 1 (C) is a pn junction type photodiode, and for example, a p + type semiconductor, an n-type semiconductor is used as layer 65b, and an n-type semiconductor is used as layer 65c. + Alternatively, n may be used as layer 65a. + type semiconductor, a p-type semiconductor as layer 65b, and a p-type semiconductor as layer 65c. + Alternatively, the photoelectric conversion element 101 may use a pin junction photodiode using an i-type semiconductor as the layer 65b.

[0107] The pn junction photodiode or the pin junction photodiode can be formed using single crystal silicon. Alternatively, the pin junction photodiode can be formed using a thin film of amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like.

[0108] In addition, if Figure 8 As shown in FIG. 2(D) , the photoelectric conversion element 101 included in the layer 61 may be a stack of layers 66a , 66b , 66c , and 66d . Figure 8 The photoelectric conversion element 101 shown in FIG. 2 (D) is an example of an avalanche photodiode, in which the layers 66a and 66d correspond to electrodes, and the layers 66b and 66c correspond to photoelectric conversion sections.

[0109] The layer 66a is preferably made of a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stacked layer thereof can be used.

[0110] The layer 66d is preferably a conductive layer having high light transmittance to visible light (Light). For example, indium oxide, tin oxide, zinc oxide, indium tin oxide, gallium zinc oxide, indium gallium zinc oxide, or graphene can be used. In addition, the layer 66d can be omitted.

[0111] The photoelectric conversion layer 66b, 66c may have a pn junction photodiode structure using a selenium-based material as the photoelectric conversion layer. Preferably, a p-type semiconductor selenium-based material is used as the layer 66b, and an n-type semiconductor such as gallium oxide is used as the layer 66c.

[0112] Photoelectric conversion elements using selenium materials have high external quantum efficiency for visible light. The photoelectric conversion element can be a device that increases the amount of electron amplification relative to the amount of incident light by using avalanche multiplication. In addition, selenium materials have a high light absorption coefficient, so for example, the photoelectric conversion layer can be manufactured in a thin film, which is advantageous from the perspective of production. The thin film of the selenium material can be formed by a vacuum evaporation method or a sputtering method, etc.

[0113] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0114] The n-type semiconductor is preferably formed of a material with a wide band gap and translucency to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or oxides mixed with the above substances can be used. In addition, these materials also have the function of a hole injection blocking layer, which can reduce dark current.

[0115] As Figure 8 The layer 62 shown in FIG. (A) may be, for example, a silicon substrate. Si transistors and the like are provided on the silicon substrate, and in addition to the above-mentioned pixel circuits, circuits for driving the pixel circuits, image signal readout circuits, image processing circuits, and the like may also be provided.

[0116] In addition, if Figure 8 As shown in FIG. 1B , the pixel may also have a stacked structure of layer 61 , layer 63 , and layer 62 .

[0117] Layer 63 may include OS transistors (e.g., transistors 102 and 103 of the pixel circuit). At this time, layer 62 preferably includes Si transistors (e.g., transistors 107 and 108 of the pixel circuit).

[0118] By adopting this structure, the elements constituting the pixel circuit can be dispersed into multiple layers and the elements can be arranged in an overlapping manner, so that the area of the imaging device can be reduced. In addition, in the structure of (B) of Figure 8 , layer 62 can also be used as a support substrate and pixels 100 and peripheral circuits can be provided on layer 61 and layer 63.

[0119] <OS transistor>

[0120] As the semiconductor material for the OS transistor, a metal oxide with a bandgap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium can be used, such as CAC-OS described later.

[0121] As the semiconductor layer, for example, a film represented by "In-M-Zn type oxide" containing indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be adopted.

[0122] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn type oxide, the atomic ratio of the metal elements of the sputtering target preferably used for depositing and forming the In-M-Zn oxide film satisfies In≥M and Zn≥M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. Note that the atomic ratio of the semiconductor layer deposited and formed can vary within the range of ±40% of the atomic ratio of the metal elements in the above sputtering target.

[0123] As the semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, as the semiconductor layer, a semiconductor with a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, and further preferably 1×10 11 / cm 3Below, more preferably less than 1×10 10 / cm 3 and 1×10 -9 / cm 3 Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Therefore, since the impurity concentration and defect level density are low, it can be said that it is an oxide semiconductor with stable characteristics.

[0124] Note that the present invention is not limited to the above description, and a material having an appropriate composition can be used according to the desired semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the transistor. In addition, it is preferred to appropriately set the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0125] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the elements of Group 14, oxygen vacancies increase and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 Below, preferably 2×10 17 atoms / cm 3 the following.

[0126] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers are generated, which increases the off-state current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0127] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, the carrier density increases, and it is easy to become n-type. As a result, the transistor using the oxide semiconductor containing nitrogen is easy to become normally-on. Therefore, the nitrogen concentration of the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5×10 18 atoms / cm 3 the following.

[0128] In addition, the semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure includes, for example, a crystallized CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor or C-AxisAligned and AB-plane Anchored Crystalline Oxide Semiconductor) with a c-axis orientation, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the defect energy level density of the amorphous structure is the highest, while the defect energy level density of the CAAC-OS is the lowest.

[0129] The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystalline component. Alternatively, the oxide semiconductor film with an amorphous structure has, for example, a completely amorphous structure and no crystalline part.

[0130] In addition, the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have a single layer structure or a stacked layer structure including two or more of the above regions.

[0131] Next, the structure of CAC (Cloud-Aligned Composite)-OS, which is one embodiment of a non-single-crystal semiconductor layer, will be described.

[0132] CAC-OS refers to, for example, a configuration in which elements contained in an oxide semiconductor are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm, is also referred to as a mosaic or patch shape.

[0133] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0134] For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, In-Ga-Zn oxide can be referred to as CAC-IGZO in particular) refers to a material divided into indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0). ) or indium zinc oxide (hereinafter referred to as InX2 Zn Y2 O Z2 (X2, Y2 and Z2 are real numbers greater than 0). ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4 and Z4 are real numbers greater than 0). ) etc. to form a mosaic shape, and the mosaic-shaped InO X1 or In X2 Zn Y2 O Z2 A structure uniformly distributed in the film (hereinafter also referred to as a cloud shape).

[0135] In other words, CAC-OS is a GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 In this specification, for example, when the atomic number ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0136] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1≤x0≤1, m0 is an arbitrary number).

[0137] The crystalline compound has a single crystal structure, a polycrystalline structure or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0138] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to the following composition: in the material composition containing In, Ga, Zn and O, nanoparticle-like regions with Ga as the main component are observed in part, and nanoparticle-like regions with In as the main component are observed in part, and these regions are randomly dispersed in a mosaic shape. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0139] CAC-OS does not include a stacked-layer structure of two or more films having different compositions, for example, a structure consisting of two layers of a film having In as a main component and a film having Ga as a main component.

[0140] Note that sometimes no GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 There are clear boundaries between the regions of the main components.

[0141] In the case where CAC-OS includes one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium instead of gallium, CAC-OS refers to a structure in which nanoparticle-like regions with the element as the main component are observed in a part and nanoparticle-like regions with In as the main component are observed in a part and are irregularly dispersed in a mosaic manner.

[0142] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When CAC-OS is formed by sputtering, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used as a film-forming gas. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the film-forming gas during film formation, the better. For example, the flow rate ratio of the oxygen gas is set to be greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0143] CAC-OS has the following characteristics: when measured by the Out-of-plane method using θ / 2θ scanning, which is one of the X-ray diffraction (XRD) measurement methods, no clear peak is observed. In other words, according to X-ray diffraction, it can be seen that there is no orientation in the ab plane direction and the c-axis direction in the measurement area.

[0144] In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam (also called a nanobeam) with a beam diameter of 1 nm, a ring-shaped area with high brightness and multiple bright spots in the ring-shaped area were observed. Therefore, according to the electron diffraction pattern, it can be seen that the crystalline structure of CAC-OS has an nc (nano-crystal) structure that is not oriented in the plane direction and the cross-sectional direction.

[0145] In addition, for example, in CAC-OS of In-Ga-Zn oxide, it can be confirmed from EDX surface analysis images (EDX-mapping) obtained by energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) that there is GaO X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 A composition in which the main components are unevenly distributed in the area.

[0146] The structure of CAC-OS is different from that of IGZO compounds in which metal elements are evenly distributed, and it has different properties from IGZO compounds. X3 The area with In as the main component X2 Zn Y2 O Z2 or InO X1 The regions where the main components are present are separated from each other, and the regions where the main components are present are in a mosaic-like structure.

[0147] Here, In X2 Zn Y2 O Z2 or InO X1 The conductivity of the area with GaO as the main component is higher than that of the area with GaO as the main component. X3 In other words, when the carrier flows through the region with In X2 Zn Y2 O Z2 or InO X1 When In is the main component of the region, it exhibits the conductivity of an oxide semiconductor. X2 Zn Y2 O Z2 or InO X1 When the region as the main component is distributed in a cloud-like manner in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0148] On the other hand, GaO X3 The insulation of the area with In as the main component is higher than that of the area with In X2 Zn Y2 O Z2 or InO X1 In other words, when GaO X3 When regions with the main components of MgO and the like are distributed in an oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0149] Therefore, when CAC-OS is used in semiconductor devices, the X3 The insulation properties of etc. and the causes of In X2 Zn Y2 O Z2 or InO X1 The complementary effect of conductivity can achieve high on-state current (I on ) and high field effect mobility (μ).

[0150] In addition, semiconductor elements using CAC-OS have high reliability. Therefore, CAC-OS is suitable for use as a constituent material of various semiconductor devices.

[0151] Fig. 9 Figure (A) shows Figure 8 FIG. 10A is a diagram showing an example of a cross section of a pixel shown in FIG. 101. As the photoelectric conversion element 101, the layer 61 includes a pn junction type photodiode using silicon as a photoelectric conversion layer. The layer 62 includes Si transistors and the like constituting a pixel circuit.

[0152] In the photoelectric conversion element 101, the layer 65a may be p + type region, layer 65b is an n-type region and layer 65c is an n-type region. + In addition, layer 65b is provided with region 36 for connecting the power line to layer 65c. For example, region 36 may be p + Type area.

[0153] exist Fig. 9 In FIG. 1A , the Si transistor has a planar structure with a channel formation region on a silicon substrate 40, but Fig.12 Figure (A), Fig.12 As shown in FIG. 2(B) , a structure including a fin-type semiconductor layer on a silicon substrate 40 may also be adopted. Fig.12 Figure (A) is equivalent to the cross section along the channel length direction. Fig.12 Figure (B) corresponds to a cross section in the channel width direction.

[0154] In addition, if Fig.12 As shown in FIG. 1C , a transistor including a semiconductor layer 45 of a silicon thin film may be used. For example, the semiconductor layer 45 may be formed of single crystal silicon (SOI (Silicon on Insulator)) formed on an insulating layer 46 on a silicon substrate 40 .

[0155] Here, Fig. 9 FIG. 1 (A) shows an example in which the components of layer 61 and the components of layer 62 are electrically connected by bonding technology.

[0156] Insulating layer 42, conductive layer 33, and conductive layer 34 are provided on layer 61. Conductive layer 33 and conductive layer 34 have a region in which insulating layer 42 is buried. Conductive layer 33 is electrically connected to layer 65a. Conductive layer 34 is electrically connected to region 36. In addition, the surfaces of insulating layer 42, conductive layer 33, and conductive layer 34 are flattened so that their heights are uniform.

[0157] An insulating layer 41, a conductive layer 31, and a conductive layer 32 are provided on the layer 62. The conductive layer 31 and the conductive layer 32 have a region in which the insulating layer 41 is buried. The conductive layer 32 is electrically connected to a power supply line. The conductive layer 31 is electrically connected to one of a source and a drain of the transistor 102. In addition, the surfaces of the insulating layer 41, the conductive layer 31, and the conductive layer 32 are flattened so that their heights are uniform.

[0158] Here, the main components of the conductive layer 31 and the conductive layer 33 are preferably the same metal element. The main components of the conductive layer 32 and the conductive layer 34 are preferably the same metal element. Insulating layer 41 and insulating layer 42 are preferably composed of the same component.

[0159] For example, Cu, Al, Sn, Zn, W, Mo, Ag, Pt, Au, etc. can be used as the conductive layers 31, 32, 33, and 34. From the viewpoint of ease of bonding, Cu, Al, W, or Au is preferably used. In addition, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used for the insulating layers 41 and 42.

[0160] In other words, it is preferable that the same metal material as the above metal material is used as the combination of the conductive layer 31 and the conductive layer 33 and the combination of the conductive layer 32 and the conductive layer 34. In addition, it is preferable that the same insulating material as the above insulating material is used as the insulating layer 41 and the insulating layer 42. By adopting the above structure, bonding can be performed with the boundary between the layer 61 and the layer 62 as the bonding position.

[0161] Through the above-described lamination process, electrical connections can be obtained between the combination of conductive layer 31 and conductive layer 33 and the combination of conductive layer 32 and conductive layer 34. In addition, mechanically strong connection between insulating layer 41 and insulating layer 42 can be obtained.

[0162] When joining metal layers, a surface activation bonding method can be used. In this method, the oxide film and impurity adsorption layer on the surface are removed by sputtering treatment, etc., and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method that uses temperature and pressure to bond the surfaces can be used. The above methods can all produce atomic-level bonding, so excellent bonding can be obtained both electrically and mechanically.

[0163] In addition, when bonding the insulating layer, a hydrophilic bonding method can be used. In this method, after obtaining high flatness by polishing, etc., the surfaces that have been hydrophilized by oxygen plasma, etc. are brought into contact for temporary bonding, and dehydration is performed by heat treatment to perform formal bonding. The hydrophilic bonding method also produces bonding at the atomic level, so mechanically excellent bonding can be obtained.

[0164] In the case of the bonding layer 61 and the layer 62, since the insulating layer and the metal layer are mixed at each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

[0165] For example, a method of bonding can be adopted in which the surface is cleaned after polishing, the surface of the metal layer is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed. Alternatively, a difficultly oxidizable metal such as Au can be used as the surface of the metal layer and a hydrophilic treatment can be performed. Alternatively, bonding methods other than the above methods can be used.

[0166] Fig. 9 Figure (B) is as Figure 8 The pixel layer 61 shown in FIG. (A) is a cross-sectional view when a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer is used. The layer 66a is one electrode, the photoelectric conversion layers are layers 66b and 66c, and the other electrode is layer 66d.

[0167] In this case, the layer 61 can be provided directly on the layer 62. The layer 66a is electrically connected to the source or drain of the transistor 102. The layer 66d is electrically connected to the power supply line through the conductive layer 37.

[0168] Fig.10 Figure (A) shows Figure 8 FIG. (B) is a diagram showing an example of a cross section of a pixel. As the photoelectric conversion element 101, layer 61 includes a pn junction type photodiode using silicon as a photoelectric conversion layer. Layer 62 includes Si transistors and the like. Layer 63 includes OS transistors and the like. Fig.10 FIG. 1(A) shows a structural example in which the bonding layer 61 and the layer 63 are electrically connected.

[0169] Fig.10 FIG. 1A shows that the OS transistor is a self-aligned structure, but Fig.12 As shown in Figure (D), it can also be a transistor with a non-self-aligned structure.

[0170] Although the transistor 102 is shown to include a back gate 35, a structure including a back gate may also be employed. Fig.12 As shown in FIG. 1 (E), the back gate 35 may be electrically connected to the front gate of the transistor facing it. Alternatively, a structure may be adopted in which a fixed potential different from that of the front gate can be supplied to the back gate 35.

[0171] An insulating layer 43 having a function of preventing diffusion of hydrogen is provided between a region where the OS transistor is formed and a region where the Si transistor is formed. Hydrogen in the insulating layer provided near the channel formation region of the transistors 107 and 108 terminates dangling bonds of silicon. On the other hand, hydrogen in the insulating layer provided near the channel formation region of the transistor 102 may be one of the causes of generation of carriers in the oxide semiconductor layer.

[0172] By providing the insulating layer 43 to confine hydrogen in one layer, the reliability of the transistors 107 and 108 can be improved. At the same time, since diffusion of hydrogen from one layer to another layer can be suppressed, the reliability of the transistor 102 can be improved.

[0173] The insulating layer 43 can be made of, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

[0174] Fig.10 Figure (B) shows that Figure 8 The pixel layer 61 shown in FIG. (B) is a cross-sectional view of a case where a pn junction type photodiode using a selenium-based material as a photoelectric conversion layer is used. The layer 61 can be directly provided on the layer 63. The details of the layers 61, 62, and 63 can refer to the above description.

[0175] Fig.11 Figure (A) shows Fig.10 The sensor region is composed of a layer 61 having a photoelectric conversion element 101 and a layer 63 having an OS transistor. The operation region is composed of a layer 63 having Si transistors and the like. The operation region includes transistors 107 and 108 in the pixel and circuits such as the pooling circuit, drivers 11, 12, and 13 of embodiment 1. By having a stacked structure having a sensor region and an operation region, the circuit area can be reduced.

[0176] Fig.11 Figure (B) shows a cross-sectional photograph of the sensor region and a cross-sectional photograph of the operation region. The sensor region is composed of a pn junction photodiode and an OS transistor (OSFET) using a selenium-based material as a photoelectric conversion layer, and the operation region is composed of Si transistors (SiFET) to form various circuits.

[0177] <Other pixel components>

[0178] Fig.13FIG. (A) is a stereoscopic diagram showing an example of adding a color filter or the like to a pixel of an imaging device of one embodiment of the present invention. The stereoscopic diagram also shows a cross section of a plurality of pixels. An insulating layer 80 is formed on the layer 61 forming the photoelectric conversion element 101. The insulating layer 80 can use a silicon oxide film or the like having high light transmittance to visible light. In addition, a structure of a stacked silicon nitride film can be used as a passivation film. In addition, a structure of a stacked dielectric film of hafnium oxide or the like can be used as an antireflection film.

[0179] A light shielding layer 81 may also be formed on the insulating layer 80. The light shielding layer 81 has a function of preventing the mixing of light passing through the upper color filter. A metal layer such as aluminum or tungsten may be used as the light shielding layer 81. In addition, the metal layer may be laminated with a dielectric film having the function of an anti-reflection film.

[0180] An organic resin layer 82 used as a planarization film may be provided on the insulating layer 80 and the light shielding layer 81. In addition, a color filter 83 (color filters 83a, 83b, 83c) is formed in each pixel. For example, the color filters 83a, 83b, and 83c are provided with colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta), thereby obtaining a color image.

[0181] An insulating layer 86 or the like having a light-transmitting property to visible light may be provided on the color filter 83 .

[0182] In addition, if Fig.13 As shown in FIG. 8B , an optical conversion layer 85 may be used instead of the color filter 83. By adopting such a structure, an imaging device capable of obtaining images in various wavelength regions can be formed.

[0183] For example, when a color filter that blocks light with a wavelength below the visible light is used as the optical conversion layer 85, an infrared camera device can be obtained. When a color filter that blocks light with a wavelength below the near infrared light is used as the optical conversion layer 85, a far infrared camera device can be obtained. In addition, when a color filter that blocks light with a wavelength above the visible light is used as the optical conversion layer 85, an ultraviolet camera device can be obtained. A color filter for visible light can be combined with a color filter for infrared or ultraviolet light.

[0184] In addition, by using a scintillator for the optical conversion layer 85, an imaging device for obtaining an image that visualizes the radiation intensity, such as an X-ray imaging device, can be formed. When radiation such as X-rays that pass through the object to be photographed is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light due to the photoluminescence phenomenon. Image data is obtained by detecting this light with the photoelectric conversion element 101. In addition, the imaging device of this structure can also be used for radiation detectors, etc.

[0185] The scintillator contains a substance that absorbs the energy of radiation and emits visible light or ultraviolet light when the scintillator is irradiated with radiation such as X-rays or gamma rays. 2 O 2 S: Tb, Gd 2 O 2 S: Pr, Gd 2 O 2 S: Eu, BaFCl: Eu, NaI, CsI, CaF 2 , BaF 2 , CeF 3 , LiF, LiI, ZnO and other materials dispersed in resin or ceramics.

[0186] In addition, in the photoelectric conversion element 101 using a selenium-based material, since radiation such as X-rays can be directly converted into electric charges, it is not necessary to use a scintillator.

[0187] In addition, if Fig.13 As shown in FIG. 8C , a microlens array 84 may be provided on the color filter 83. Light passing through each lens of the microlens array 84 is irradiated to the photoelectric conversion element 101 via the color filter 83 provided thereunder. Fig.13 A microlens array 84 is provided on the optical conversion layer 85 shown in FIG.

[0188] <Package and module structure examples>

[0189] An example of a package and a camera module that accommodate an image sensor chip will be described below. The image sensor chip may be the one having the structure of the above-mentioned imaging device.

[0190] Fig.14 FIG. (A1) is a perspective view of the top surface of a package housing an image sensor chip. The package includes a package substrate 410 for fixing an image sensor chip 450, a glass cover plate 420, and an adhesive 430 for bonding them.

[0191] Fig.14 Figure (A2) is a perspective view of the bottom side of the package. The bottom side of the package includes a BGA (Ball grid array) with solder balls as bumps 440. Note that it is not limited to BGA, and can also include LGA (Land grid array), PGA (Pin Grid Array), etc.

[0192] Fig.14FIG. (A3) is a perspective view of a package omitting a portion of the glass cover 420 and the adhesive 430. An electrode pad 460 is formed on the package substrate 410, and the electrode pad 460 is electrically connected to the bump 440 through a through hole. The electrode pad 460 is electrically connected to the image sensor chip 450 through a lead 470.

[0193] in addition, Fig.14 FIG. (B1) is a perspective view of the top surface of a camera module in which an image sensor chip is housed in a lens-integrated package. The camera module includes a package substrate 411 that fixes an image sensor chip 451, a lens cover 421, and a lens 435. In addition, an IC chip 490 having functions such as a driving circuit and a signal conversion circuit of a camera device is provided between the package substrate 411 and the image sensor chip 451, and has a structure as a SiP (System in Package).

[0194] Fig.14 (B2) is a perspective view of the bottom side of the camera module. The bottom and side surfaces of the package substrate 411 have a QFN (Quad flat no-lead package) structure with a storage connection pad 441. Note that this structure is an example, and a QFP (Quad flat package) or the above-mentioned BGA can also be provided.

[0195] Fig.14 FIG. (B3) is a perspective view of the module omitting a portion of the lens cover 421 and the lens 435. The connection pad 441 is electrically connected to the electrode pad 461, and the electrode pad 461 is electrically connected to the image sensor chip 451 or the IC chip 490 via the wire 471.

[0196] By housing the image sensor chip in a package of the above type, it can be easily mounted on a printed circuit board or the like, and thus the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0197] As described above, the structure and method described in this embodiment can be used in combination with the structure and method described in other embodiments as appropriate.

[0198] (Implementation 3)

[0199] Electronic devices that can use the camera device according to one embodiment of the present invention include display devices, personal computers, image storage devices and image reproduction devices with recording media, mobile phones, including portable game consoles, portable data terminals, e-book readers, imaging devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. Fig.15 Specific examples of these electronic devices are shown.

[0200] Fig.15 Figure (A) is a surveillance camera, which includes a bracket 951, a camera unit 952, a protective cover 953, etc. The camera unit 952 is provided with a rotating mechanism, etc., and can capture the surroundings by being installed on the ceiling. As one of the components used to obtain images in the camera unit, a camera device of one embodiment of the present invention can be provided. Note that "surveillance camera" is a general name and is not limited to its use. For example, a device having the function of a surveillance camera is called a video camera or a video camera.

[0201] Fig.15 FIG. (B) is a video camera including a first housing 971, a second housing 972, a display unit 973, an operation key 974, a lens 975, a connection unit 976, and the like. The operation key 974 and the lens 975 are provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring an image in the video camera, an imaging device according to one embodiment of the present invention may be provided.

[0202] Fig.15 FIG. 9C is a digital camera including a housing 961, a shutter button 962, a microphone 963, a light emitting unit 967, a lens 965, etc. As one of the components for acquiring an image in the digital camera, an imaging device according to one embodiment of the present invention may be provided.

[0203] Fig.15 FIG. (D) is a watch-type information terminal, which includes a display unit 932, a housing and wristband 933, and a camera 939. The display unit 932 may also include a touch panel for operating the information terminal. The display unit 932 and the housing and wristband 933 are flexible and suitable for being worn on the body. As one of the components for acquiring images in the information terminal, a camera device of one embodiment of the present invention may be provided.

[0204] Fig.15FIG. (E) shows an example of a mobile phone, which includes a housing 981, a display portion 982, an operation button 983, an external connection interface 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor on the display portion 982. By touching the display portion 982 with a finger or a stylus pen, various operations such as making a call or inputting text can be performed. As one of the components for acquiring an image in the mobile phone, a camera device of one embodiment of the present invention can be provided.

[0205] Fig.15 FIG. (F) is a portable data terminal including a housing 911, a display unit 912, a camera 919, etc. Information can be input and output through the touch panel function of the display unit 912. As one of the components for acquiring an image in the portable data terminal, a camera device according to one embodiment of the present invention can be provided.

[0206] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0207] In addition, in this specification, etc., a display element, a display device as a device including a display element, a light-emitting element, and a light-emitting device as a device including a light-emitting element may adopt various methods or include various elements. The display element, the display device, the light-emitting element, or the light-emitting device may include, for example, at least one of an EL (electroluminescent) element (EL element including organic and inorganic substances, organic EL element, inorganic EL element), an LED chip (white LED chip, red LED chip, green LED chip, blue LED chip, etc.), a transistor (a transistor that emits light according to current), a plasma display panel (PDP), an electron emission element, a display element using carbon nanotubes, a liquid crystal element, electronic ink, an electrowetting element, an electrophoretic element, a display element using MEMS (micro-electromechanical system) (for example, a grating light valve (GLV), a digital micromirror device (DMD), a DMS (digital micromirror device), MIRASOL (registered trademark in Japan), an IMOD (interference modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, a piezoelectric ceramic display, etc.), and a quantum dot. In addition, a display element, a display device, a light-emitting element or a light-emitting device may also have a display medium whose contrast, brightness, reflectivity, transmittance, etc. change due to electrical or magnetic effects. Examples of display devices using EL elements include EL displays, etc. Examples of display devices using electron emission elements include field emission displays (FED) or SED flat-panel displays (SED: Surface-conduction Electron-emitter Display: Surface-conduction electron emission display), etc. Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays), etc. Examples of display devices using electronic ink, electronic powder fluid (a registered trademark in Japan), or electrophoretic elements include electronic paper, etc. Examples of display devices using quantum dots in each pixel include quantum dot displays, etc. Quantum dots can be used not as display elements but as part of a backlight. By using quantum dots, a display with high color purity can be performed. Note that when a semi-transmissive liquid crystal display or a reflective liquid crystal display is implemented, part or all of the pixel electrodes may function as a reflective electrode. For example, part or all of the pixel electrode may contain aluminum, silver, etc. In addition, a storage circuit such as SRAM may be disposed under the reflective electrode. Thus, power consumption can be further reduced. Note that when an LED chip is used, graphene or graphite may also be disposed under the electrode or nitride semiconductor of the LED chip. Graphene or graphite may also be a multilayer film having a plurality of layers stacked thereon. Thus, by disposing graphene or graphite, a nitride semiconductor such as a crystallized n-type GaN semiconductor layer may be more easily formed thereon.Furthermore, a p-type GaN semiconductor layer having crystals is provided thereon, so that an LED chip can be formed. In addition, an AlN layer can be provided between graphene or graphite and the n-type GaN semiconductor layer having crystals. In addition, the GaN semiconductor layer included in the LED chip can also be formed by MOCVD. Note that the GaN semiconductor layer included in the LED chip can also be formed by sputtering by providing graphene. In addition, in a display element using MEMS, by configuring a desiccant in a space where the display element is sealed (for example, between an element substrate on which the display element is provided and an opposing substrate opposite to the element substrate), it is possible to prevent the MEMS, etc. from malfunctioning or deteriorating due to moisture.

[0208] Note that this embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0209] (Supplementary Notes Regarding the Descriptions in This Manual, etc.)

[0210] Next, comments are added to each structure and description in the above-mentioned embodiment.

[0211] <Supplementary Notes on One Mode of the Invention Shown in the Embodiment>

[0212] The structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one embodiment of the present invention. In addition, when a plurality of structural examples are described in one embodiment, the structural examples can be appropriately combined.

[0213] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in the embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0214] Note that the contents described in the embodiments refer to the contents described in each embodiment using various drawings or the contents described in the text described in the specification.

[0215] In addition, more figures may be formed by combining a figure (or part thereof) shown in a certain embodiment with other parts of the figure, other figures (or parts thereof) shown in the embodiment, and at least one of the figures (or parts thereof) shown in one or more other embodiments.

[0216] <Notes on ordinal numbers>

[0217] In this specification, etc., ordinal numbers such as "first", "second", and "third" are added to avoid confusion among constituent elements. Therefore, they are not added to limit the number of constituent elements. In addition, they are not added to limit the order of constituent elements. In addition, for example, a constituent element with the ordinal number "first" in one of the embodiments of this specification, etc. may be attached with the ordinal number "second" in other embodiments or claims. In addition, for example, a constituent element with the ordinal number "first" in one of the embodiments of this specification, etc. may be omitted in other embodiments or claims.

[0218] <Supplementary Notes on the Description of the Drawings>

[0219] The embodiments are described with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same figure mark is used in different drawings to show the same part or the part with the same function, and repeated description is omitted.

[0220] In this specification, for convenience, words and phrases such as "upper" and "lower" are used to describe the positional relationship of the components with reference to the drawings. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases showing the configuration are not limited to the descriptions shown in this specification, and the expression method can be appropriately changed according to the situation.

[0221] In addition, the terms "above" or "below" do not limit the positional relationship of the components to the situation where they are "directly above" or "directly below" and in direct contact. For example, when it is described as "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed on insulating layer A in direct contact, and the situation where other components are included between insulating layer A and electrode B may also be included.

[0222] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not necessarily limited to the above dimensions. The drawings are shown for the sake of clarity and are not limited to the shapes or values ​​shown in the drawings. For example, the signal, voltage or current unevenness caused by noise or timing deviation may be included.

[0223] In drawings such as perspective views, some components may be omitted for clarity.

[0224] In the drawings, the same components, components having the same function, components made of the same material, components formed at the same time, etc. are sometimes shown using the same reference numerals, and repeated descriptions are sometimes omitted.

[0225] 〈Supplementary Notes on Records That May Be Renamed〉

[0226] In this specification, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and the drain" (a first electrode or a first terminal), and the other of the source and the drain is referred to as "the other of the source and the drain" (a second electrode or a second terminal). This is because the source and the drain of the transistor are interchangeable depending on the structure or operating conditions of the transistor. The source and the drain of the transistor may be appropriately renamed as a source (drain) terminal, a source (drain) electrode, etc., depending on the circumstances. In addition, in this specification, the two terminals other than the gate are sometimes referred to as a first terminal and a second terminal or a third terminal and a fourth terminal. In addition, when a transistor described in this specification has more than two gates (this structure is sometimes referred to as a dual-gate structure), the gate is sometimes referred to as a first gate, a second gate, a front gate, or a back gate. In particular, the "front gate" may be simply replaced by a "gate". In addition, the "back gate" may be simply replaced by a "gate". In addition, a “bottom gate” refers to a terminal formed before a channel formation region is formed when a transistor is formed, and a “top gate” refers to a terminal formed after a channel formation region is formed when a transistor is formed.

[0227] A transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. Of the two input / output terminals used as a source or a drain, one terminal is used as a source and the other terminal is used as a drain, depending on the type of transistor or the potential level supplied to each terminal. Therefore, in this specification, etc., "source" and "drain" can be interchanged.

[0228] Note that in this specification, the term "electrode" or "wiring" does not limit the function of its constituent elements. For example, an "electrode" may be used as a part of a "wiring" or vice versa. Furthermore, the term "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wirings" are formed as one.

[0229] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference with the reference potential. For example, when the reference potential is the ground potential, voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential.

[0230] In this specification, etc., words such as "film" and "layer" can be interchanged depending on the situation or state. For example, "conductive layer" can be replaced with "conductive film" in some cases. In addition, "insulating film" can be replaced with "insulating layer" in some cases. In addition, other words can be used instead of words such as "film" and "layer" depending on the situation or state. For example, "conductive layer" or "conductive film" can be replaced with "conductive body" in some cases. In addition, for example, "insulating layer" or "insulating film" can be replaced with "insulator" in some cases.

[0231] In this specification, etc., depending on the situation or state, the words "wiring", "signal line" and "power line" can be interchanged with each other. For example, "wiring" can sometimes be converted to "signal line". In addition, for example, "wiring" can sometimes be converted to "power line". Vice versa, "signal line" or "power line" can sometimes be converted to "wiring". Sometimes "power line" can be converted to "signal line". Vice versa, "signal line" can sometimes be converted to "power line". In addition, depending on the situation or state, the "potential" applied to the wiring can be converted to "signal". Vice versa, "signal" can sometimes be converted to "potential".

[0232] 〈Supplementary Notes on Definitions of Words and Phrases〉

[0233] Next, the definitions of the words and phrases involved in the above-mentioned embodiment are explained.

[0234] About Impurities in Semiconductors

[0235] Impurities of semiconductors are, for example, substances other than the main components that constitute the semiconductor layer. For example, an element with a concentration lower than 0.1 atomic% is an impurity. Sometimes, due to the inclusion of impurities, for example, DOS (Density of States) is formed in the semiconductor, carrier mobility is reduced, or crystallinity is reduced. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, there are, for example, first group elements, second group elements, thirteenth group elements, fourteenth group elements, fifteenth group elements or transition metals other than the main components, in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. When the semiconductor is an oxide semiconductor, for example, the mixing of impurities such as hydrogen sometimes leads to the generation of oxygen defects. In addition, when the semiconductor is a silicon layer, as impurities that change the characteristics of the semiconductor, there are, for example, oxygen, first group elements other than hydrogen, second group elements, thirteenth group elements, fifteenth group elements, etc.

[0236] "transistor"

[0237] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel formation region between a drain (drain terminal, a drain region, or a drain electrode) and a source (source terminal, a source region, or a source electrode). By supplying a voltage exceeding a threshold voltage between the gate and the source, a channel can be formed in the channel formation region and a current can flow between the source and the drain.

[0238] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, "source" and "drain" may be interchanged.

[0239] "switch"

[0240] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0241] For example, an electric switch or a mechanical switch may be used. In other words, the switch is not limited to a specific switch as long as it can control the current.

[0242] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, metal-insulator-semiconductor (MIS) diodes, or diode-connected transistors), or logic circuits combining these elements.

[0243] When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited. In addition, the "non-conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When the transistor is used only as a switch, there is no particular restriction on the polarity (conductive type) of the transistor.

[0244] An example of a mechanical switch is a switch using MEMS (micro-electro-mechanical system) technology such as a digital micro-mirror device (DMD). This switch has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0245] "connect"

[0246] Note that in this specification, when it is stated that "X is connected to Y", it includes the following cases: X is electrically connected to Y; X is functionally connected to Y; and X is directly connected to Y. Therefore, the connection relationship is not limited to the connection relationship shown in the drawings or the text, and includes connection relationships other than those shown in the drawings or the text.

[0247] X and Y used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films and layers, etc.).

[0248] As an example of a case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) that can electrically connect X and Y may be connected between X and Y. In addition, the switch has a function of controlling on and off. In other words, whether or not current flows is controlled by placing the switch in a conducting state (on state) or a non-conducting state (off state).

[0249] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, γ (gamma) correction circuit, etc.), a potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), a level converter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplifier circuit (a circuit capable of increasing signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a storage circuit, a control circuit, etc.) may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y can be said to be functionally connected.

[0250] Furthermore, when it is explicitly stated that “X is electrically connected to Y”, the following cases are included: a case where X is electrically connected to Y (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); a case where X and Y are functionally connected (in other words, a case where X and Y are functionally connected with another circuit interposed therebetween); and a case where X and Y are directly connected (in other words, a case where X and Y are connected without another element or another circuit interposed therebetween). In other words, when “electrically connected” is explicitly stated, it is the same as a case where only “connected” is explicitly stated.

[0251] Note that, for example, in the case where the source (or first terminal, etc.) of the transistor is electrically connected to X through Z1 (or not through Z1) and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 (or not through Z2) and in the case where the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1 and another part of Z1 is directly connected to X, the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2 and another part of Z2 is directly connected to Y, it can be displayed as follows.

[0252] For example, it can be expressed as "X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y". Alternatively, it can be expressed as "the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y". Alternatively, it can be expressed as "X is electrically connected to Y through the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are sequentially arranged to be connected to each other". By specifying the connection order in the circuit structure using the same expression method as this example, the source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expressions are merely examples and are not limited to the above expressions. Here, X, Y, Z1, and Z2 are objects (eg, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0253] In addition, even if independent components are electrically connected to each other on a circuit diagram, one component may have the functions of multiple components. For example, when a portion of a wiring is used as an electrode, one conductive film has the functions of both wiring and electrode. Therefore, the category of "electrically connected" in this specification also includes the case where one conductive film has the functions of multiple components.

[0254] "Parallel, Perpendicular"

[0255] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, it also includes a state where the angle is greater than -5° and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, it also includes a state where the angle is greater than 85° and less than 95°. In addition, "approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0256] [Explanation of symbols]

[0257] 10: Camera device, 11: Driver, 12: Driver, 13: Driver, 31: Conductive layer, 32: Conductive layer, 33: Conductive layer, 34: Conductive layer, 35: Back gate, 36: Region, 37: Conductive layer, 40: Silicon substrate, 41: Insulating layer, 42: Insulating layer, 43: Insulating layer, 45: Semiconductor layer, 46: Insulating layer, 80: Insulating layer, 81: Light shielding layer, 82: Organic resin layer, 83: Color filter, 83a: Color filter, 83b: Color filter, 83c: Color filter, 84: Microlens array, 85: Optical conversion layer, 86: Insulating layer, 100: Pixel, 100a: Output terminal, 100b: Output terminal, 101: Photoelectric conversion element, 102: Transistor, 103: Crystal transistor, 104: capacitor, 105: transistor, 106: transistor, 107: transistor, 108: transistor, 111: wiring, 112: wiring, 113a: wiring, 113b: wiring, 113c: wiring, 113d: wiring, 114: wiring, 115: wiring, 117: wiring, 118: wiring, 119: wiring, 200: pooling module, 203: switch, 204: switch, 210: pooling circuit, 210a: wiring, 211: wiring, 211a: wiring, 211b: wiring, 212: operation circuit, 212a: transistor, 212b: transistor, 212c: transistor, 220: comparison module, 221: determination circuit, 221a: input terminal , 221b: input terminal, 221c: output terminal, 223a: transistor, 223b: transistor, 224a: input terminal, 224b: output terminal, 230: comparison circuit, 230a: comparison circuit, 230b: comparison circuit, 230c: comparison circuit, 231a: input terminal, 231b: input terminal, 231c: output terminal, 232: wiring, 236: transistor, 241: transistor, 242: transistor, 243: transistor, 244: transistor, 245: transistor, 246: transistor, 250: analog-digital conversion circuit, 251: output circuit, 410: packaging substrate, 411: packaging substrate, 420: glass cover, 421: lens cover, 43 0: adhesive, 435: lens, 440: bump, 441: connection pad, 450: image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode pad, 470: lead, 471: lead, 490: IC chip, 911: housing, 912: display unit, 919: camera, 932: display unit, 933: housing and wristband, 939: camera, 951: bracket, 952: camera unit, 953: protective cover, 961: housing, 962: shutter button, 963: microphone, 965: lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation key, 975: lens, 976: connection part,981: Housing, 982: Display unit, 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

1. A photographing device, include: Multiple pixels in the capture area; as well as A current mirror circuit includes a first transistor and a second transistor, wherein the plurality of pixels and the current mirror circuit are stacked, The plurality of pixels includes a first plurality of pixels and a second plurality of pixels, One of a source and a drain of the first transistor is electrically connected to a first wiring to which a current based on an analog signal obtained from the first plurality of pixels is input, The one of the source and the drain of the first transistor is electrically connected to the gate of the first transistor, The other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, the other of the source and the drain of the second transistor is electrically connected to a second wiring to which a current based on an analog signal obtained from the second plurality of pixels is input, and A gate of the second transistor is electrically connected to the gate of the first transistor.

2. The photographing device according to claim 1, wherein the transistors included in the plurality of pixels are n-channel transistors, and The first transistor and the second transistor are p-channel transistors.

Images