Method for manufacturing optical semiconductor device

Abstract

The optical semiconductor device of the present invention comprises: a mesa strip (8) formed by sequentially stacking an n-type InP cladding layer (2), an active layer (3) and a p-type InP cladding layer (4) on the surface of an n-type InP substrate (1); an Fe-doped semi-insulating InP layer (9) buried on both sides of the mesa strip in a manner higher than the height of the mesa strip; an n-type InP barrier layer (10) stacked on the surface of the Fe-doped semi-insulating InP layer on both sides of the mesa strip at a narrower interval than the active layer in a region corresponding to the central portion of the active layer (3); a p-type InP cladding layer (6) formed on the back side of both ends of the mesa strip side of the n-type InP barrier layer; and a p-type InP cladding layer (12) buried in the top of the mesa strip, the p-type InP cladding layer and the n-type InP barrier layer, the p-type InP cladding layer being set to have a higher carrier concentration than the p-type InP cladding layer and the p-type InP cladding layer to reduce leakage current.

Description

Technical Field

[0001] The present application relates to an optical semiconductor device and a method for manufacturing the same. Background Art

[0002] In recent years, optical communications have become significantly faster, and applications that require high-speed operation of semiconductor lasers have increased. In addition, direct modulation semiconductor lasers that directly modulate distributed feedback semiconductor lasers for achieving high-speed operation at low cost are sought.

[0003] In a semiconductor laser of a direct modulation type operating at high speed, it is necessary to reduce parasitic capacitance. In particular, in an embedded structure in which an embedded layer is provided on both sides of an active layer, it is effective to use a semi-insulating semiconductor layer for the embedded layer. The semi-insulating semiconductor layer generally uses an InP layer with iron (Fe) as a dopant. However, although the Fe-doped semi-insulating InP layer captures electrons, it does not capture holes (holes). In the semiconductor laser of the embedded structure, the side of the p-type InP cladding layer contacts the Fe-doped semi-insulating InP layer. When holes are injected from the p-type InP layer to the Fe-doped semi-insulating InP layer, leakage current flows due to the recombination of the injected holes and the captured electrons. In order to reduce the leakage current, an n-type InP barrier layer for capturing holes is provided between the p-type InP layer and the Fe-doped semi-insulating InP layer.

[0004] Patent document 1 discloses, as a method for reducing leakage current, an example in which after forming an n-type InP buried layer (barrier layer), the width of the insulating film is processed to be narrower, a portion of the p-type InP cladding layer is etched to be thinner, and then an n-type buried layer (barrier layer) is formed.

[0005] Patent Document 1: Japanese Patent No. 5545670 (paragraph 0025, Figure 3 )

[0006] However, when forming the n-type InP barrier layer, the barrier layer is selectively grown, so the width of the end portion perpendicular to the active layer becomes thinner on the upper part of the active layer, and the effect of blocking holes is weak, and there is a problem that the holes to be injected into the active layer are not captured and become leakage current. In addition, in Patent Document 1, although the part of the side surface of the p-type InP cladding layer that contacts the Fe-doped semi-insulating InP layer is reduced, there is a problem that the leakage current is not sufficiently suppressed. Summary of the invention

[0007] The present application discloses a technology for solving the above-mentioned problems, and an object of the present application is to provide an optical semiconductor device with reduced leakage current and a method for manufacturing the same.

[0008] The optical semiconductor device disclosed in the present application is characterized in that it comprises: a mesa strip formed by stacking a first conductive type cladding layer, an active layer and a first second conductive type cladding layer in sequence on the surface of a first conductive type semiconductor substrate; a buried layer buried in both sides of the mesa strip in a manner higher than the height of the mesa strip; a first conductive type barrier layer stacked on the surface of the buried layer on both sides of the mesa strip at a narrower interval than the active layer in a region corresponding to the central portion of the active layer; a second second conductive type cladding layer formed on the back side of both end portions of the mesa strip side of the first conductive type barrier layer; and a third second conductive type cladding layer buried in the top of the mesa strip, the second second conductive type cladding layer and the first conductive type barrier layer, the carrier concentration of the second second conductive type cladding layer being formed to be higher than the carrier concentration of the first second conductive type cladding layer and the third second conductive type cladding layer.

[0009] The manufacturing method of the optical semiconductor device disclosed in the present application is characterized in that it includes the following steps: a step of sequentially stacking a first conductive type cladding layer, an active layer and a first second conductive type cladding layer on the surface of a first conductive type semiconductor substrate, and then sequentially stacking an etching stop layer and a second second conductive type cladding layer to form a semiconductor layer; a step of etching the above semiconductor layer to form a mesa strip; a step of forming a buried layer on both sides of the above mesa strip; a step of forming a first conductive type barrier layer on the top of the above mesa strip and on the surface of the above buried layer; a step of forming a mask that exposes a region of the above first conductive type barrier layer corresponding to the central portion of the above active layer, and then etching until the above etching stop layer is reached to form an opening; a step of removing the above mask and the above etching stop layer; and a step of stacking a third second conductive type cladding layer on the above opening and on the surface of the above first conductive type barrier layer, and then stacking a second conductive type contact layer, the carrier concentration of the second second conductive type cladding layer being formed to be higher than the carrier concentrations of the first second conductive type cladding layer and the third second conductive type cladding layer.

[0010] In addition, the manufacturing method of the optical semiconductor device disclosed in the present application is characterized in that it includes the following steps: a step of stacking a first conductive type cladding layer, an active layer and a first second conductive type cladding layer in sequence on the surface of a first conductive type semiconductor substrate, and then stacking a second second conductive type cladding layer to form a semiconductor layer; a step of etching the above-mentioned semiconductor layer to form a mesa strip; a step of forming a buried layer on both sides of the above-mentioned mesa strip; a step of forming a first conductive type barrier layer on the top of the above-mentioned mesa strip and on the surface of the above-mentioned buried layer; a step of etching the first conductive type barrier layer and the above-mentioned second second conductive type cladding layer to form an opening after forming a mask that exposes the area of ​​the above-mentioned first conductive type barrier layer corresponding to the central part of the above-mentioned active layer; a step of removing the above-mentioned mask; and a step of stacking a second conductive type contact layer after stacking a third second conductive type cladding layer on the above-mentioned opening and on the surface of the above-mentioned first conductive type barrier layer, wherein the carrier concentration of the second second conductive type cladding layer is formed to be higher than the carrier concentration of the above-mentioned first second conductive type cladding layer and the above-mentioned third second conductive type cladding layer.

[0011] According to the present application, leakage current from the active layer to the first conductivity type barrier layer can be reduced, thereby achieving a reduction in laser oscillation threshold current and an increase in light output. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a cross-sectional view showing the structure of the optical semiconductor device according to the first embodiment.

[0013] Figure 2 This is a flowchart showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0014] Figure 3 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0015] Figure 4 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0016] Figure 5 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0017] Figure 6 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0018] Figure 7 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0019] Figure 8 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0020] Fig. 9 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0021] Fig.10 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0022] Fig.11 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the first embodiment.

[0023] Fig.12 It is a cross-sectional view showing the structure of an optical semiconductor device according to the second embodiment.

[0024] Fig.13 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the second embodiment.

[0025] Fig.14 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the second embodiment.

[0026] Fig.15 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the second embodiment.

[0027] Fig.16 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the second embodiment.

[0028] Fig.17 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the second embodiment.

[0029] Fig.18 It is a cross-sectional view showing the structure of an optical semiconductor device according to a third embodiment.

[0030] Fig.19 This is a flowchart showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0031] Fig. 20 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0032] Fig.21 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0033] Fig. 22 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0034] Fig.23 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0035] Fig.24It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0036] Fig.25 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0037] Fig.26 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the third embodiment.

[0038] Fig. 27 It is a cross-sectional view showing the structure of an optical semiconductor device according to a fourth embodiment.

[0039] Fig.28 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the fourth embodiment.

[0040] Fig.29 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the fourth embodiment.

[0041] Fig.30 It is a cross-sectional view showing the manufacturing process of the optical semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION

[0042] Implementation Method 1

[0043] Figure 1 1 is a cross-sectional view showing the structure of an optical semiconductor device 101 according to Embodiment 1 of the present application. Figure 1 As shown, the optical semiconductor device 101 has mesa stripes 8 extending in the

[011] direction formed on the surface of an n-type InP substrate 1 (first conductivity type semiconductor) in the plane orientation (110). The mesa stripes 8 have a width W1 of 1.4 μm, for example.

[0044] The mesa strip 8 is provided on the surface of the n-type InP substrate 1, and is formed by sequentially stacking an n-type InP cladding layer 2 (a semiconductor of the first conductivity type), an active layer 3, a p-type InP cladding layer 4 (a semiconductor of the second conductivity type) as a first cladding layer of the second conductivity type, a p-type InP cladding layer 6 (a semiconductor of the second conductivity type) as a second cladding layer of the second conductivity type, and a p-type InP cladding layer 12 (a semiconductor of the second conductivity type) as a third cladding layer of the second conductivity type. Both sides of the mesa strip 8 are buried by an Fe-doped semi-insulating InP layer 9 (a semiconductor of any conductivity type) as a buried layer so as to cover the entire side surfaces of the mesa strip 8.

[0045] An n-type InP barrier layer 10 (first conductivity type semiconductor) is provided on the surface of the Fe-doped semi-insulating InP layer 9, but is formed above the active layer 3 with a width W2 narrower than the width W1 of the active layer 3. The width W2 is, for example, 1.0 μm.

[0046] The p-type InP cladding layer 6 is formed at the back end of the n-type InP barrier layer 10 with a width W3 above the active layer 3. The width W3 is, for example, 0.2 μm. The thickness D2 of the n-type InP barrier layer 10 above the active layer 3 is equal to the thickness D1 of the portion (approximately several tens of μm) sufficiently away from the active layer 3. The thickness D1 and the thickness D2 can be arbitrarily set between 300 and 1000 nm.

[0047] A p-type InP cladding layer 12 is formed between the surface of the p-type InP cladding layer 4 and the back surface of the n-type InP barrier layer 10, between the interrupted n-type InP barrier layers 10, and on the surface of the n-type InP barrier layer 10. A p-type InGaAs contact layer 13 (a semiconductor of the second conductivity type) is formed on the surface of the p-type InP cladding layer 12. A p-side electrode 14 is formed on the surface of the p-type InGaAs contact layer 13. An n-side electrode 15 is formed on the back surface of the n-type InP substrate 1.

[0048] The carrier concentration of the p-type InP cladding layer 6 is set to be greater than the carrier concentrations of the p-type InP cladding layer 4 and the p-type InP cladding layer 12. The carrier concentration can be 0.5 to 3.0×10E+18cm -3 Any setting in between.

[0049] Thus, by providing a p-type InP cladding layer 6 having a higher carrier concentration than the p-type InP cladding layer 4 between the p-type InP cladding layer 4 and the n-type InP barrier layer 10 above the active layer 3, the energy barrier of the pn junction interface with the n-type InP barrier layer becomes higher, thereby reducing the leakage current from the active layer to the n-type InP barrier layer. In addition, by providing a p-type InP cladding layer having a high carrier concentration, the element resistance can also be reduced.

[0050] Next, a method for manufacturing the optical semiconductor device 101 according to the first embodiment of the present application will be described. Figure 2 It is a flowchart showing the manufacturing process of the optical semiconductor device 101 . Figures 3 to 11 It means Figure 2 Corresponding cross-sectional views of each manufacturing step of the optical semiconductor device 101 .

[0051] First, if Figure 3 As shown in the figure, on the surface of the n-type InP substrate 1 with a plane orientation of (110), an n-type InP cladding layer 2 (thickness 100-200nm, carrier concentration 0.1-1.0×10E+18cm) is sequentially stacked by MOCVD (Metal Organic Chemical Vapour Deposition: Metal Organic Chemical Vapor Deposition) method. -3), an active layer 3 of a multi-quantum well (MQW) structure that becomes a light-emitting layer, a p-type InP cladding layer 4 (thickness 50 to 400 nm, carrier concentration 0.5 to 3.0×10E+18 cm -3 ), p-type InGaAsP etching stop layer 5 (thickness 50 to 400 nm, carrier concentration 0.5 to 3.0×10E+18 cm -3 ), and a p-type InP cladding layer 6 (thickness 50 to 400 nm, carrier concentration 1.0 to 3.0×10E+18 cm -3 ) is then performed on the surface of the p-type InP cladding layer 6 by SiO 2 After the insulating film 7 is formed, it is processed to a desired ridge width (step S201).

[0052] However, the carrier concentration of the p-type InP cladding layer 6 is set higher than the carrier concentration of the p-type InP cladding layer 4. The carrier concentration can be 0.5 to 3.0×10E+18 cm -3 The ridge width is about 0.5 to 2.0 μm.

[0053] Then, if Figure 4 As shown, using the insulating film 7 as a mask, dry etching is performed from the p-type InP cladding layer 6 to the middle of the n-type InP cladding layer 2 or the n-type InP substrate 1 to form the mesa stripes 8 (step S202).

[0054] Although dry etching is performed here, wet etching may also be used to form the mesa stripes 8. The etching depth is about 1 to 4 μm. The mesa stripes extend in the

[011] direction.

[0055] Next, if Figure 5 As shown, on both sides of the mesa strip 8, a semi-insulating InP layer 9 (thickness 1000-4000nm, carrier concentration 0.01-9.0×10E+18cm) doped with Fe is used. -3 ) performs buried growth (step S203).

[0056] At this time, the Fe-doped semi-insulating InP layer 9 is grown so as to cover the entire side surfaces of the mesa stripes 8 .

[0057] Then, if Figure 6 As shown, the convex portions of the surface of the Fe-doped semi-insulating InP layer 9 on both sides of the mesa strip 8 are removed and flattened using an etchant containing hydrogen bromide and acetic acid (step S204).

[0058] Next, if Figure 7As shown, after the insulating film 7 is removed by using buffered hydrofluoric acid or hydrofluoric acid, an n-type InP barrier layer 10 (thickness 300 to 1000 nm, carrier concentration 2.0 to 9.0×10E+18 cm -3 ), and an n-type InGaAs layer 11 (thickness 50 to 200 nm, carrier concentration 0.5 to 5.0×10E+18 cm) as a mask for selective etching. -3 )(Step S205).

[0059] Then, if Figure 8 As shown, an opening of a resist layer (not shown) narrower than the width of the active layer is formed above the active layer 3 by photolithography, and only the n-type InGaAs layer 11 is etched by dry etching or nitric acid (step S206).

[0060] Next, if Fig. 9 As shown, the n-type InGaAs layer 11 is used as an etching mask, and an etchant such as hydrochloric acid is used to selectively etch the n-type InP barrier layer 10 above the active layer 3 and the p-type InP cladding layer 6 until the p-type InGaAsP etching stop layer 5 is reached (step S207).

[0061] Then, if Fig.10 As shown, the n-type InGaAs layer 11 and the p-type InGaAsP etching stopper layer 5 are selectively etched using nitric acid or the like (step S208).

[0062] Next, if Fig.11 As shown, a p-type InP cladding layer 12 (thickness 100 to 4000 nm, carrier concentration 0.1 to 3.0×10E+18 cm) is sequentially stacked. -3 ) and a p-type InGaAs contact layer 13 (thickness 100 to 1000 nm, carrier concentration 1.0 to 10.0×10E+18 cm -3 )(Step S209).

[0063] At this time, the carrier concentration of the p-type InP cladding layer 12 is set to be lower than the carrier concentration of the p-type InP cladding layer 6 .

[0064] Finally, a p-side electrode 14 is provided on the surface of the p-type InGaAs contact layer 13, and an n-side electrode 15 is provided on the back surface of the n-type InP substrate 1, thereby obtaining Figure 1 An optical semiconductor device 101 is shown.

[0065] As described above, the optical semiconductor device 101 according to the first embodiment comprises: a mesa strip 8 formed by stacking an n-type InP cladding layer 2, an active layer 3, and a p-type InP cladding layer 4 in this order on the surface of an n-type InP substrate 1; an Fe-doped semi-insulating InP layer 9 embedded on both sides of the mesa strip 8 in a manner higher than the height of the mesa strip 8; an n-type InP barrier layer 10 stacked on the surface of the Fe-doped semi-insulating InP layer 9 on both sides of the mesa strip 8 at a distance narrower than the active layer 3 in a region corresponding to the central portion of the active layer 3; and a p-type InP cladding layer 6 formed in the shape of a The back side of the two ends of the mesa strip 8 side formed on the n-type InP barrier layer 10; and the p-type InP cladding layer 12, which is buried in the top of the mesa strip 8, the p-type InP cladding layer 6 and the n-type InP barrier layer 10, the carrier concentration of the p-type InP cladding layer 6 is formed to be higher than the carrier concentration of the p-type InP cladding layer 4 and the p-type InP cladding layer 12, so the energy barrier of the pn junction interface between the n-type InP barrier layer becomes higher, which can reduce the leakage current from the active layer to the n-type InP barrier layer, thereby achieving the reduction of the laser oscillation threshold current and the high output of the light output.

[0066] In addition, by providing a p-type InP cladding layer with a high carrier concentration, the increase in light loss can be suppressed and the element resistance can be reduced. Furthermore, when forming an n-type InP barrier layer, since selective growth is not used, the film thickness can be thickened even on the upper part of the active layer, and the effect of reducing leakage current can be expected.

[0067] Implementation Method 2

[0068] In the first embodiment, the Fe-doped semi-insulating InP layer 9 is planarized. However, in the second embodiment, a case where the planarization is not performed will be described.

[0069] Fig.12 2 is a cross-sectional view showing the structure of an optical semiconductor device 102 according to Embodiment 2 of the present application. Fig.12 As shown, the optical semiconductor device 102 is different from the optical semiconductor device 101 of the first embodiment in that an Fe-doped semi-insulating InP layer 9 whose surface is not flattened is formed. The other structures of the optical semiconductor device 102 of the second embodiment are the same as those of the optical semiconductor device 101 of the first embodiment, and the corresponding parts are marked with the same Figure 1 The same reference numerals are used and their descriptions are omitted.

[0070] Next, a method for manufacturing the optical semiconductor device 102 according to the second embodiment of the present application is described. The manufacturing process of the optical semiconductor device 102 according to the second embodiment is the same as the flowchart of the manufacturing process of the optical semiconductor device 101 according to the first embodiment except that the flowchart of the manufacturing process of the optical semiconductor device 101 according to the first embodiment is omitted. Figure 2 ) in the planarization process of the buried layer ( Figure 2 Except for step S204), the same Figure 2 . Figures 13 to 17 It means Fig.12 Corresponding cross-sectional views of each manufacturing step of the optical semiconductor device 102 .

[0071] First, in the method for manufacturing the optical semiconductor device 102 according to the second embodiment, the semiconductor layer forming step (step S201, Figure 3 ) to the buried layer forming step (step S203, Figure 5 ) are the same so the description is omitted.

[0072] Next, in step S203, the mesa strips 8 are buried by the Fe-doped semi-insulating InP layer 9 (see Figure 5 ),like Fig.13 As shown, the insulating film 7 is removed by using buffered hydrofluoric acid or hydrofluoric acid, and an n-type InP barrier layer 10 (thickness 300 to 1000 nm, carrier concentration 2.0 to 9.0×10E+18 cm -3 ), and an n-type InGaAs layer 11 (thickness 50 to 200 nm, carrier concentration 0.5 to 5.0×10E+18 cm) as a mask for selective etching. -3 )(Step S205).

[0073] Next, if Fig.14 As shown, an opening of a resist layer (not shown) narrower than the width of the active layer is formed above the active layer 3 by photolithography, and only the n-type InGaAs layer 11 is etched by dry etching or nitric acid (step S206).

[0074] Then, if Fig.15 As shown, the n-type InGaAs layer 11 is used as an etching mask, and an etchant such as hydrochloric acid is used to selectively etch the n-type InP barrier layer 10 above the active layer 3 and the p-type InP cladding layer 6 until the p-type InGaAsP etching stop layer 5 is reached (step S207).

[0075] Next, if Fig.16 As shown, the n-type InGaAs layer 11 and the p-type InGaAsP etching stopper layer 5 are selectively etched using nitric acid or the like (step S208).

[0076] Then, if Fig.17 As shown, a p-type InP cladding layer 12 (thickness 100 to 4000 nm, carrier concentration 0.1 to 3.0×10E+18 cm) is sequentially stacked. -3) and a p-type InGaAs contact layer 13 (thickness 100 to 1000 nm, carrier concentration 1.0 to 10.0×10E+18 cm -3 )(Step S209).

[0077] At this time, the carrier concentration of the p-type InP cladding layer 12 is set to be lower than the carrier concentration of the p-type InP cladding layer 6 .

[0078] Finally, a p-side electrode 14 is provided on the surface of the p-type InGaAs contact layer 13, and an n-side electrode 15 is provided on the back surface of the n-type InP substrate 1, thereby obtaining Fig.12 An optical semiconductor device 102 is shown.

[0079] As described above, according to the optical semiconductor device 102 involved in the present embodiment 2, in the manufacturing method of the optical semiconductor device 102, the flattening step of the Fe-doped semi-insulating InP layer 9 in the manufacturing process of the optical semiconductor device 101 involved in the present embodiment 1 is omitted, so that not only the same effect as that of the embodiment 1 can be obtained, but also the manufacturing cost can be reduced.

[0080] Implementation 3

[0081] In the first and second embodiments, the case where the p-type InP cladding layer 6 is not directly stacked on the p-type InP cladding layer 4 is described. However, in the third embodiment, the case where the p-type InP cladding layer 6 is directly stacked is described.

[0082] Fig.18 2 is a cross-sectional view showing the structure of an optical semiconductor device 103 according to Embodiment 3 of the present application. Fig.18 As shown, in the optical semiconductor device 103, the p-type InP cladding layer 6 formed on the back end of the n-type InP barrier layer 10 is stacked on the surface end of the p-type InP cladding layer 4. As a result, the Fe-doped semi-insulating InP layer 9 is not in contact with the p-type InP cladding layer 12, but is in contact with the p-type InP cladding layer 4. The other structures of the optical semiconductor device 103 of the third embodiment are the same as those of the optical semiconductor device 101 of the first embodiment, and the corresponding parts are marked with the same Figure 1 The same reference numerals are used and their descriptions are omitted.

[0083] Next, a method for manufacturing the optical semiconductor device 103 according to the third embodiment of the present application will be described. Fig.19 1 is a flowchart showing the manufacturing process of the optical semiconductor device 103. However, the manufacturing process of the optical semiconductor device 103 of the third embodiment is different from the flowchart of the manufacturing process of the optical semiconductor device 101 of the first embodiment ( Figure 2 ) in the planarization process of the buried layer ( Figure 2The same as step S204) up to step S204, Figure 2 . Figure 20 to Figure 26 It means Fig.18 Corresponding cross-sectional views of each manufacturing step of the optical semiconductor device 103 .

[0084] First, if Fig. 20 As shown in FIG. 1 , an n-type InP cladding layer 2 (thickness 100 to 200 nm, carrier concentration 0.1 to 1.0×10E+18 cm) is sequentially stacked on the surface of an n-type InP substrate 1 with a plane orientation (110) by MOCVD. -3 ), an active layer 3 of a multi-layer quantum well (MQW) structure that becomes a light-emitting layer, a p-type InP cladding layer 4 (thickness 50 to 400 nm, carrier concentration 0.5 to 3.0×10E+18 cm -3 ), and a p-type InP cladding layer 6 (thickness 50 to 400 nm, carrier concentration 1.0 to 3.0×10E+18 cm -3 ) is then performed on the surface of the p-type InP cladding layer 6 by SiO 2 After the insulating film 7 is formed, it is processed to a desired ridge width (step S201).

[0085] However, the carrier concentration of the p-type InP cladding layer 6 is set higher than the carrier concentration of the p-type InP cladding layer 4. The carrier concentration can be 0.5 to 3.0×10E+18 cm -3 The ridge width is about 0.5 to 2.0 μm. Unlike the optical semiconductor device 101 of the first embodiment, the p-type InGaAsP etching stopper layer 5 is not stacked.

[0086] Then, if Fig.21 As shown, using the insulating film 7 as a mask, dry etching is performed from the p-type InP cladding layer 6 to the middle of the n-type InP cladding layer 2 or the n-type InP substrate 1 to form the mesa stripes 8 (step S202).

[0087] Although dry etching is performed here, wet etching may also be used to form the mesa stripes 8. The etching depth is about 1 to 4 μm. The mesa stripes extend in the

[011] direction.

[0088] Next, if Fig. 22 As shown, on both sides of the mesa strip 8, a semi-insulating InP layer 9 doped with Fe (thickness 1000-4000nm, carrier concentration 0.01-9.0×10E+18cm -3 ) performs buried growth (step S203).

[0089] At this time, the Fe-doped semi-insulating InP layer 9 is grown so as to cover the entire side surfaces of the mesa stripes 8 .

[0090] Then, if Fig.23 As shown, the convex portions of the surface of the Fe-doped semi-insulating InP layer 9 on both sides of the mesa strip 8 are removed and flattened using an etchant containing hydrogen bromide and acetic acid (step S204).

[0091] Next, if Fig.24 As shown, after the insulating film 7 is removed by using buffered hydrofluoric acid or hydrofluoric acid, an n-type InP barrier layer 10 (thickness 300 to 1000 nm, carrier concentration 2.0 to 9.0×10E+18 cm -3 )(Step S1901).

[0092] Then, if Fig.25 As shown, by photolithography, an opening of the resist layer (not shown) which is narrower than the width of the active layer is formed above the active layer 3, and the n-type InP barrier layer 10 and the p-type InP cladding layer 6 are etched by dry etching using the resist layer as an etching mask (step S1902).

[0093] Next, if Fig.26 As shown, a p-type InP cladding layer 12 (thickness 100 to 4000 nm, carrier concentration 0.1 to 3.0×10E+18 cm -3 ) and a p-type InGaAs contact layer 13 (thickness 100 to 1000 nm, carrier concentration 1.0 to 10.0×10E+18 cm -3 )(Step S1903).

[0094] At this time, the carrier concentration of the p-type InP cladding layer 12 is set to be lower than the carrier concentration of the p-type InP cladding layer 6 .

[0095] Finally, a p-side electrode 14 is provided on the surface of the p-type InGaAs contact layer 13, and an n-side electrode 15 is provided on the back surface of the n-type InP substrate 1, thereby obtaining Fig.18 The optical semiconductor device 103 is shown.

[0096] As described above, according to the optical semiconductor device 103 involved in the present embodiment 3, since the p-type InP cladding layer 6 formed on the back end of the n-type InP barrier layer 10 is stacked on the surface of the p-type InP cladding layer 4, the area where the p-type InP cladding layer and the Fe-doped semi-insulating InP layer are in contact is narrower, which can not only obtain the same effect as in the embodiment 1, but also further reduce the leakage current from the active layer to the n-type InP barrier layer.

[0097] Implementation 4

[0098] In the third embodiment, the Fe-doped semi-insulating InP layer 9 is planarized. However, in the fourth embodiment, a case where the planarization is not performed will be described.

[0099] Fig. 27 1 is a cross-sectional view showing the structure of an optical semiconductor device 104 according to Embodiment 4 of the present application. Fig. 27 As shown, the optical semiconductor device 104 is different from the optical semiconductor device 103 of the third embodiment in that the Fe-doped semi-insulating InP layer 9 whose surface is not flattened is formed. The other structures of the optical semiconductor device 104 of the fourth embodiment are the same as those of the optical semiconductor device 10 of the third embodiment, and the corresponding parts are marked with Fig.18 The same reference numerals are used and their descriptions are omitted.

[0100] Next, a method for manufacturing the optical semiconductor device 104 according to the fourth embodiment of the present application is described. The manufacturing process of the optical semiconductor device 104 according to the fourth embodiment is the same as the flowchart of the manufacturing process of the optical semiconductor device 103 according to the third embodiment except that the flowchart is omitted. Figure 2 , Fig.19 ) in the planarization process of the buried layer ( Figure 2 Except for step S204), the same Figure 2 as well as Fig.19 . Figures 28 to 30 It means Fig. 27 Corresponding cross-sectional views of each manufacturing step of the optical semiconductor device 104 .

[0101] First, in the method for manufacturing the optical semiconductor device 104 according to the fourth embodiment, the semiconductor layer forming step (steps S201, S204) in the method for manufacturing the optical semiconductor device 103 according to the third embodiment is performed. Fig. 20 ) to the buried layer forming step (step S203, Fig. 22 ) are the same as above, and the description thereof is omitted.

[0102] Next, in step S203, the mesa strips 8 are buried by the Fe-doped semi-insulating InP layer 9 (see Fig. 22 ),like Fig.28 As shown, after the insulating film 7 is removed by using buffered hydrofluoric acid or hydrofluoric acid, an n-type InP barrier layer 10 (thickness 300 to 1000 nm, carrier concentration 2.0 to 9.0×10E+18 cm -3 )(Step S1901).

[0103] Then, if Fig.29As shown, by photolithography, an opening of the resist layer (not shown) which is narrower than the width of the active layer is formed above the active layer 3, and the n-type InP barrier layer 10 and the p-type InP cladding layer 6 are etched by dry etching using the resist layer as an etching mask (step S1902).

[0104] Next, if Fig.30 As shown, a p-type InP cladding layer 12 (thickness 100 to 4000 nm, carrier concentration 0.1 to 3.0×10E+18 cm -3 ) and p-type InGaAs contact layer 13 (thickness 100 to 1000 nm, carrier concentration 1.0 to 10.0×10E+18 cm -3 )(Step S1903).

[0105] At this time, the carrier concentration of the p-type InP cladding layer 12 is set to be lower than the carrier concentration of the p-type InP cladding layer 6 .

[0106] Finally, a p-side electrode 14 is provided on the surface of the p-type InGaAs contact layer 13, and an n-side electrode 15 is provided on the back surface of the n-type InP substrate 1, thereby obtaining Fig. 27 The optical semiconductor device 104 is shown.

[0107] As described above, according to the optical semiconductor device 104 involved in the present embodiment 4, in the manufacturing method of the optical semiconductor device 104, the flattening step of the Fe-doped semi-insulating InP layer 9 in the manufacturing process of the optical semiconductor device 103 involved in the present embodiment 3 is omitted, so that not only the same effect as that of the embodiment 3 can be obtained, but also the manufacturing cost can be reduced.

[0108] Although the present application describes various illustrative embodiments and examples, the various features, forms and functions described in one or more embodiments are not limited to the application of a specific embodiment, and can also be applied to the embodiments alone or in various combinations. Therefore, countless unillustrated variations can be imagined within the technical scope disclosed in the present application specification. For example, it includes the case where at least one constituent element is deformed, added or omitted, and also includes the case where at least one constituent element is extracted and combined with constituent elements of other embodiments.

[0109] Description of Reference Numerals

[0110] 1...n-type InP substrate; 2...n-type InP cladding layer; 3...active layer; 4...p-type InP cladding layer (first second conductivity type cladding layer); 5...p-type InGaAsP etching stop layer; 6...p-type InP cladding layer (second second conductivity type cladding layer); 8...mesa strip; 9...Fe-doped semi-insulating InP layer (buried layer); 10...n-type InP barrier layer; 12...p-type InP cladding layer (third second conductivity type cladding layer); 101, 102, 103, 104...optical semiconductor device.

Claims

1. A method for manufacturing an optical semiconductor device, characterized in that: The method for manufacturing an optical semiconductor device comprises the following steps: A step of sequentially stacking a first conductive type cladding layer, an active layer, and a first second conductive type cladding layer on a surface of a first conductive type semiconductor substrate, and then sequentially stacking an etching stop layer and a second second conductive type cladding layer to form a semiconductor layer; A step of etching the semiconductor layer to form mesa strips; A process of forming a buried layer on both sides of the mesa strip; The step of forming a first conductive type barrier layer on the top of the mesa strip and on the surface of the buried layer; After forming a mask that exposes a region of the first conductive type barrier layer corresponding to a central portion of the active layer when viewed in a strip cross-sectional direction, etching is performed until the etching stop layer is reached to form an opening; A process of removing the mask and the etching stop layer; as well as After laminating a third second-conductivity-type cladding layer on the opening and the surface of the first-conductivity-type barrier layer, laminating a second-conductivity-type contact layer, The first second conductive type cladding layer having a carrier concentration lower than that of the second second conductive type cladding layer is formed on the surface of the active layer between the second second conductive type cladding layer and the active layer, and the carrier concentration of the third second conductive type cladding layer is set to be lower than that of the second second conductive type cladding layer. The first conductivity type is n-type, and the second conductivity type is p-type.

2. The method for manufacturing an optical semiconductor device according to claim 1, wherein: The etching stop layer uses a second conductivity type InGaAsP layer, and the mask uses a first conductivity type InGaAs layer.

3. The method for manufacturing an optical semiconductor device according to claim 1 or 2, wherein: The method includes performing a step of planarizing the buried layer after the step of forming the buried layer.

4. A method for manufacturing an optical semiconductor device, characterized in that: The method for manufacturing an optical semiconductor device comprises the following steps: A step of sequentially stacking a first conductive type cladding layer, an active layer, and a first second conductive type cladding layer on a surface of a first conductive type semiconductor substrate, and then stacking a second second conductive type cladding layer to form a semiconductor layer; A step of etching the semiconductor layer to form mesa strips; A process of forming a buried layer on both sides of the mesa strip; The step of forming a first conductive type barrier layer on the top of the mesa strip and on the surface of the buried layer; After forming a mask that exposes a region of the first conductive type barrier layer corresponding to a central portion of the active layer when viewed in a strip cross-sectional direction, the first conductive type barrier layer and the second conductive type cladding layer are etched to form an opening; A step of removing the mask; as well as After laminating a third second-conductivity-type cladding layer on the opening and the surface of the first-conductivity-type barrier layer, laminating a second-conductivity-type contact layer, The first second conductive type cladding layer having a carrier concentration lower than that of the second second conductive type cladding layer is formed on the surface of the active layer between the second second conductive type cladding layer and the active layer, and the carrier concentration of the third second conductive type cladding layer is set to be lower than that of the second second conductive type cladding layer. The first conductivity type is n-type, and the second conductivity type is p-type.

5. The method for manufacturing an optical semiconductor device according to claim 4, wherein: The method includes performing a step of planarizing the buried layer after the step of forming the buried layer.

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