A test method and test structure

Abstract

The application discloses a test method and a test structure, and belongs to the field of quantum chip manufacturing. The test method is realized based on measurement of a flip interconnection test component. The flip interconnection test component comprises a flip unit for flip interconnection. The flip unit provides a measurement line, and the flip unit forms an interconnection unit connected with the measurement line after flip interconnection. The flip unit gives a first arrangement pattern capable of representing the analog spacing of the aforementioned interconnection unit. Therefore, whether the arrangement of the interconnection unit is reasonable or optimal can be judged according to the measurement result of whether a short circuit occurs in the measurement line of two test units adjacent to each other and composed of the measurement line and the interconnection unit. Thus, the test structure and the test method can be used for verification detection of a theoretically designed flip interconnection scheme, so as to obtain an ideal flip interconnection scheme.

Description

Technical Field

[0001] This application belongs to the field of quantum chip fabrication, specifically involving a testing method and a testing structure. Background Technology

[0002] Due to the increasing number of qubits, flip-chip bonding is often chosen in the fabrication of quantum chips to transform the planar structure into a three-dimensional structure, thereby improving the utilization rate of unit area and reducing the chip size. Implementing flip-chip bonding requires the formation of bonding metal layers on both the upper and lower layer chips, and then the bonding metal layers of the upper and lower layer chips are bonded together to form a flip-chip.

[0003] Therefore, it is necessary to consider the arrangement pattern of the welded metal layers in order to make better use of the limited space. Summary of the Invention

[0004] In view of this, this application discloses a test method and test structure that can be used to verify whether the arrangement of solder joints in the designed flip-chip interconnect is reasonable (e.g., whether the spacing is too small, as too small a spacing may cause an undesirable short circuit) or better (e.g., the spacing is as small as possible without being too small to cause a short circuit), so as to obtain a denser and feasible arrangement of solder joint arrays, thereby providing higher space utilization while ensuring soldering quality and effect.

[0005] The solution presented in this application is implemented through the following steps.

[0006] A testing method that can be used to determine the target spacing between discrete interconnect structures in a flip-chip interconnect assembly.

[0007] The testing method includes:

[0008] At least one flip-chip interconnect test assembly is provided, wherein the flip-chip interconnect test assembly is fabricated by flip-chip cells via flip-chip interconnection, each flip-chip interconnect test assembly has at least two test cells, each test cell includes an interconnect cell and a measurement line, the measurement line is provided by the flip-chip cells, the interconnect cells are connected to the measurement lines, the flip-chip cells provide a first layout pattern, and the first layout pattern characterizes at least one simulated spacing of the interconnect cells, the simulated spacing being defined by the interconnect cells corresponding to two adjacent measurement lines respectively;

[0009] Measurement operations are performed on all test units, and a target spacing is obtained from at least one simulated spacing that satisfies a first preset condition based on the measurement operation with a negative result; wherein, the measurement operation includes measuring whether the measurement lines of two adjacent test units are short-circuited.

[0010] To make more efficient use of the limited space on a chip, the arrangement of the flip-chip interconnect structures needs to be considered. This means ensuring that the interconnect structures provide sufficient solder quality (e.g., ensuring that the solder joints between the two mating structures of the flip-chip interconnect do not stick together, otherwise it will cause a short circuit), while simultaneously making the interconnect structures as compact as possible, for example, by forming a dense arrangement of all interconnect structures.

[0011] In the test method of the above example of this application, the flip-chip interconnect test assembly includes flip-chip units. The flip-chip units are connected in an inverted interconnect manner through interconnect units to form the flip-chip interconnect test assembly, and the measurement lines and interconnect units therein constitute a test unit. The arrangement of the interconnect units can be given by the flip-chip units and characterized by a first arrangement pattern. Simultaneously, the first arrangement pattern can characterize the spacing between the interconnect units as a simulated spacing for testing, and the simulated spacing is defined by the interconnect units corresponding to two adjacent measurement lines.

[0012] Based on the aforementioned flip-chip interconnect test assembly, a short-circuit test is performed on any two adjacent measurement lines, and the simulated spacing of the interconnect units is examined based on the measurement results. If the measurement results indicate that the two adjacent measurement lines are not short-circuited, this measurement structure reflects that the interconnect units connected to these two measurement lines have not come into contact with each other due to the flip-chip interconnect operation. Furthermore, it can be concluded that the spacing of the interconnect units in the test unit used to fabricate the flip-chip interconnect test assembly is acceptable.

[0013] Therefore, the above testing method can determine whether the spacing arrangement (first arrangement pattern) corresponding to the corresponding interconnect units is reasonable—a short circuit indicates an unreasonable arrangement. Furthermore, after performing relevant measurements on different interconnect units corresponding to various spacings, multiple simulated spacings can be filtered based on these measurement results. That is, after completing the test operation to check whether adjacent measurement lines are short-circuited, based on the measurement operation where the measurement result is negative (a positive result indicates a short circuit, and a negative result indicates no short circuit), a simulated spacing that meets the first preset condition is obtained from at least one simulated spacing as the target spacing. The first preset condition can be adjusted as needed for different design purposes to obtain the target spacing that meets the design requirements.

[0014] According to some examples of this application, the number of simulated spacings in at least one simulated spacing of the first arrangement pattern representing interconnection units is at least two. Simulated spacings with the same value constitute one type, while simulated spacings with different values ​​constitute different types.

[0015] According to some examples of this application, when no test result is negative among the test results corresponding to the measurement operations of all test cells, the first layout pattern is modified to provide at least one simulated spacing with the simulated spacing value adjusted. That is, when the provided flip-chip interconnect test assembly has no non-short-circuited test cells after measurement, the first layout pattern needs to be modified, i.e., a new flip-chip interconnect test assembly made based on the modified first layout pattern is provided. Then, measurement operations can be performed on the new flip-chip interconnect test assembly.

[0016] According to some examples of this application, the first preset condition includes: when the number of measurement operations with a measurement result of no is one, the target spacing is the simulated spacing corresponding to the measurement with a measurement result of no.

[0017] According to some examples of this application, the first preset condition includes: when the number of measurement operations with a negative result is multiple, the target spacing is the minimum value among the simulated spacings corresponding to negative measurement results. It should be noted that when the number of measurement operations with a negative result is multiple, there may be a situation where all the corresponding simulated spacings are the same. Therefore, the minimum value mentioned here can be any one of these identical simulated spacings.

[0018] According to some examples of this application, each test cell also includes a non-interconnect cell fabricated by a stripping process, and the testing method further includes: determining that there is no residual adhesive in the area where the non-interconnect cell of the flip-chip interconnect test assembly is located. A non-interconnect cell indicates that the flip-chip interconnect test assembly has not undergone a flip-chip interconnect (e.g., bonding) operation. This determination of the absence of residual adhesive in the area where the non-interconnect cell is located can be performed before or after the measurement operation.

[0019] According to some examples of this application, the testing method further includes: before providing at least one flip-chip interconnect test component, determining a second arrangement pattern consisting of interconnect units that satisfies a second preset condition, and the second arrangement pattern represents at least one pre-screening spacing, wherein each spacing value in the at least one pre-screening spacing corresponds one-to-one with each spacing value in the at least one simulated spacing.

[0020] According to some examples of this application, the second preset condition includes: the duration of the peeling process in the process of making the second arrangement pattern composed of interconnecting units is less than the preset reference duration, and there is no adhesive residue after peeling.

[0021] Alternatively, the second preset condition includes: during the process of creating the second arrangement pattern composed of interconnecting units, there is residual adhesive after the peeling process, and the residual adhesive is removed without residue after washing.

[0022] According to some examples of this application, the second preset condition includes: detecting that the interconnecting unit does not have any deformation that deviates from the preset shape.

[0023] In a second aspect, examples of this application present a test structure comprising:

[0024] The first test chip has a first chip and a second chip configured with flip-chip interconnect;

[0025] At least two test units are configured in the first chip, each test unit including a first interconnect unit connected to the measurement lines;

[0026] The second interconnect unit is configured in the second chip;

[0027] The first interconnect unit and the second interconnect unit are matched and connected in a one-to-one correspondence to form an interconnect structure, and all interconnect structures are defined with an arrangement pattern having at least one spacing.

[0028] According to some examples in this application, the number of the first test chip is one;

[0029] Alternatively, when the number of spacings in at least one spacing is at least two, the number of first test chips is the same as the number of spacing types in at least one spacing, and interconnect structures with the same spacing are configured on the same test chip, while interconnect structures with different spacings are configured on different test chips.

[0030] According to some examples of this application, the cross-sectional shape of each first interconnect unit is a circle with the same diameter;

[0031] Alternatively, the cross-sectional shape of each first interconnect unit is a square with the same side length.

[0032] According to some examples of this application, all the first interconnecting units include first type units and second type units, and the shapes and dimensions of the first type units and the second type units are different. For example, the first type units and the second type units are both cylinders with a circular cross-section, but the diameters of their bases are different; or the first type units and the second type units are both quadrangular prisms with a square cross-section, but the side lengths of the squares are different.

[0033] According to some examples in this application, the number of measuring lines is at least three and arranged side by side in sequence;

[0034] Among them, the two outermost measurement lines connect to either the first type unit or the second type unit, and the remaining measurement lines between the two outermost measurement lines are simultaneously connected to both the first type unit and the second type unit. Furthermore, any two adjacent measurement lines are between either the first type unit or the second type unit of the transaction finger distribution.

[0035] Beneficial effects:

[0036] Compared with existing technologies, the testing method and testing structure exemplified in this application have at least the following advantages:

[0037] The testing method is a systematic approach that enables repeatable and scalable testing. It verifies the interconnect arrangement and dimensions of the designed flip-chip interconnect scheme, and even the rationality of material selection. Furthermore, it allows for the identification of optimal interconnect arrangements within flip-chip interconnect components. The test structure implemented in the example scheme is also simple and easy to manufacture, thus reducing testing costs and shortening chip manufacturing cycles during chip production. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0039] Figure 1 A flowchart illustrating the first testing method provided in this application embodiment;

[0040] Figure 2 A flowchart illustrating the second testing method provided in this application embodiment;

[0041] Figure 3 A layout diagram of various first arrangement graphics provided in the embodiments of this application;

[0042] Figure 4 A schematic diagram of the structure of a flip-chip interconnect test assembly in an embodiment of this application is shown;

[0043] Figure 5 A schematic diagram of the structure of another flip-chip interconnect test assembly in an embodiment of this application is shown;

[0044] Figure 6 A schematic diagram of the structure of another flip-chip interconnect test assembly in an embodiment of this application is shown;

[0045] Figure 7 It was made public. Figure 6 The simulated spacing between indium pillars in the flip-chip interconnect test assembly and the structural diagrams for short-circuit and non-short-circuit conditions during the flip-chip interconnect process are shown.

[0046] Icons: 200 - Wafer substrate; 201 - Indium pillar; 301 - Bottom substrate; 302 - Top substrate; 303 - Interconnect unit; 304 - Measurement line; 305 - Type 1 unit; 306 - Type 2 unit. Detailed Implementation

[0047] The inventors believe that in the development of quantum chips, when using flip-chip interconnect technology such as flip-chip bonding to fabricate quantum chips, the arrangement of the bonding metal (which can be indium pillars or indium balls; furthermore, it can be combined with titanium nitride as a transition connection structure to facilitate connection with aluminum in superconducting quantum chips) needs to be carefully considered so as to reserve more space for the layout of various components and circuits in the quantum chip while meeting the chip design performance requirements.

[0048] In other words, when a more flexible or larger-scale layout of circuits and devices in a flip-chip is desired, a denser arrangement of the bonding metal can be attempted. However, the rationality of the design scheme for the dense arrangement of the bonding metal, and whether and how this dense arrangement will affect the performance of the quantum chip, are all issues that require careful consideration. Furthermore, when multiple dense arrangement schemes for the bonding metal are designed, it is necessary to choose the optimal scheme. For example, which scheme results in a more compact arrangement—occupying less space?

[0049] Therefore, if the spacing between the soldered metals on the chip surface can be calibrated or tested to confirm or verify whether the dense arrangement scheme of the design is qualified or which scheme is better among multiple schemes, it will be of great benefit to the fabrication of quantum chips.

[0050] In the example of this application, the inventor proposes that an important indicator for judging whether the arrangement of the solder metal is qualified is that the solder metal in the quantum chip or quantum device that has completed flip-chip interconnection does not short-circuit.

[0051] Since densely packed sets of weld metal are typically arranged in an array, i.e., distributed across multiple rows and columns, and the distance between weld metals within the same row is relatively large, determining whether weld metals are short-circuited primarily involves examining whether there is a short circuit between weld metals in different rows (more specifically, adjacent rows). It should be noted that the distance between weld metals can be the spacing between weld metals in different rows, measured in the column direction; or in other examples, the distance between weld metals can also be the spacing between weld metals in different rows, measured in the row direction. This will be described in detail later with reference to the accompanying figures.

[0052] The criterion for determining whether a short circuit occurs is based on the fact that during flip welding, the weld metal softens and deforms and spreads outwards during the pressure welding process. Therefore, if the spacing between the weld metals is not well designed, the weld metals may come into contact with each other and cause a short circuit.

[0053] Furthermore, considering the actual manufacturing process—flip-chip interconnect devices or equipment often require a combination of multiple processes, such as photolithography, lift-off, etc.—flip-chip interconnect technology typically involves fabricating upper and lower chips separately (each layer optionally including solder metal and / or necessary circuitry, components, etc.), and then connecting them through alignment, bonding, and other operations to form a flip-chip interconnect. Therefore, in addition to ensuring that the solder metal in the fabricated flip-chip interconnect is not short-circuited, in some examples, as a more comprehensive consideration, one can also consider whether the arrangement of the solder metal will adversely affect the fabrication of the upper and lower chips. Alternatively, in addition to ensuring that the solder metal in the fabricated flip-chip interconnect does not short-circuit, one can also consider the arrangement of the solder metal so that although the fabrication of the upper and lower chips may be more difficult due to the dense arrangement of the solder metal, the increased space utilization resulting from the non-short-circuited and densely arranged solder metal in the subsequently fabricated flip-chip interconnect outweighs the loss of increased difficulty in fabricating the upper and lower chips after weighing all factors.

[0054] In short, in some cases, when considering a densely packed solder metal arrangement, the solder metals in the fabricated flip-chip interconnect should not be short-circuited. Alternatively, in other cases, when designing a densely packed solder metal arrangement, it is important to consider that the initial fabrication of independent upper and lower layer chips will not be significantly more difficult due to the dense arrangement of solder metals, while also ensuring that the solder metals in the subsequently fabricated flip-chip interconnect are not short-circuited with each other.

[0055] Based on the foregoing, the inventors propose a testing method in this application example. This method is used to verify the dense arrangement scheme of the bonding metals in flip-chip interconnects during the fabrication process. One achievement is finding a reasonable spacing between the bonding metals, i.e., extracting the required process parameters. It should be noted that the reasonable spacing for dense arrangement may not always be consistent or the same for bonding metals of different materials, structures, and shapes. Therefore, the reasonable spacing can be different under different aforementioned circumstances. However, the testing method in this application example can be applied to the testing and verification of dense arrangement schemes for bonding metals of different materials, structures, and shapes. In other words, for bonding metals of different materials, structures, and shapes, the testing method in this application example can measure and verify their dense arrangement spacing, thereby finding a scheme that meets the actual needs of flip-chip interconnects. It should be noted that when the parameters extracted through this application example are applied to the fabrication of flip-chip interconnects, it is recommended that the material, shape, and size of the bonding metals used in the actual fabrication process be consistent with the material, shape, and size of the bonding metals used in the implementation of the testing method.

[0056] In general, the inventors propose a method for extracting the spacing of densely packed solder metals in flip-chip interconnects. Whether the solder metals in a fabricated flip-chip are short-circuited or their distance from each other is influenced by multiple factors—such as the properties of the solder metals themselves, the planar area of ​​the solder metals, the height of the solder metals, and the alignment accuracy of the flip-chip bonding machine. The method described in this application simplifies and standardizes the process, thereby extracting the process parameters for manufacturing flip-chip interconnects that meet mass production requirements. That is, given a determination of the material, shape, or structure of the solder metals, the spacing of the solder metals can be obtained through the testing scheme described in this application, which can then guide actual production operations.

[0057] The following section details the testing methods used in this application example; please refer to it accordingly. Figures 1 to 7 .

[0058] This application provides an example, such as... Figure 1 and Figure 2 The test method shown can be used to determine the target spacing between discrete interconnect structures in a flip-chip interconnect assembly. The test method includes the following steps:

[0059] Step S101: Provide at least one flip-chip interconnect test component.

[0060] The number of flip-chip interconnect test assemblies is typically selected based on the arrangement of the solder metals to be tested / verified. When only one pitch needs to be tested, these densely packed solder metals can be placed in one flip-chip interconnect test assembly. When multiple pitches need to be tested, these densely packed solder metals can also be placed in one flip-chip interconnect test assembly. On the other hand, when multiple pitches need to be tested, these densely packed solder metals can be placed in different flip-chip interconnect test assemblies. Therefore, flip-chip interconnect test assemblies can be configured as needed, with at least two, and exemplary examples, two, three, four, or even more.

[0061] In general, this flip-chip interconnect assembly is a flip-chip interconnect chip that has been connected using flip-chip interconnect technology. The flip-chip interconnect test assembly in the example is made by flip-chip bonding of flip-chip cells. Generally, a flip-chip interconnect assembly includes two flip-chip cells (in some examples, this can be described as an upper chip / flip chip and a lower chip / base chip), and each flip-chip cell includes a substrate and various optionally configured suitable lines and components on the substrate. In the example, each flip-chip cell in a flip-chip interconnect assembly includes at least solder metal, and measurement lines are configured in one or both flip-chip cells (the following figures show that one of the flip-chip cells in a flip-chip interconnect assembly—the base chip or lower chip—is configured with measurement lines).

[0062] Based on the above description, each flip-chip interconnect test assembly has a test unit, and the test unit includes interconnect units and measurement lines, wherein the interconnect units are composed of soldered metal connections between upper and lower layers. Depending on whether a short circuit is detected, each flip-chip interconnect test assembly includes at least two test units.

[0063] It is worth noting that the spacing of a weld metal arrangement can be represented by two adjacent interconnecting units of any two adjacent test units. However, in order to improve the accuracy of the test, such as to avoid the randomness of the results that may be caused by missing weld metal, multiple test units (each test unit can have multiple weld metals) can be set for a weld metal arrangement spacing, so that multiple short-circuit tests can be performed on any two adjacent test units each time.

[0064] When multiple arrangement spacings need to be tested separately, the same or different number of measurements can be configured for each arrangement spacing. One measurement represents the measurement performed between two adjacent test units of the corresponding arrangement spacing.

[0065] As described above, the solder metal in the flip-chip unit constituting the flip-chip interconnect test assembly has a first arrangement pattern, and this first arrangement pattern can provide the spacing of the solder metal. That is, the first arrangement pattern can characterize at least one simulated spacing of the interconnect units in the flip-chip interconnect test assembly, and the simulated spacing is defined by the interconnect units corresponding to two adjacent measurement lines. It is understood that the interconnect structure is formed by the flip-chip interconnect operation of the solder metal in the interconnect unit. Therefore, although the simulated spacing of the interconnect unit corresponds to the spacing of the solder metal in the flip-chip unit, this does not usually mean that the two are equal. Because in the flip-chip unit, the solder metal has not undergone the flip-chip interconnect operation of pressure bonding, it does not diffuse or deform; however, after pressure bonding to form the interconnect unit, the solder metal will diffuse and deform, resulting in the interconnect unit having a simulated spacing that is smaller than the spacing of the solder metal. Therefore, the phrase "the first arrangement pattern characterizes at least one simulated spacing of the interconnect cells" described in the text can be understood as follows: given that the material, shape, and structural dimensions of the solder metal are determined, and it is fabricated and formed in a flip-chip unit, then based on a defined flip-chip interconnect process, the simulated spacing of the interconnect cells in the fabricated flip-chip interconnect test assembly is also typically determined. Thus, by providing a first arrangement pattern through the flip-chip unit, it can correspond to the simulated spacing of the interconnect cells in the flip-chip interconnect test assembly.

[0066] Furthermore, for the same type of weld metal (material, shape, structure, etc.), when weld metals with the same spacing are flip-chip welded together using the same process (welding temperature, pressure, etc.), the arrangement of interconnect units composed of upper and lower layers of weld metal in the flip-chip interconnect test assembly is the same, and the way they are short-circuited is also consistent.

[0067] Therefore, depending on the spacing of the solder metal in the flip-chip, the number of simulated spacing types of interconnect cells characterized by the first arrangement pattern in the flip-chip interconnect test assembly can be one, two, three, or even more.

[0068] Step S102: Perform measurements using a flip-chip interconnect test assembly and obtain the spacing value as the target spacing from the measurement results.

[0069] Depending on the number of test cells in the flip-chip interconnect test assembly, different numbers of measurement operations are performed to complete the measurement of all test cells. The required spacing can then be obtained from the measurement results, which can be used as the process parameters extracted by the test method in this application example for the actual fabrication of quantum chips.

[0070] The measurement operation includes checking whether the measurement lines of two adjacent test units are short-circuited. Therefore, when there are multiple test units, such as at least three, and the number of types of simulated spacing they represent is at least two, multiple measurements can be performed. Alternatively, when there are multiple test units, such as at least three, and the number of types of simulated spacing they represent is one, multiple measurements can also be performed—this avoids measurement errors or inaccuracies.

[0071] As we know, each measurement operation yields two results: short circuit and no short circuit. Based on the aforementioned requirements, we need the simulated spacing corresponding to the no-short circuit condition. Therefore, for the same simulated spacing, we can perform a single measurement or multiple measurements to better confirm that a short circuit has indeed not occurred at that spacing. For different simulated spacings, if two or more no-short circuit conditions are found in the measurement results corresponding to these spacings, it indicates that these simulated spacings meet the basic requirements. Then, to better utilize chip space, we can select the spacing value with the smallest simulated spacing as the target spacing—that is, the extracted process parameter.

[0072] In short, such as Figure 1 As shown, based on the obtained flip-chip interconnect test assembly, measurement operations are performed on all test units, and based on the measurement operation with or without measurement results, a simulated spacing that satisfies the first preset condition is obtained from at least one simulated spacing as the target spacing.

[0073] If none of the test results based on the measurement operations of all test units show a negative result—that is, no non-short circuit case—then it is necessary to consider modifying the first layout pattern to provide at least one simulated spacing with adjusted simulated spacing values, for example... Figure 2 In the process, there is a branch that determines whether the result of the measurement operation is short-circuited and the conclusion is no.

[0074] In other instances, adjustments to the material, shape, and structural dimensions of the solder metal can be considered. This involves fabricating a new flip-chip interconnect test assembly and conducting tests. However, it should be noted that the material, shape, and structural dimensions of the solder metal are usually pre-selected or already determined. In such cases, adjusting the spacing of the solder metal in the flip-chip unit is the preferred option. In other words, if all measurement results are negative, the flip-chip interconnect test assembly needs to be modified or re-fabricated.

[0075] Please refer to it again. Figure 2 If, after all measurement operations are completed, there is only one measurement operation with a negative result, then the target spacing is the simulated spacing corresponding to the measurement with a negative result. Alternatively, if, after all measurement operations are completed, there are multiple measurement operations with negative results, and the simulated spacing corresponding to each measurement operation is the same, then the target spacing is the simulated spacing corresponding to the measurement with a negative result.

[0076] Please refer to it again. Figure 2 When the number of measurement operations with a negative result is at least two or more, the target spacing is the minimum value among the simulated spacings corresponding to negative or positive measurement results. For example, when the number of measurement operations with a negative result is at least two, and the simulated spacing corresponding to each measurement operation is different or partially the same, the target spacing is the minimum value among all the simulated spacings corresponding to negative or positive measurement results.

[0077] Optionally, in other embodiments of this application, the testing method may further include obtaining the distribution parameters of the solder metal used to fabricate the flip-chip interconnect test assembly. For example, determining a second arrangement pattern of interconnect units that satisfies a second preset condition.

[0078] The second layout pattern can represent at least one pre-screening spacing, and each spacing value in the at least one pre-screening spacing corresponds one-to-one with each spacing value in the at least one simulated spacing. That is, the number of types of pre-screening spacings for the weld metal in the second layout pattern (with the same value representing one type) can be the same as the number of types of simulated spacings (with the same value representing one type), or the number of pre-screening spacings can be greater than the number of simulated spacings. Because some of the pre-screening spacings may not meet the requirements, flip-chip interconnect test components with simulated weld metal spacing cannot be fabricated based on these pre-screening spacings.

[0079] Accordingly, the "requirement" mentioned above, where "a portion of the pre-screening spacing may not meet the requirements," refers to, for example, a stripping process in fabricating a second arrangement of interconnect units that takes less time than a preset reference time. This is because, for a wafer or substrate of a given size, when the solder metal (such as indium pillars) is sparsely distributed, the stripping time for the solder metal after photolithography will be relatively longer. Conversely, if the solder metal is densely packed, the stripping time will be shorter. Each solder metal provides a stripping edge; therefore, each additional edge increases the speed of the stripping process; that is, more indium pillars provide more edges, resulting in faster stripping. Thus, increasing the amount of solder metal increases the stripping speed, but the spacing between solder metals of the same structural size on the same wafer will decrease.

[0080] Furthermore, the presence of residual photoresist after the stripping process can affect subsequent processes. Therefore, in some examples, if the stripping time meets the requirements, it is advisable to "observe" to determine if there is no residual photoresist. Even further, although residual photoresist may occur during the stripping process, it is acceptable in some cases if it can be removed without residue after photoresist washing. That is, if the stripping time is sufficiently good, even with residual photoresist, if it can be easily removed, the aforementioned second-row pattern is a feasible solution.

[0081] Furthermore, since the fabrication of flip-chip interconnect test assemblies involves aligning and pressing the flip-chip units, any deformation of the interconnect units in the completed test assembly could cause problems when the parameters extracted in this way are used to fabricate flip-chips. Therefore, the example test method could also include examining whether the interconnect units in the test unit have deviated from a predetermined shape. For example, assuming the solder metal in the flip-chip unit is upright (e.g., perpendicular to the substrate surface), if the solder metal tilts during pressing, it could also cause short circuits or other problems. Therefore, in some cases, in addition to checking whether the test result indicates no short circuit, it is advisable to also examine whether the solder metal has undergone undesirable deformation.

[0082] Based on the above, the test scheme of this application example can be briefly summarized as including the following two methods.

[0083] First scenario: Test the obtained flip-chip interconnect test component, and then obtain the simulated spacing that meets the requirements from the test results as the target spacing.

[0084] Second scenario: Perform pre-screening to obtain flip-chip interconnect test components corresponding to the pre-screening results, test them, and then obtain the simulated spacing that meets the requirements from the test results as the target spacing.

[0085] The second case mentioned above can be described as planar screening and flip-chip screening.

[0086] The planar screening process is illustrated by the following description:

[0087] Generally, the solder metal for flip-chip bonding is spherical, cylindrical, or prismatic. Spherical structures allow for better outward diffusion during bonding, and deformation is easier to control; cylindrical structures are better suited for creating larger chip pitches. As an extreme case, a cuboid structure with a cylindrical surface circumscribed by a square (e.g., a square prism). In this case, the solder metal expands outwards more significantly during bonding, potentially causing short circuits. Furthermore, square structures are less conducive to processes like heat coating compared to circular structures.

[0088] This allows for the fabrication of planar chips, comprising a silicon substrate and cylindrical indium pillars or indium pillars with a square cross-section arranged in an array on the substrate. See also... Figure 3 It provides a set of 18 indium pillar units arranged in three rows and six columns on a wafer substrate 200. These indium pillar units are all concentrated on a silicon substrate, and in other examples they can also be arranged one-to-one on a silicon substrate; or some of them are located on one substrate and the rest are located on another substrate.

[0089] Figure 3 This example illustrates 18 indium pillar arrangement units located on the same silicon substrate, with each indium pillar arrangement unit comprising 25 indium pillars 201. Each indium pillar arrangement unit can form or represent a previously described second arrangement pattern, and the same indium pillar arrangement unit comprises 25 indium pillars of the same structure, material, and size in five rows and five columns. It is worth noting that, since the indium pillars in the same row typically have a relatively larger spacing, in some examples the target spacing can be expressed as the spacing between indium pillars at corresponding positions in adjacent rows—for example, the spacing between the indium pillars in the first row and first column of an indium pillar arrangement unit and the indium pillars in the first row and first column of a second indium pillar arrangement unit. Figure 3 The label indicates the spacing D along the column direction between the indium pillars in the first row, sixth column and the indium pillars in the second row, fifth column, within the indium pillar arrangement set. A flip-chip interconnect assembly fabricated based on this spacing D is provided by an exemplary [example / example / details]. Figure 4 public. Figure 4 The document reveals a bottom substrate 301, a top substrate 302, a measurement line 304, and an interconnect unit 303 located between the bottom and top layers.

[0090] In other instances, the spacing between the indium pillars can also be the spacing D along the row direction of the corresponding indium pillars in adjacent measurement units, which is... Figure 5 It was made public in the text and was mentioned and detailed again later.

[0091] The above example uses a square-section indium prism. When the indium prism has a circular cross-section, it can be expressed as the distance between the centers of the two indium prisms, or the distance between the lines connecting their centers and subtracting their radii. (See reference...) Figure 6 and Figure 7 .

[0092] Each of the aforementioned indium pillar arrays can be individually fabricated onto the surface of a wafer substrate using a lift-off process to form a pre-screened chip. During the fabrication of the pre-screened chip, particular attention is paid to the spin coating and adhesive washing processes. By inspecting the condition of the solder pillars / indium pillars fabricated in the pre-screened chip (e.g., whether they are deformed, have a large tilt angle, or have residual adhesive), unsuitable parameter combinations are eliminated, thus initially obtaining the dimensional configuration of the flip-chip bonding metal packing. Then, based on the pre-screened chip, the material, shape, and structural dimensions of the indium pillars are obtained to fabricate flip-chip interconnect test components. Alternatively, as described above and in reference... Figure 6 In a flip-chip interconnect test assembly that combines non-interconnect units and interconnect units, residual adhesive, washing adhesive, and peeling time in the non-interconnect unit area can be considered separately. At the same time, short circuit tests can be performed on the area where the interconnect units are located, which will be explained later.

[0093] The flip-chip screening process is explained by the following description:

[0094] Based on the close-packing arrangement of the solder metal obtained through the planar screening process, when no measurement lines are fabricated in the aforementioned pre-screened chip, measurement lines can be fabricated on the wafer surface. Following the close-packing arrangement of the solder metal obtained through the planar screening process, the solder metal is fabricated onto the wafer surface and connected to the measurement lines. Then, flip-chip interconnection is performed to form a flip-chip interconnection test assembly. It is understood that when measurement lines have already been fabricated in the aforementioned pre-screened chip, flip-chip interconnection can be directly performed to form a flip-chip interconnection test assembly. As an example, the structure of the flip-chip interconnection test assembly can be found in [reference needed]. Figure 4It includes a bottom substrate 301, a top substrate 302, interconnect units 303, and measurement lines 304. The interconnect units have a simulated pitch and include three measurement lines 304. For this simulated pitch, two measurement operations can be performed using any two adjacent measurement lines 304. The measurement lines 304 can be configured on the bottom substrate 304 to facilitate the placement of pads for contact with the connectors or contacts of the measurement instrument; in other examples, the bottom and top substrates can each have measurement lines configured, and pads can be brought out via through-silicon vias (TSVs) for use as contacts for the measurement instrument.

[0095] To facilitate and simplify the measurement process, the structure of the flip-chip interconnect test component can be adjusted to allow the aforementioned planar screening and flip-chip screening to be performed simultaneously. For example, considering that in some flip-chip interconnects, the size of the bottom substrate 301 of the bottom chip can be larger than the size of the top substrate 302 of the top chip, the bottom substrate 301 has an area covered by the top substrate 302, such as... Figure 6 The I region and the areas not covered by the top substrate 302, such as Figure 6 The X area in the middle.

[0096] In region I, the indium pillars are bonded together, which can lead to diffusion and tilting, potentially causing short circuits. Therefore, this region can be used for flip-chip bonding screening. Conversely, the indium pillars in region X are not bonded together, making them suitable for planar screening. Based on... Figure 6 In the arrangement shown, the spacing between the indium pillars and the short-circuit and non-short-circuit conditions during the bonding process in the area where the upper and lower chips overlap (region I) are determined by... Figure 7 It has been made public.

[0097] The test method of this application example has been fully explained above. The test structure will be discussed below.

[0098] The test structure provided in this application example can be provided and used by the aforementioned flip-chip interconnect test assembly. The test structure has a first test chip and a first chip (with a bottom substrate 301) and a second chip (with a top substrate 302) configured for flip-chip interconnection. The first chip has at least two test units, and each test unit includes a first interconnect unit (e.g., an indium pillar) connected to a measurement line. One or more first interconnect units connected to one of the measurement lines may be present, see [reference]. Figure 4 A measurement line connects five first interconnect units, see reference. Figure 5 A measurement line connects six first interconnect units, see reference. Figure 6A measurement line connects 12 first interconnect units (six of which are located in the covered area for flip-chip screening to determine whether there is a short circuit; the other six are located in the uncovered area for planar screening such as peeling time, presence of residual adhesive, and whether the residual adhesive can be washed off).

[0099] The second chip has a second interconnect unit (e.g., an indium pillar). In the first test chip, the first and second interconnect units are matched and connected in a one-to-one correspondence to form an interconnect structure. These interconnect structures together constitute an arrangement pattern that can be identified or referred to as corresponding to at least one pitch.

[0100] As mentioned earlier, when verifying schemes with multiple pitches, various arrangements can be configured in a single first test chip, or they can be configured separately in different first test chips. Furthermore, for testing convenience, interconnect structures corresponding to the same pitch can be configured in the same test chip, while interconnect structures defining different pitches can be configured in different test chips. As an alternative, indium pillars corresponding to different arrangement pitches can be distributed in a single first test chip.

[0101] Furthermore, as described above, the material, structural dimensions, and length of the indium pillars can all lead to varying degrees of diffusion during pressure bonding. Therefore, indium pillars of different sizes can be used to configure the same simulated pitch. For example, assuming a simulated pitch of 5 micrometers, it can be formed by arranging square indium pillars with a cross-sectional area of ​​10 micrometers on each side, or by arranging square indium pillars with a cross-sectional area of ​​12 micrometers on each side, or by arranging circular indium pillars with a cross-sectional area of ​​10 micrometers in diameter, and so on.

[0102] For example, corresponding to the two types of indium pillars, the indium pillars can be divided into a first type of unit and a second type of unit, and the shape and size of the first type of unit and the second type of unit are different. Further, based on this, the number of measurement lines can be less than three or more, and they are arranged side-by-side sequentially. The two outermost measurement lines connect to either the first type of unit or the second type of unit, and the remaining measurement lines between the two outermost measurement lines connect to both the first type of unit and the second type of unit. Furthermore, any two adjacent measurement lines are between either a first type of unit with an intersecting finger-like distribution or a second type of unit with an intersecting finger-like distribution.

[0103] Please see Figure 5 A first test chip with three measurement lines 304 is disclosed (the upper layer chip, i.e., the second chip, is not shown).

[0104] Among them, the two outer measuring lines 304 are respectively connected to square indium pillars of different shapes—either type 305 or type 306. Simultaneously, a measuring line between the two measuring lines 304 connects both type 305 and type 306. It should be noted that... Figure 5 In this design, the first type unit 305 and the second type unit 306 are not directly connected to the measuring line 304, but are connected via wires. That is, the first type unit 305 is not directly crimped onto the measuring line 304, and the second type unit 306 is not directly crimped onto the measuring line 304. A solution for directly crimping the measuring line 304 can be found in [reference needed]. Figure 4 , Figure 6 .

[0105] In this scheme, when testing the first and second measurement lines from top to bottom in the direction shown in the diagram, the presence or absence of a short circuit can determine whether the first spacing of the first type unit 305 is qualified; when testing the second and third measurement lines from top to bottom in the direction shown in the diagram, the presence or absence of a short circuit can determine whether the second spacing of the second type unit 306 is qualified. The first and second spacings can be the same or two different types.

[0106] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A test method for determining a target spacing between discrete interconnect structures in a flip-chip interconnect assembly, characterized in that, The testing method includes: At least one flip-chip interconnect test assembly is provided, the flip-chip interconnect test assembly being fabricated from flip-chip units via flip-chip interconnection, each flip-chip interconnect test assembly having at least two test units, each test unit including an interconnect unit and a measurement line, the measurement line being provided by the flip-chip unit, the interconnect unit being connected to the measurement line, the flip-chip unit providing a first layout pattern, and the first layout pattern representing at least one simulated spacing of the interconnect units, the simulated spacing being defined by the interconnect units corresponding to two adjacent measurement lines respectively; Measurement operations are performed on all test units, and based on the measurement operation with a negative result, a simulated spacing that satisfies a first preset condition is obtained from the at least one simulated spacing as the target spacing; wherein, the measurement operation includes measuring whether the measurement lines of two adjacent test units are short-circuited; The first arrangement pattern represents at least two types of simulated spacings among at least one simulated spacing of the interconnecting units; The first preset condition includes: when the number of measurement operations with a negative result is one, the target spacing is the simulated spacing corresponding to the measurement with a negative result; Alternatively, the first preset condition includes: when the number of measurement operations with a negative result is multiple, the target spacing is the minimum value among the simulated spacings corresponding to the negative measurement results.

2. The test method according to claim 1, characterized in that, When there is no negative test result among the test results corresponding to the measurement operations of all test units, the first layout pattern is changed to provide the at least one simulated spacing with the simulated spacing value adjusted.

3. The test method according to claim 1, characterized in that, Each of the test units also includes a non-interconnect unit fabricated by a stripping process, and the test method further includes: determining that there is no residual adhesive in the area where the non-interconnect unit of the flip-chip interconnect test assembly is located.

4. The test method according to claim 1, characterized in that, The testing method further includes: before providing at least one flip-chip interconnect test component, determining a second arrangement pattern composed of interconnect units that meets a second preset condition, and the second arrangement pattern represents at least one pre-screening spacing, wherein the value of each spacing in the at least one pre-screening spacing corresponds one-to-one with the value of each spacing in the at least one simulated spacing. The second preset condition includes: the peeling process in the manufacturing process of the second arrangement pattern composed of interconnecting units takes less than a preset reference time, and there is no adhesive residue after peeling. Alternatively, the second preset condition includes: during the process of making the second arrangement pattern composed of interconnecting units, there is residual adhesive after the peeling process, and the residual adhesive is removed without residue after washing. Alternatively, the second preset condition includes: detecting that the interconnecting unit does not have any deformation that deviates from the preset shape.

5. A test structure for implementing the test method according to any one of claims 1 to 4, said test structure being provided by the flip-chip interconnect test assembly, characterized in that, The test structure includes: The first test chip has a first chip and a second chip configured with flip-chip interconnect; At least two test units are configured on the first chip, each test unit including a first interconnect unit connected to a measurement line; The second interconnect unit is configured in the second chip; The first interconnect unit and the second interconnect unit are matched and connected one-to-one to form an interconnect structure, and all interconnect structures are defined with an arrangement pattern having at least one spacing.

6. The test structure according to claim 5, characterized in that, The number of the first test chips is one; Alternatively, when the number of spacings in the at least one spacing is at least two, the number of the first test chips is the same as the number of spacing types in the at least one spacing, and interconnect structures with the same spacing are configured on the same test chip, while interconnect structures with different spacings are configured on different test chips.

7. The test structure according to claim 5, characterized in that, The cross-sectional shape of each of the first interconnect units is a circle with the same diameter; Alternatively, the cross-sectional shape of each of the first interconnect units is a square with the same side length.

8. The test structure according to claim 5, characterized in that, All the first interconnect units include first type units and second type units, and the shape and size of the first type units are different from those of the second type units.

9. The test structure according to claim 8, characterized in that, The number of the measuring lines is at least three, and they are arranged side by side in sequence. The two outermost measurement lines connect to either the first type unit or the second type unit. The remaining measurement lines between the two outermost measurement lines are connected to both the first type unit and the second type unit. Furthermore, any two adjacent measurement lines are either first type units or second type units that are interdigitated.

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