A universal IO interface circuit

Abstract

The application discloses a general IO interface circuit, which comprises a sending level conversion circuit and a receiving level conversion circuit, the sending level conversion circuit and the receiving level conversion circuit are connected, the sending level conversion circuit comprises a first voltage dividing circuit and a MOS tube group, the first voltage dividing circuit and the MOS tube group are connected, the receiving level conversion circuit comprises a second voltage dividing circuit and an inverter, and the second voltage dividing circuit and the inverter are connected, wherein the 1.8V device is used to realize the 5V voltage resistance function, a constant voltage is not needed to be provided by means of a reference voltage source, the chip development area and the chip packaging cost are reduced, and the internal chip uses the 1.8V device; when the 5V voltage is connected externally, the voltage borne by the three NMOS tubes is divided by the voltage dividing technology, one NMOS tube bears the voltage of about 1.7V on average, and the voltage safety is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of IO interface, and more particularly, relates to a general IO interface circuit. BACKGROUND

[0002] The general IO interface is an IO module commonly used for analog and digital signal transmission and has the functions of receiving and sending. The general IO interface can transmit internal control signals or data of a chip to other chips and can also receive data sent by external chips, so as to realize data transmission or control functions. The existing general IO interface has the following defects:

[0003] First, the internal chip analog voltage is 3.3V, the external voltage of the IO interface is 3.3V, and a separate LDO needs to be used to provide a 1.8V / 2.5V / 3.3V reference voltage. Such a circuit makes the design complex and has a large area overhead. Second, the analog voltage is 3.3V, and the PAD end voltage is 3.3V. The PAD cannot be pulled up to 5V. If a 5V control voltage is to be provided, an MOSFET tube needs to be added outside the chip, which increases the use cost. SUMMARY

[0004] The application aims to provide a general IO interface circuit to solve the technical problems of complex design and large area overhead of the IO interface circuit in the prior art.

[0005] To achieve the above technical purposes, the technical scheme adopted by the application is as follows:

[0006] A general IO interface circuit comprises a sending level conversion circuit and a receiving level conversion circuit, the sending level conversion circuit and the receiving level conversion circuit are connected, the sending level conversion circuit comprises a first voltage dividing circuit and an MOS tube group, the first voltage dividing circuit and the MOS tube group are connected, the receiving level conversion circuit comprises a second voltage dividing circuit and an inverter, and the second voltage dividing circuit and the inverter are connected.

[0007] Preferably, the first voltage dividing circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor, the first resistor is connected with the second resistor and the third resistor respectively, the fourth resistor is connected with the MOS tube group, and the fifth resistor is connected with the MOS tube group.

[0008] Preferably, the MOS tube group comprises a first NMOS tube, a second NMOS tube and a third NMOS tube, the drain of the first NMOS tube is connected with the source of the second NMOS tube, the drain of the second NMOS tube is connected with the source of the third NMOS tube, and the drain of the third NMOS tube is connected with the first voltage dividing circuit.

[0009] Preferably, the MOS tube group comprises a fourth NMOS tube, and the fourth NMOS tube is connected with the first voltage dividing circuit.

[0010] Preferably, the sending level conversion circuit comprises a capacitor, one end of the capacitor is connected with the MOS tube group, and the other end of the capacitor is grounded.

[0011] Preferably, the second voltage dividing circuit comprises a sixth resistor, a seventh resistor and an eighth resistor, the seventh resistor is connected with the sixth resistor and the eighth resistor respectively, and the inverter is connected with the seventh resistor and the eighth resistor respectively.

[0012] Preferably, the inverter comprises a fifth NMOS tube, a first PMOS tube and a second PMOS tube, the second PMOS tube is connected with the fifth NMOS tube and the first PMOS tube respectively.

[0013] Preferably, the sending level conversion circuit further comprises an internal input end, and the internal input end is connected with the MOS tube group.

[0014] Preferably, the receiving level conversion circuit further comprises a flip-flop, and an input end of the flip-flop is connected with the inverter.

[0015] Preferably, the sending level conversion circuit and the receiving level conversion circuit both comprise a PAD end, the PAD end is connected with the first voltage dividing circuit and the second voltage dividing circuit respectively, and the sending level conversion circuit and the receiving level conversion circuit are connected through the PAD end.

[0016] The application has the advantages that:

[0017] 1. The application comprises a sending level conversion circuit and a receiving level conversion circuit, and the sending level conversion circuit and the receiving level conversion circuit are connected.

[0018] 2. The sending level conversion circuit of the application comprises a first voltage dividing circuit and a MOS tube group, the first voltage dividing circuit and the MOS tube group are connected, the receiving level conversion circuit comprises a second voltage dividing circuit and an inverter, and the second voltage dividing circuit and the inverter are connected. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0020] Figure 1 is a structural schematic diagram of a transmitting level conversion circuit;

[0021] Figure 2 is a structural schematic diagram of a receiving level conversion circuit. DETAILED DESCRIPTION

[0022] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0024] Embodiment 1:

[0025] The present embodiment is applicable to signal transmission, and includes a general IO interface circuit, which includes a transmitting level conversion circuit and a receiving level conversion circuit. The transmitting level conversion circuit and the receiving level conversion circuit are connected. The transmitting level conversion circuit includes a first voltage dividing circuit and a MOS tube group, and the first voltage dividing circuit and the MOS tube group are connected. The receiving level conversion circuit includes a second voltage dividing circuit and an inverter, and the second voltage dividing circuit and the inverter are connected.

[0026] As shown in Figure 1 , the transmitting level conversion circuit and the receiving level conversion circuit both include a PAD end, and the PAD end is connected with the first voltage dividing circuit and the second voltage dividing circuit respectively. The transmitting level conversion circuit and the receiving level conversion circuit are connected through the PAD end. The transmitting level conversion circuit further includes an internal input end, and the internal input end is connected with the MOS tube group. The transmitting level conversion circuit includes a capacitor C1, one end of the capacitor C1 is connected with the MOS tube group, and the other end of the capacitor C1 is grounded.

[0027] The first voltage dividing circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, the first resistor R1 is connected with the second resistor R2 and the third resistor R3 respectively, the fourth resistor R4 is connected with the MOS tube group, and the fifth resistor R5 is connected with the MOS tube group.

[0028] The MOS tube group comprises a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3, the drain of the first NMOS tube is connected with the source of the second NMOS tube, the drain of the second NMOS tube is connected with the source of the third NMOS tube, and the drain of the third NMOS tube is connected with the first voltage dividing circuit. The MOS tube group comprises a fourth NMOS tube N4, and the fourth NMOS tube N4 is connected with the first voltage dividing circuit.

[0029] The internal input end is connected with the gate of the first NMOS tube, the bulk end of the second NMOS tube and the capacitor respectively. The source of the first NMOS tube is connected with the bulk end of the first NMOS tube, and the drain of the first NMOS tube is connected with the source of the second NMOS tube. The gate of the second NMOS tube is connected with the fourth resistor R4 and the bulk end of the third NMOS tube respectively, and the drain of the second NMOS tube is connected with the source of the third NMOS tube. The gate of the third NMOS tube is connected with the source of the fourth NMOS tube and the first resistor R1 respectively, and the drain of the third NMOS tube is connected with the third resistor R3. The gate of the fourth NMOS tube is connected with the fifth resistor R5, the source of the fourth NMOS tube is connected with the first resistor R1 and the gate of the third NMOS tube respectively, and the bulk end of the fourth NMOS tube is connected with the drain of the fourth NMOS tube.

[0030] The PAD end is connected with the first resistor R1 and the third resistor R3 respectively, the first resistor R1 is connected with the second resistor R2 and the PAD end respectively, the second resistor R2 is connected with the capacitor and the first resistor R1 respectively, the third resistor R3 is connected with the PAD end and the drain of the third NMOS tube respectively, the fourth resistor R4 is connected with the gate of the second NMOS tube, and the fifth resistor R5 is connected with the gate of the fourth NMOS tube and the drain of the fourth NMOS tube respectively.

[0031] When the signal is sent, the chip internal data is transmitted to the internal data receiving end, and the chip internal data is output through the PAD end after being divided by the transmission level conversion circuit.

[0032] The internal data receiving end is connected to the gate of the first NMOS transistor. When the internal data receiving end is at a high potential of 1.8V, the first NMOS transistor is turned on, and the drain of the first NMOS transistor is at a low potential of 0V. The gate of the second NMOS transistor is at a high potential of 1.8V, the second NMOS transistor is turned on, and the drain of the second NMOS transistor is at a low potential of 0V. At this time, the gate of the third NMOS transistor is at a high potential, the third NMOS transistor is turned on, and the PAD end is pulled to a low potential.

[0033] When the internal data receiving end is at a low potential of 0V, the first NMOS transistor is not turned on. The drain N1d of the first NMOS transistor is at a high potential, and the gate N2g of the second NMOS transistor is at a high potential of 1.8V, so the second NMOS transistor is not turned on, and the drain of the second NMOS transistor is at a high potential. At this time, the gate N3g of the third NMOS transistor is at a high potential, the third NMOS transistor is not turned on, and the PAD end is pulled up to 5V. Thus, the function of level shifting from 1.8V to 5V is realized. The 5V voltage resistance function is realized by using 1.8V devices, without the need to rely on a reference voltage source to provide a constant voltage, reducing chip development area and chip packaging cost, and can be applied to low-speed control signals such as HDMI.

[0034] If the internal data receiving end is at a high potential of 1.8V, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor all work in a safe region, and at this time, the voltage resistance problem of the tubes does not need to be considered. If the internal data receiving end is at a low potential of 0V, and the voltage of the PAD end is 5V, the voltage N1_Vds from the drain to the source of the first NMOS transistor, the voltage N2_Vds from the drain to the source of the second NMOS transistor, and the voltage N3_Vds from the drain to the source of the third NMOS transistor all have the risk of overvoltage.

[0035] The voltage N1_Vgs from the gate to the source of the first NMOS transistor, the voltage N2_Vgs from the gate to the source of the second NMOS transistor, and the voltage N3_Vgs from the gate to the source of the third NMOS transistor all have the risk of overvoltage. The voltage N1_Vbs from the bulk to the source of the first NMOS transistor, the voltage N1_Vbd from the bulk to the drain of the first NMOS transistor, the voltage N2_Vbs from the bulk to the source of the second NMOS transistor, the voltage N2_Vbd from the bulk to the drain of the second NMOS transistor, the voltage N3_Vbs from the bulk to the source of the third NMOS transistor, and the voltage N3_Vbd from the bulk to the drain of the third NMOS transistor all have the risk of overvoltage.

[0036] The voltage of the third NMOS tube gate is divided by the first resistor R1 and the second resistor R2, and the voltage N3g=3.6V is obtained. The voltage Vgd=-1.4V of the third NMOS tube gate to the drain, the voltage N3b=1.8V of the bulk end of the third NMOS tube, and the voltage Vdb=3.2V of the drain to the bulk end of the third NMOS tube. The voltage N2d=3.4V of the second NMOS tube drain, the voltage N3_Vds=1.6V of the third NMOS tube drain to the source, and the voltage N3_Vgs=0.2V of the third NMOS tube gate to the source. At this time, the third NMOS tube meets the voltage withstand requirement.

[0037] The voltage N2_Vgs=1.8V of the second NMOS tube gate to the source, the voltage N2_Vgd=-1.6V of the second NMOS tube gate to the drain, the voltage N2_Vds=1.6V of the second NMOS tube drain to the source, the voltage N2_Vbs=-1.7V of the bulk end to the source of the second NMOS tube, and the voltage N2_Vbd=-3.4V of the bulk end to the drain of the second NMOS tube. At this time, the second NMOS tube meets the voltage withstand requirement.

[0038] The voltage N1_Vgs=0 of the first NMOS tube gate to the source, the voltage N1_Vgd=-1.7V of the first NMOS tube gate to the drain, the voltage N1_Vds=1.7V of the first NMOS tube drain to the source, the voltage N1_Vbs=0 of the bulk end to the source of the first NMOS tube, and the voltage N1_Vbd=-1.7V of the bulk end to the drain of the first NMOS tube. At this time, the first NMOS tube meets the voltage withstand requirement.

[0039] The use of the resistor voltage division structure greatly simplifies the circuit structure, saves the circuit area, and at the same time, is applied in a low-speed circuit, does not need large driving, and saves power consumption. At the same time, it also does not need a MOSFET tube outside the chip to achieve 1.8V to 5V, thereby saving packaging cost and development cost.

[0040] Embodiment 2:

[0041] This embodiment is suitable for receiving signals, and includes a general IO interface circuit, which includes a sending level conversion circuit and a receiving level conversion circuit. The sending level conversion circuit and the receiving level conversion circuit are connected. The sending level conversion circuit includes a first voltage division circuit and a MOS tube group, and the first voltage division circuit and the MOS tube group are connected. The receiving level conversion circuit includes a second voltage division circuit and an inverter, and the second voltage division circuit and the inverter are connected.

[0042] As Figure 2As shown, the transmitting level conversion circuit and the receiving level conversion circuit each include a PAD terminal, the PAD terminal is connected with the first voltage dividing circuit and the second voltage dividing circuit respectively, and the transmitting level conversion circuit and the receiving level conversion circuit are connected through the PAD terminal. The receiving level conversion circuit further includes a flip-flop, and an input terminal of the flip-flop is connected with the inverter.

[0043] The second voltage dividing circuit includes a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8, the seventh resistor R7 is connected with the sixth resistor R6 and the eighth resistor R8 respectively, and the inverter is connected with the seventh resistor R7 and the eighth resistor R8 respectively. The inverter includes a fifth NMOS tube N5, a first PMOS tube P1 and a second PMOS tube P2, the second PMOS tube P2 is connected with the fifth NMOS tube N5 and the first PMOS tube P1 respectively.

[0044] The drain of the first PMOS tube is connected with the bulk terminal of the first PMOS tube, the source of the first PMOS tube is connected with the drain of the second PMOS tube, and the gate of the first PMOS tube is connected with the second voltage dividing circuit. The bulk terminal of the second PMOS tube is connected with the bulk terminal of the first PMOS tube, the source of the second PMOS tube is connected with the drain of the fifth NMOS tube, and the gate of the second PMOS tube is connected with the second voltage dividing circuit. The bulk terminal of the fifth NMOS tube is connected with the source of the fifth NMOS tube, the source of the fifth NMOS tube is connected with the second voltage dividing circuit, and the gate of the fifth NMOS tube is connected with the second voltage dividing circuit.

[0045] When receiving a signal, the external data of the chip is transmitted to the PAD terminal, and the external data of the chip is input into the chip interior through the MOS tube group after being divided by the receiving level conversion circuit. When receiving a signal, the potential of the PAD terminal is 5V, 1.8V is obtained through the voltage division of the seventh resistor R7 and the eighth resistor R8, and the signal of the input terminal of the flip-flop is obtained through the inverter composed of the fifth NMOS tube, the first PMOS tube and the second PMOS tube. The voltage of 5V is reduced to 1.8V through the voltage division of the seventh resistor R7 and the eighth resistor R8, so as to avoid the Vgs overvoltage of the fifth NMOS tube.

[0046] Embodiment 3

[0047] This embodiment is suitable for IO self-checking mode, for example, Figure 1 and Figure 2 As shown, a general IO interface circuit includes a transmitting level conversion circuit and a receiving level conversion circuit, the transmitting level conversion circuit and the receiving level conversion circuit are connected, the transmitting level conversion circuit includes a first voltage dividing circuit and a MOS tube group, the first voltage dividing circuit and the MOS tube group are connected, the receiving level conversion circuit includes a second voltage dividing circuit and an inverter, and the second voltage dividing circuit and the inverter are connected.

[0048] The transmitting level conversion circuit and the receiving level conversion circuit each include a PAD terminal, the PAD terminal is connected with the first voltage dividing circuit and the second voltage dividing circuit respectively, and the transmitting level conversion circuit and the receiving level conversion circuit are connected through the PAD terminal. The transmitting level conversion circuit further includes an internal input terminal, the internal input terminal is connected with the MOS tube group. The transmitting level conversion circuit includes a capacitor C1, one end of the capacitor C1 is connected with the MOS tube group, and the other end of the capacitor C1 is grounded.

[0049] The first voltage dividing circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, the first resistor R1 is connected with the second resistor R2 and the third resistor R3 respectively, the fourth resistor R4 is connected with the MOS tube group, and the fifth resistor R5 is connected with the MOS tube group.

[0050] The MOS tube group includes a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3, the drain of the first NMOS tube is connected with the source of the second NMOS tube, the drain of the second NMOS tube is connected with the source of the third NMOS tube, and the drain of the third NMOS tube is connected with the first voltage dividing circuit. The MOS tube group includes a fourth NMOS tube N4, the fourth NMOS tube N4 is connected with the first voltage dividing circuit.

[0051] The internal input terminal is connected with the gate of the first NMOS tube, the bulk terminal of the second NMOS tube and the capacitor respectively. The source of the first NMOS tube is connected with the bulk terminal of the first NMOS tube, and the drain of the first NMOS tube is connected with the source of the second NMOS tube. The gate of the second NMOS tube is connected with the fourth resistor R4 and the bulk terminal of the third NMOS tube respectively, and the drain of the second NMOS tube is connected with the source of the third NMOS tube. The gate of the third NMOS tube is connected with the source of the fourth NMOS tube and the first resistor R1 respectively, and the drain of the third NMOS tube is connected with the third resistor R3. The gate of the fourth NMOS tube is connected with the fifth resistor R5, the source of the fourth NMOS tube is connected with the first resistor R1 and the gate of the third NMOS tube respectively, and the bulk terminal of the fourth NMOS tube is connected with the drain of the fourth NMOS tube.

[0052] The PAD terminal is connected with the first resistor R1 and the third resistor R3 respectively, the first resistor R1 is connected with the second resistor R2 and the PAD terminal respectively, the second resistor R2 is connected with the capacitor and the first resistor R1 respectively, the third resistor R3 is connected with the PAD terminal and the drain of the third NMOS tube respectively, the fourth resistor R4 is connected with the gate of the second NMOS tube, and the fifth resistor R5 is connected with the gate of the fourth NMOS tube and the drain of the fourth NMOS tube respectively.

[0053] The receiving level conversion circuit further comprises a flip-flop, an input end of the flip-flop being connected with the inverter.

[0054] The second voltage dividing circuit comprises a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8, the seventh resistor R7 being connected with the sixth resistor R6 and the eighth resistor R8 respectively, and the inverter being connected with the seventh resistor R7 and the eighth resistor R8 respectively. The inverter comprises a fifth NMOS tube N5, a first PMOS tube P1 and a second PMOS tube P2, the second PMOS tube P2 being connected with the fifth NMOS tube N5 and the first PMOS tube P1 respectively.

[0055] The drain of the first PMOS tube is connected with the bulk end of the first PMOS tube, the source of the first PMOS tube is connected with the drain of the second PMOS tube, and the gate of the first PMOS tube is connected with the second voltage dividing circuit. The bulk end of the second PMOS tube is connected with the bulk end of the first PMOS tube, the source of the second PMOS tube is connected with the drain of the fifth NMOS tube, and the gate of the second PMOS tube is connected with the second voltage dividing circuit. The bulk end of the fifth NMOS tube is connected with the source of the fifth NMOS tube, the source of the fifth NMOS tube is connected with the second voltage dividing circuit, and the gate of the fifth NMOS tube is connected with the second voltage dividing circuit.

[0056] In the IO self-checking mode, data is transmitted from the chip interior to the internal data receiving end, the first NMOS tube, the second NMOS tube and the third NMOS tube are controlled, and the data is transmitted to the PAD end after being divided by the voltage dividing group. The data is input to the gate of the fifth NMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube from the PAD end, and is input to the chip interior by controlling the fifth NMOS tube, the first PMOS tube and the second PMOS tube, so as to detect whether the IO interface circuit is normal.

[0057] It should be noted that:

[0058] The phrase "one embodiment" or "an embodiment" as used throughout this description means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Therefore, the appearances of the phrase "one embodiment" or "an embodiment" throughout the description are not necessarily all referring to the same embodiment.

[0059] Although preferred embodiments of the application have been described, a person of ordinary skill in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the application.

[0060] Moreover, it should be noted that the specific embodiments described in the specification are illustrative only and not restrictive of the patent concept. Equivalent or similar changes or modifications made to the configuration, features and principles described in the patent concept are included in the scope of the patent. Those skilled in the art can make various modifications or supplements to the specific embodiments described or use similar ways to replace them, as long as they do not deviate from the structure of the patent or exceed the scope defined by the claims.

Claims

1. A general-purpose I / O interface circuit, characterized in that, It includes a transmit level conversion circuit and a receive level conversion circuit, wherein the transmit level conversion circuit and the receive level conversion circuit are connected; The transmit level conversion circuit includes a first voltage divider circuit and a MOSFET group. The first voltage divider circuit and the MOSFET group are connected. The first voltage divider circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor. One end of the first resistor is electrically connected to the second resistor, and the other end of the first resistor is electrically connected to the third resistor. The MOSFET group includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The drain of the first NMOS transistor is electrically connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor is electrically connected to the source of the third NMOS transistor. The source of the OS transistor is electrically connected, the source of the third NMOS transistor is also electrically connected to the gate of the second NMOS transistor, the drain of the third NMOS transistor is electrically connected to the end of the third resistor away from the first resistor, one end of the fourth resistor is electrically connected to the gate of the second NMOS transistor, the end of the first resistor close to the second resistor is also electrically connected to the gate of the third NMOS transistor, the end of the second resistor away from the first resistor is also electrically connected to the source of the first NMOS transistor, one end of the fifth resistor is electrically connected to the gate of the fourth NMOS transistor, and the other end of the fifth resistor is electrically connected to the source of the fourth NMOS transistor. The received level conversion circuit includes a second voltage divider circuit and an inverter. The second voltage divider circuit and the inverter are connected. The second voltage divider circuit includes a sixth resistor, a seventh resistor, and an eighth resistor. The inverter includes a fifth NMOS transistor, a first PMOS transistor, and a second PMOS transistor. One end of the seventh resistor is electrically connected to the sixth resistor, and the other end of the seventh resistor is electrically connected to the eighth resistor. The drain of the first PMOS transistor is connected to the bulk terminal of the first PMOS transistor, and the source of the first PMOS transistor is connected to the drain of the second PMOS transistor. The bulk terminal of the second PMOS transistor is electrically connected to the bulk terminal of the first PMOS transistor. The source of the second PMOS transistor is electrically connected to the drain of the fifth NMOS transistor. The gate of the second PMOS transistor is electrically connected to the gate of the fifth NMOS transistor. The gate of the second PMOS transistor is also electrically connected to the gate of the first PMOS transistor. One end of the seventh resistor connected to the eighth resistor is also electrically connected to the gate of the fifth NMOS transistor. The end of the eighth resistor away from the seventh resistor is electrically connected to the bulk terminal of the fifth NMOS transistor. The end of the eighth resistor away from the seventh resistor is also electrically connected to the source of the fifth NMOS transistor. Both the transmit level conversion circuit and the receive level conversion circuit include a PAD terminal. The end of the third resistor away from the third NMOS transistor is electrically connected to one end of the PAD terminal. The other end of the PAD terminal is also electrically connected to the end of the sixth resistor away from the seventh resistor. The transmit level conversion circuit and the receive level conversion circuit are connected through the PAD terminal.

2. The general-purpose I / O interface circuit as described in claim 1, characterized in that, The transmit level conversion circuit includes a capacitor, one end of which is electrically connected to the source of the first NMOS transistor, the other end of which is grounded, and the other end of which is also electrically connected to the gate of the first NMOS transistor.

3. The general-purpose I / O interface circuit as described in claim 1, characterized in that, The transmit level conversion circuit also includes an internal input terminal, the output terminal of which is electrically connected to the gate of the first NMOS transistor, and the output terminal of which is also electrically connected to the bulk terminal of the second NMOS transistor.

4. A general-purpose I / O interface circuit as described in claim 1, characterized in that, The receiving level conversion circuit also includes a flip-flop, the input of which is electrically connected to the source of the second PMOS transistor, and the input of which is also electrically connected to the drain of the fifth NMOS transistor.

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