Shift register and driving method thereof, gate driving circuit and display device

Abstract

The embodiment of the present disclosure provides a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register includes: an input module, which is used to provide a signal of a signal input terminal to a pull-up node under the control of a signal input terminal; a first pull-down module, which is used to provide a signal of a third power supply terminal to a first pull-down node under the control of a signal input terminal and / or a pull-up node; a first pull-down control module, which is used to provide a signal of a first power supply terminal to a first pull-down node under the control of a first power supply terminal when the first pull-down module stops working; a second noise reduction module, which is used to provide a signal of a third power supply terminal to a pull-up node under the control of a second pull-down node; a first node control module, which is used to provide a signal of a third power supply terminal to a second pull-down node under the control of a first power supply terminal; an output module and an output pull-down module. The present disclosure can reduce leakage of a pull-up node and avoid attenuation and distortion of an output signal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit and a display device. Background Art

[0002] GOA (Gate Drive On Array) technology is a technology that integrates a gate drive circuit into an array substrate, thereby replacing a gate drive chip to reduce power consumption and cost.

[0003] The active layer materials of the thin film transistors used in the GOA circuit can be selected from a-Si (amorphous silicon), LTPS (low temperature polycrystalline silicon), IGZO (Indium Gallium Zinc Oxide), etc. Large-size display screens usually use thin film transistors with active layer materials of IGZO as thin film transistors in GOA circuits, but when the display size and resolution are further increased, it is necessary to use oxide material thin film transistors with higher mobility for GOA circuits.

[0004] Existing products using oxide materials have defects such as abnormal display during screen scanning, which affects the quality of display products. Summary of the invention

[0005] The embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device to solve or alleviate one or more technical problems in the prior art.

[0006] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a shift register, including:

[0007] An input module, coupled to the signal input terminal and the pull-up node respectively, and configured to provide the signal of the signal input terminal to the pull-up node under the control of the signal input terminal;

[0008] A first pull-down module is coupled to the signal input terminal, the first pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the first pull-down node under the control of the signal input terminal and / or the pull-up node;

[0009] A first pull-down control module is coupled to the first power supply terminal and the first pull-down node respectively, and is configured to provide a signal of the first power supply terminal to the first pull-down node under the control of the first power supply terminal when the first pull-down module stops working;

[0010] A second noise reduction module is coupled to the second pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of the second pull-down node;

[0011] A first node control module is coupled to the first power supply terminal, the second pull-down node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the second pull-down node under the control of the first power supply terminal;

[0012] An output module, respectively connected to the pull-up node, the clock signal terminal and the first signal output terminal, is configured to provide a signal of the clock signal terminal to the first signal output terminal under the control of the pull-up node;

[0013] The output pull-down module is coupled to the first pull-down node, the second pull-down node, the fourth power supply terminal and the first signal output terminal respectively, and is configured to provide a signal of the fourth power supply terminal to the first signal output terminal under the control of the first pull-down node or the second pull-down node.

[0014] In some embodiments, the shift register further comprises:

[0015] A second pull-down module is coupled to the signal input terminal, the second pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the second pull-down node under the control of the signal input terminal and / or the pull-up node;

[0016] A second pull-down control module is coupled to the second power supply terminal and the second pull-down node respectively, and is configured to provide a signal of the second power supply terminal to the second pull-down node under the control of the second power supply terminal when the second pull-down module stops working, and the second power supply terminal and the first power supply terminal are at opposite potentials at the same time;

[0017] A first noise reduction module is coupled to the first pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of the first pull-down node;

[0018] The second node control module is coupled to the second power terminal, the first pull-down node and the third power terminal respectively, and is configured to provide a signal of the third power terminal to the first pull-down node under the control of the second power terminal.

[0019] In some embodiments, the first pull-down module includes a first pull-down submodule and a first auxiliary pull-down submodule, and the second pull-down module includes a second pull-down submodule and a second auxiliary pull-down submodule;

[0020] A first pull-down submodule is coupled to the pull-up node, the third power supply terminal and the first pull-down node respectively, and is configured to provide a signal of the third power supply terminal to the first pull-down node under the control of the pull-up node;

[0021] A first auxiliary pull-down submodule is coupled to the signal input terminal, the third power terminal and the first pull-down node respectively, and is configured to provide a signal of the third power terminal to the first pull-down node under the control of the signal input terminal;

[0022] A second pull-down submodule is coupled to the pull-up node, the third power supply terminal, and the second pull-down node, respectively, and is configured to provide a signal of the third power supply terminal to the second pull-down node under the control of the pull-up node;

[0023] The second auxiliary pull-down submodule is coupled to the signal input terminal, the third power terminal and the second pull-down node respectively, and is configured to provide a signal from the third power terminal to the second pull-down node under the control of the signal input terminal.

[0024] In some embodiments, at least one of the following is included:

[0025] The input module includes a first transistor, a gate of the first transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the first transistor are coupled to the signal input terminal and the pull-up node respectively;

[0026] The first pull-down submodule includes a sixth transistor A, a gate of the sixth transistor A is coupled to the pull-up node, and a first electrode and a second electrode of the sixth transistor A are respectively coupled to the third power supply terminal and the first pull-down node;

[0027] The first auxiliary pull-down submodule includes a seventh transistor A, a gate of the seventh transistor A is coupled to the signal input terminal, and a first electrode and a second electrode of the seventh transistor A are coupled to the third power supply terminal and the first pull-down node respectively;

[0028] The first pull-down control module includes a fifth transistor A, a gate of the fifth transistor A is coupled to the first power supply terminal, and a first electrode and a second electrode of the fifth transistor A are coupled to the first power supply terminal and the first pull-down node respectively;

[0029] The first noise reduction module includes an eighth transistor A, a gate of the eighth transistor A is coupled to the first pull-down node, and a first electrode and a second electrode of the eighth transistor A are coupled to the third power supply terminal and the pull-up node respectively;

[0030] The second noise reduction module includes an eighth transistor B, a gate of the eighth transistor B is coupled to the second pull-down node, and a first electrode and a second electrode of the eighth transistor B are coupled to the third power supply terminal and the pull-up node respectively;

[0031] The first node control module includes a fourteenth transistor A, a gate of the fourteenth transistor A is coupled to the first power supply terminal, and a first electrode and a second electrode of the fourteenth transistor A are coupled to the third power supply terminal and the second pull-down node respectively;

[0032] The second pull-down submodule includes a sixth transistor B, a gate of the sixth transistor B is coupled to the pull-up node, and a first electrode and a second electrode of the sixth transistor B are coupled to the third power supply terminal and the second pull-down node respectively;

[0033] The second auxiliary pull-down submodule includes a seventh transistor B, a gate of the seventh transistor B is coupled to the signal input terminal, and a first electrode and a second electrode of the seventh transistor B are coupled to the third power supply terminal and the second pull-down node respectively;

[0034] The second pull-down control module includes a fifth transistor B, a gate of the fifth transistor B is coupled to the second power supply terminal, and a first electrode and a second electrode of the fifth transistor B are coupled to the second power supply terminal and the second pull-down node respectively;

[0035] The second node control module includes a fourteenth transistor B, a gate of the fourteenth transistor B is coupled to the second power supply terminal, and a first electrode and a second electrode of the fourteenth transistor B are coupled to the third power supply terminal and the first pull-down node respectively.

[0036] In some embodiments,

[0037] The output module includes a third transistor and a bootstrap capacitor, the gate of the third transistor is coupled to the pull-up node, the first electrode of the third transistor is coupled to the clock signal terminal, the second electrode of the third transistor is coupled to the first signal output terminal, and the first electrode and the second electrode of the bootstrap capacitor are respectively coupled to the pull-up node and the first signal output terminal;

[0038] The output pull-down module includes a thirteenth transistor A, a gate of the thirteenth transistor A is coupled to the first pull-down node, and a first electrode and a second electrode of the thirteenth transistor A are respectively coupled to the fourth power supply terminal and the first signal output terminal.

[0039] In some embodiments, the output pull-down module further includes a thirteenth transistor B, a gate of the thirteenth transistor B is coupled to the second pull-down node, and a first electrode and a second electrode of the thirteenth transistor B are respectively coupled to the fourth power supply terminal and the first signal output terminal.

[0040] In some embodiments,

[0041] The output module further includes an eleventh transistor and a second signal output terminal, a gate of the eleventh transistor is coupled to the pull-up node, a first electrode of the eleventh transistor is coupled to the clock signal terminal, and a second electrode of the eleventh transistor is coupled to the second signal output terminal;

[0042] The output pull-down module further includes a twelfth transistor A, a gate of the twelfth transistor A is coupled to the first pull-down node, a first electrode of the twelfth transistor A is coupled to the third power supply terminal, and a second electrode of the twelfth transistor A is coupled to the second signal output terminal;

[0043] The output pull-down module further includes a twelfth transistor B, a gate of the twelfth transistor B is coupled to the second pull-down node, a first electrode of the twelfth transistor B is coupled to the third power supply terminal, and a second electrode of the twelfth transistor B is coupled to the second signal output terminal.

[0044] In some embodiments, the shift register further includes a reset module, which is respectively coupled to the reset signal terminal, the third power terminal and the pull-up node, and the reset module is configured to provide a signal from the third power terminal to the pull-up node under the control of the reset signal terminal.

[0045] In some embodiments, in the display stage of the display device, the signals at the third power terminal and the fourth power terminal are the same, and in the shutdown stage of the display device, the signal at the fourth power terminal is the same as the signal at the first power terminal.

[0046] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving method of a shift register, which is applied to the shift register in any embodiment of the present disclosure, and the method includes:

[0047] In the first stage, the signal input terminal provides a high-level signal, and the input module provides a high-level signal to the pull-up node under the control of the signal input terminal; the first pull-down module provides a signal of the third power supply terminal to the first pull-down node under the control of the signal input terminal and / or the pull-up node; the first node control module provides a signal of the third power supply terminal to the second pull-down node under the control of the first power supply terminal, so that the second pull-down node is pulled down to the potential of the third power supply terminal; the output module provides a signal of the clock signal terminal to the first signal output terminal under the control of the pull-up node;

[0048] In the second stage, the clock signal terminal provides a high level signal, so that the first signal output terminal outputs a high level signal.

[0049] As a third aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a gate driving circuit, comprising a plurality of cascaded shift registers as in any embodiment of the present disclosure.

[0050] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the shift register or the gate driving circuit in any embodiment of the present disclosure.

[0051] According to the technical solution of the embodiment of the present disclosure, the first node control module can provide a signal from the third power supply end to the second pull-down node under the control of the first power supply end, so that the potential of the second pull-down node is the same as that of the third power supply end. Therefore, the second pull-down node can completely shut down the second noise reduction module, avoid discharge of the pull-up node through the second noise reduction module, reduce leakage of the pull-up node, and facilitate the output module to fully operate and provide the signal of the clock signal end to the first signal output end, avoid signal attenuation and distortion of the first signal output end, and avoid abnormal scanning display of the display device.

[0052] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0054] Figure 1a A schematic diagram of a circuit structure of a shift register in the related art;

[0055] Figure 1b for Figure 1a The working timing diagram of the shift register shown;

[0056] Figure 2 Schematic diagram of the structure of a shift register in one embodiment of the present disclosure;

[0057] Figure 3 It is a schematic diagram of the structure of a shift register in another embodiment of the present disclosure;

[0058] Figure 4 It is a schematic diagram of the structure of a shift register in another embodiment of the present disclosure;

[0059] Figure 5 is a working timing diagram of the shift register according to an embodiment of the present disclosure;

[0060] Figure 6 FIG. 4 is a structural block diagram of a gate driving circuit in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0062] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is called the first electrode, the drain (drain electrode) is called the second electrode, or the drain can be called the first electrode and the source is called the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is specified as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain. The switching transistor used in the embodiment of the present invention can be a P-type switching transistor or an N-type transistor. The P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level; the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, multiple signals in each embodiment of the present invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential state quantities of the signal, and do not represent that the first potential or the second potential in the full text has a specific value. In the embodiment of the present invention, the first potential is taken as an effective potential for description.

[0063] The coupling may include: direct physical contact between the two ends or indirect connection between the two ends (eg, connection between the two ends via a signal line). The embodiment of the present invention does not limit the coupling method between the two ends.

[0064] The GOA circuit can be applied to a display device. The GOA circuit includes a plurality of cascaded shift registers, and the signal output end of each shift register is coupled to the gate line of a row of pixels to provide a gate drive signal to the gate line, thereby driving the display device to display. The shift register includes a plurality of thin film transistors.

[0065] In order to apply oxide material thin film transistors with higher mobility to GOA circuits, the oxide process has developed in a higher direction, from Mob10 to Mob20. Figure 1a is a schematic diagram of a circuit structure of a shift register in the related art, Figure 1b for Figure 1a The working timing diagram of the shift register is shown in FIG. Figure 1a As shown, the first power supply terminal VDDA and the second power supply terminal VDDB are in opposite potentials at the same time. For example, at the same time, one of the first power supply terminal VDDA and the second power supply terminal VDDB provides a high level signal and the other provides a low level signal. Therefore, Figure 1a The first part and the second part can work alternately to extend the life of the fifth transistor.

[0066] The inventors of the present case discovered that the first pull-down node PD1 or the second pull-down node PD2 is affected by the fifth transistor M5 (A, B). When the first power terminal VDDA or the second power terminal VDDB switches from the high level VGH to the low level VGL, before it is completely switched to the low level VGL, the gate of the fifth transistor M5 (A, B) is already closed, causing the low level signal of the first pull-down node PD1 or the second pull-down node PD2 to be smaller than the level signal of the third power terminal VGL, thereby causing leakage of the pull-up node PU.

[0067] Take the first part in working state as an example to illustrate Figure 1a The working process of the shift register shown in the figure: the first power supply terminal VDDA is at a high level, and the second power supply terminal VDDB is at a low level.

[0068] like Figure 1a and Figure 1b As shown, in the first stage (T1), the signal input terminal INPUT provides a high level, the first transistor M1 is turned on, and the pull-up node PU is charged; the seventh transistor M7 (A, B) is turned on, and the signal of the third power supply terminal VGL is provided to the first pull-down node PD1 and the second pull-down node PD2, and the first pull-down node PD1 and the second pull-down node PD2 are discharged; under the control of the pull-up node PU, the third transistor M3 and the eleventh transistor M11 are both turned on, and the signal of the clock signal terminal is provided to the first signal output terminal Gout and the second signal output terminal OC out.

[0069] In the second stage (T2), the signal input terminal INPUT provides a low-level signal, the clock signal terminal CLK outputs a high-level signal, the first transistor M1 is turned off, the pull-up node PU stops charging, the seventh transistor (M7A and M7B) are both turned off, and the first signal output terminal Gout and the second signal output terminal OC out output a high level. Under the action of the bootstrap capacitor C, the voltage of the pull-up node PU is raised again, so that the sixth transistors M6A and M6B are fully turned on, and the signal of the third power supply terminal VGL is continuously provided to the first pull-down node PD1 and the second pull-down node PD2; under the control of the pull-up node PU, the third transistor M3 and the eleventh transistor M11 are both turned on, and the high-level signal of the clock signal terminal is provided to the first signal output terminal Gout and the second signal output terminal OC out, and the first signal output terminal Gout outputs a high-level signal.

[0070] In the Mob process, the oxide thin film transistor has a left drift characteristic. Figure 1aIn the circuit, the eighth transistor (M8A and M8B) and the sixth transistor (M6A and M6B) drift to the left, with amplitudes of about 1.4V and 0.5V, so that the threshold voltage Vth of the eighth transistor (M8A and M8B) is less than 0V. The left drift of the eighth transistor M8B causes the pull-up node PU to continue to leak; the left drift of the sixth transistor (M6B) causes the second pull-down node PD2 to be unable to be pulled down to the potential of the third power supply terminal VGL, causing the potential of the second pull-down node PD2 to be greater than the potential of the third power supply terminal VGL, thereby affecting the leakage current of the third transistor M8B, causing the pull-up node PU to continue to leak, causing the third transistor M3 and the eleventh transistor M11 to be unable to be fully turned on, and affected by the cascade of the shift register in the gate drive circuit, the signals of the first signal output terminal Gout and the second signal output terminal OC out are attenuated and distorted, and gradually have no output, resulting in abnormal scanning display.

[0071] Figure 2 FIG. 1 is a schematic diagram of a structure of a shift register in an embodiment of the present disclosure. In one implementation, Figure 2 As shown, the shift register may include an input module 11 , a first pull-down module 21 , a first pull-down control module 23 , a first noise reduction module 22 , a second noise reduction module 32 , a first node control module 24 , an output module 13 and an output pull-down module 14 .

[0072] The input module 11 is coupled to the signal input terminal INPUT and the pull-up node PU respectively, and the input module 11 is configured to provide the signal of the signal input terminal INPUT to the pull-up node PU under the control of the signal input terminal INPUT. Exemplarily, under the control of the signal input terminal INPUT, the input module 11 can charge the pull-up node PU and pull the pull-up node PU to a high level.

[0073] The first pull-down module 21 is coupled to the signal input terminal INPUT, the first pull-down node PD1, the pull-up node PU and the third power supply terminal VGL, respectively. The first pull-down module 21 is configured to provide a signal of the third power supply terminal VGL to the first pull-down node PD1 under the control of the signal input terminal INPUT and / or the pull-up node PU. Exemplarily, the first pull-down module 21 discharges the first pull-down node PD1 and pulls the first pull-down node PD1 to a low level under the control of the signal input terminal INPUT and / or the pull-up node PU.

[0074] The first pull-down control module 23 is coupled to the first power supply terminal VDDA and the first pull-down node PD1, respectively. The first pull-down control module 23 is configured to provide a signal of the first power supply terminal VDDA to the first pull-down node PD1 under the control of the first power supply terminal VDDA when the first pull-down module 21 stops working, so that the first pull-down node PD1 maintains a high level.

[0075] The second noise reduction module 32 is coupled to the second pull-down node PD2, the pull-up node PU and the third power supply terminal VGL, respectively. The second noise reduction module 32 is configured to provide a signal of the third power supply terminal VGL to the pull-up node PU under the control of the second pull-down node PD2. Exemplarily, in the non-display phase of the corresponding row of pixels, the pull-up node PU is reset, the second pull-down node PD2 is restored to a high level, and the second noise reduction module 32 provides a signal of the third power supply terminal VGL to the pull-up node PU under the control of the second pull-down node PD2, thereby reducing the noise of the pull-up node PU and avoiding affecting the display.

[0076] The first node control module 24 is coupled to the first power terminal VDDA, the second pull-down node PD2 and the third power terminal VGL respectively, and is configured to provide a signal of the third power terminal VGL to the second pull-down node PD2 under the control of the first power terminal VDDA.

[0077] The output module 13 is coupled to the pull-up node PU, the clock signal terminal CLK and the first signal output terminal Gout respectively. The output module 13 is configured to provide the signal of the clock signal terminal CLK to the first signal output terminal Gout under the control of the pull-up node PU, so that the first signal output terminal Gout can output the signal of the clock signal terminal CLK.

[0078] The output pull-down module 14 is coupled to the first pull-down node PD1, the second pull-down node PD2, the fourth power supply terminal LVGL and the first signal output terminal Gout, respectively. The output pull-down module 14 is configured to provide a signal of the fourth power supply terminal LVGL to the first signal output terminal Gout under the control of the first pull-down node PD1 or the second pull-down node PD2.

[0079] Exemplarily, the first power terminal VDDA may provide a high level signal, and the third power terminal VGL may provide a low level signal. During operation of the display device, the signal provided by the fourth power terminal LVGL may be the same as the signal provided by the third power terminal VGL.

[0080] Exemplarily, the pull-up node PU and the first pull-down node PD1 are in a competitive relationship, that is, when the pull-up node PU is a high-level signal, the first pull-down node PD1 is a low-level signal; when the pull-up node PU is reset to a low-level signal, the first pull-down node PD1 is restored to a high-level signal.

[0081] According to the technical solution disclosed in the present invention, the first node control module 24 can provide the signal of the third power supply terminal VGL to the second pull-down node PD2 under the control of the first power supply terminal VDDA, so that the potential of the second pull-down node PD2 is the same as that of the third power supply terminal VGL. Therefore, the second pull-down node PD2 can completely shut down the second noise reduction module 32, avoid the discharge of the pull-up node PU through the second noise reduction module 32, reduce the leakage of the pull-up node PU, and facilitate the output module 13 to fully work and provide the signal of the clock signal terminal CLK to the first signal output terminal Gout, avoid the signal attenuation and distortion of the first signal output terminal Gout, and avoid abnormal scanning display of the display device.

[0082] In one embodiment, Figure 2 As shown, the shift register may further include a second pull-down module 31 , a second pull-down control module 33 , a first noise reduction module 22 and a second node control module 34 .

[0083] The second pull-down module 31 is coupled to the signal input terminal INPUT, the second pull-down node PD2, the pull-up node PU and the third power supply terminal VGL, respectively, and the second pull-down module 31 is configured to provide a signal of the third power supply terminal VGL to the second pull-down node PD2 under the control of the signal input terminal INPUT and / or the pull-up node PU.

[0084] The second pull-down control module 33 is coupled to the second power supply terminal VDDB and the second pull-down node PD2 respectively. The second pull-down control module 33 is configured to provide a signal of the second power supply terminal VDDB to the second pull-down node PD2 under the control of the second power supply terminal VDDB when the second pull-down module 31 stops working. The second power supply terminal VDDB and the first power supply terminal VDDA are at opposite potentials at the same time.

[0085] The first noise reduction module 22 is coupled to the first pull-down node PD1, the pull-up node PU and the third power supply terminal VGL, respectively. The first noise reduction module 22 is configured to provide a signal of the third power supply terminal VGL to the pull-up node PU under the control of the first pull-down node PD1. Exemplarily, in the non-display phase of the corresponding row of pixels, the pull-up node PU is reset, the first pull-down node PD1 is restored to a high level, and the first noise reduction module 22 provides a signal of the third power supply terminal VGL to the pull-up node PU under the control of the first pull-down node PD1, thereby reducing the noise of the pull-up node PU and avoiding affecting the display.

[0086] The second node control module 34 is coupled to the second power terminal VDDB, the first pull-down node PD1 and the third power terminal VGL respectively, and is configured to provide a signal of the third power terminal VGL to the first pull-down node PD1 under the control of the second power terminal VDDB.

[0087] like Figure 2 As shown, for such a shift register, the first pull-down module 21, the first pull-down control module 23, the first noise reduction module 22 and the first node control module 24 can be the first part, and the second pull-down module 31, the second pull-down control module 33, the second noise reduction module 32 and the second node control module 34 can be the second part.

[0088] Exemplarily, the first power supply terminal VDDA and the second power supply terminal VDDB are in opposite potentials at the same time. For example, the first power supply terminal VDDA provides a high-level signal, the second power supply terminal VDDB provides a low-level signal, and the first part is in a working state; the first power supply terminal VDDA provides a low-level signal, the second power supply terminal VDDB provides a high-level signal, and the second part is in a working state. In such a shift register, the first part and the second part can work alternately, extending the life of the fifth transistor M5A and the fifth transistor M5B, thereby extending the life of the shift register.

[0089] The shift register of the disclosed embodiment, when the first part is in the working state, the first power supply terminal VDDA provides a high-level signal, and the first node control module 24, under the control of the high-level signal of the first power supply terminal VDDA, provides the signal of the third power supply terminal VGL to the second pull-down node PD2, so that the second pull-down node PD2 maintains the signal of the third power supply terminal VGL, and the potential of the second pull-down node PD2 reaches the third power supply terminal VGL level. Thus, the second pull-down node PD2 can completely shut down the second noise reduction module 32, avoid the discharge of the pull-up node PU through the second noise reduction module 32, reduce the leakage of the pull-up node PU, and facilitate the output module 13 to fully work and provide the signal of the clock signal terminal CLK to the first signal output terminal, avoid the signal attenuation and distortion of the first signal output terminal Gout, and avoid the abnormal scanning display of the display device.

[0090] When the second part is in working state, the second power supply terminal VDDB provides a high level signal, and the second node control module 34 provides the signal of the third power supply terminal VGL to the first pull-down node PD1 under the control of the high level signal of the second power supply terminal VDDB, so that the first pull-down node PD1 maintains the signal of the third power supply terminal VGL, and the potential of the first pull-down node PD1 reaches the level of the third power supply terminal VGL. Therefore, the first pull-down node PD1 can completely shut down the first noise reduction module 22, avoid the discharge of the pull-up node PU through the first noise reduction module 22, reduce the leakage of the pull-up node PU, and facilitate the output module 13 to fully work and provide the signal of the clock signal terminal CLK to the first signal output terminal, avoid the signal attenuation and distortion of the first signal output terminal Gout, and avoid the abnormal scanning display of the display device.

[0091] Therefore, the shift register in the embodiment of the present disclosure can not only extend the life of the shift register, but also avoid signal attenuation and distortion at the first signal output terminal Gout, and avoid abnormal screen scanning display of the display device.

[0092] Figure 3 FIG. 1 is a schematic diagram of the structure of a shift register in another embodiment of the present disclosure. In one implementation, Figure 3 As shown, the first pull-down module 21 includes a first pull-down submodule 211 and a first auxiliary pull-down submodule 212 .

[0093] Exemplarily, the first pull-down submodule 211 is coupled to the pull-up node PU, the third power terminal VGL and the first pull-down node PD1 respectively, and is configured to provide a signal of the third power terminal VGL to the first pull-down node PD1 under the control of the pull-up node PU.

[0094] Exemplarily, the first auxiliary pull-down submodule 212 is coupled to the signal input terminal INPUT, the third power terminal VGL and the first pull-down node PD1 respectively, and is configured to provide a signal of the third power terminal VGL to the first pull-down node PD1 under the control of the signal input terminal INPUT.

[0095] When the signal input terminal INPUT provides a valid level signal, the input module 11, under the control of the signal input terminal INPUT, provides the signal of the signal input terminal INPUT to the pull-up node PU, charges the pull-up node PU, and thus pulls up the potential of the pull-up node PU. The first auxiliary pull-down submodule 212, under the control of the signal input terminal INPUT, provides the signal of the third power supply terminal VGL to the first pull-down node PD1, so that the first pull-down node PD1 is discharged, thereby lowering the potential of the first pull-down node PD1. After the pull-up node PU is pulled up to a high level signal, the first pull-down submodule 211, under the control of the pull-up node PU, provides the signal of the third power supply terminal VGL to the first pull-down node PD1, so that the first pull-down node PD1 is discharged, thereby lowering the potential of the first pull-down node PD1. The first auxiliary pull-down submodule 212 and the first pull-down submodule 211 cooperate with each other, so that in the stage where the pull-up node PU is pulled up, the first pull-down node PD1 is continuously pulled down and maintained at a low potential. Therefore, the first noise reduction module 22 can be completely turned off under the control of the first pull-down node PD1, so as to prevent the pull-up node PU from discharging through the first noise reduction module 22 and reduce leakage of the pull-up node PU.

[0096] In one embodiment, the second pull-down module 31 includes a second pull-down sub-module 311 and a second auxiliary pull-down sub-module 312 .

[0097] Exemplarily, the second pull-down submodule 311 is coupled to the pull-up node PU, the third power terminal VGL and the second pull-down node PD2 respectively, and is configured to provide a signal of the third power terminal VGL to the second pull-down node PD2 under the control of the pull-up node PU.

[0098] Exemplarily, the second auxiliary pull-down submodule 312 is coupled to the signal input terminal INPUT, the third power terminal VGL and the second pull-down node PD2 respectively, and is configured to provide a signal of the third power terminal VGL to the second pull-down node PD2 under the control of the signal input terminal INPUT.

[0099] When the second part is in working state, the second auxiliary pull-down submodule 312 and the second pull-down submodule 311 cooperate with each other, so that when the pull-up node PU is pulled up, the second pull-down node PD2 is continuously pulled down and maintained at a low potential. Thus, the second noise reduction module 32 can be completely turned off under the control of the second pull-down node PD2, avoiding the discharge of the pull-up node PU through the second noise reduction module 32, and reducing the leakage of the pull-up node PU.

[0100] Figure 4 Schematic diagram of the structure of the shift register in another embodiment of the present disclosure. In one embodiment, the input module 11 includes a first transistor M1, the gate of the first transistor M1 is coupled to the signal input terminal INPUT, and the first electrode and the second electrode of the first transistor M1 are coupled to the signal input terminal INPUT and the pull-up node PU respectively. Exemplarily, the first transistor M1 can be turned on when the signal input terminal INPUT provides a valid level, and provide the signal of the signal input terminal INPUT to the pull-up node PU of the first transistor M1.

[0101] In one embodiment, the first pull-down submodule 211 includes a sixth transistor M6A, a gate of the sixth transistor M6A is coupled to the pull-up node PU, and a first electrode and a second electrode of the sixth transistor M6A are coupled to the third power supply terminal VGL and the first pull-down node PD1, respectively. Exemplarily, the sixth transistor M6A can be turned on when the pull-up node PU is at an effective level, and provide a signal of the third power supply terminal VGL to the first pull-down node PD1.

[0102] In one embodiment, the first auxiliary pull-down submodule 212 includes a seventh transistor M7A, a gate of the seventh transistor M7A is coupled to the signal input terminal INPUT, and a first electrode and a second electrode of the seventh transistor M7A are coupled to the third power supply terminal VGL and the first pull-down node PD1, respectively. Exemplarily, the seventh transistor M7A can be turned on when the signal input terminal INPUT provides a valid level, and provide the signal of the third power supply terminal VGL to the first pull-down node PD1.

[0103] In one embodiment, the first pull-down control module 23 includes a fifth transistor M5A, a gate of the fifth transistor M5A is coupled to the first power supply terminal VDDA, and a first electrode and a second electrode of the fifth transistor M5A are coupled to the first power supply terminal VDDA and the first pull-down node PD1, respectively. Exemplarily, the fifth transistor M5A can be turned on when the first power supply terminal VDDA is at an effective level, and provide a signal of the first power supply terminal VDDA to the first pull-down node PD1.

[0104] In one embodiment, the first noise reduction module 22 includes an eighth transistor M8A, a gate of the eighth transistor M8A is coupled to the first pull-down node PD1, and a first electrode and a second electrode of the eighth transistor M8A are respectively coupled to the third power supply terminal VGL and the pull-up node PU. Exemplarily, the eighth transistor M8A can be turned on when the first pull-down node PD1 is at an effective level, and provide a signal of the third power supply terminal VGL to the pull-up node PU.

[0105] In one embodiment, the second noise reduction module 32 includes an eighth transistor M8B, a gate of the eighth transistor M8B is coupled to the second pull-down node PD2, and a first electrode and a second electrode of the eighth transistor M8B are coupled to the third power supply terminal VGL and the pull-up node PU, respectively. Exemplarily, the eighth transistor M8B can be turned on when the second pull-down node PD2 is at an effective level, and provide a signal of the third power supply terminal VGL to the pull-up node PU.

[0106] In one embodiment, the first node control module 24 includes a fourteenth transistor M14A, a gate of the fourteenth transistor M14A is coupled to the first power supply terminal VDDA, and a first electrode and a second electrode of the fourteenth transistor M14A are respectively coupled to the third power supply terminal VGL and the second pull-down node PD2. Exemplarily, the fourteenth transistor M14A can be turned on when the first power supply terminal VDDA is at an effective level, and provide a signal of the third power supply terminal VGL to the second pull-down node PD2.

[0107] In one embodiment, the second pull-down submodule 311 includes a sixth transistor M6B, a gate of the sixth transistor M6B is coupled to the pull-up node PU, and a first electrode and a second electrode of the sixth transistor M6B are respectively coupled to the third power supply terminal VGL and the second pull-down node PD2. Exemplarily, the sixth transistor M6B can be turned on when the pull-up node PU is at an effective level, and provide a signal of the third power supply terminal VGL to the second pull-down node PD2.

[0108] In one embodiment, the second auxiliary pull-down submodule 312 includes a seventh transistor M7B, a gate of the seventh transistor M7B is coupled to the signal input terminal INPUT, and a first electrode and a second electrode of the seventh transistor M7B are respectively coupled to the third power supply terminal VGL and the second pull-down node PD2. Exemplarily, the seventh transistor M7B can be turned on when the signal input terminal INPUT provides a valid level, and provide the signal of the third power supply terminal VGL to the second pull-down node PD2.

[0109] In one embodiment, the second pull-down control module 33 includes a fifth transistor M5B, a gate of the fifth transistor B is coupled to the second power supply terminal VDDB, and a first electrode and a second electrode of the fifth transistor M5B are respectively coupled to the second power supply terminal VDDB and the second pull-down node PD2. Exemplarily, the fifth transistor M5B can be turned on when the second power supply terminal VDDB is at an effective level, and a signal of the second power supply terminal VDDB is sent to the second pull-down node PD2.

[0110] In one embodiment, the second node control module 34 includes a fourteenth transistor M14B, a gate of the fourteenth transistor M14B is coupled to the second power supply terminal VDDB, and a first electrode and a second electrode of the fourteenth transistor M14B are coupled to the third power supply terminal VGL and the first pull-down node PD1, respectively. Exemplarily, the fourteenth transistor M14B can be turned on when the second power supply terminal VDDB is at an effective level, and provide a signal of the third power supply terminal VGL to the first pull-down node PD1.

[0111] In one embodiment, Figure 3 As shown, the output module 13 includes a third transistor M3 and a bootstrap capacitor C, the gate of the third transistor M3 is coupled to the pull-up node PU, the first electrode of the third transistor M3 is coupled to the clock signal terminal CLK, the second electrode of the third transistor M3 is coupled to the first signal output terminal, and the first electrode and the second electrode of the bootstrap capacitor are coupled to the pull-up node PU and the first signal output terminal respectively.

[0112] The third transistor M3 is turned on under the high level signal of the pull-up node PU, and when the clock signal terminal CLK is a high level signal, the high level signal of the clock signal terminal CLK is provided to the first signal output terminal, and the first signal output terminal can output a high level signal. Under the bootstrap effect of the bootstrap capacitor C, the potential of the pull-up node PU is raised again, so that the third transistor M3 is turned on more fully, ensuring the stable output of the first signal output terminal and avoiding attenuation and distortion of the output signal of the first signal output terminal.

[0113] Exemplarily, the output pull-down module 14 includes a thirteenth transistor M13A, a gate of the thirteenth transistor M13A is coupled to the first pull-down node PD1, and a first electrode and a second electrode of the thirteenth transistor M13A are coupled to the fourth power supply terminal LVGL and the first signal output terminal, respectively. Exemplarily, when the corresponding row of pixels does not need to be displayed, the thirteenth transistor M13A is turned on when the first pull-down node PD1 is at an effective level, and provides the signal of the fourth power supply terminal LVGL to the first signal output terminal.

[0114] In one embodiment, Figure 3 As shown, the output pull-down module 14 further includes a thirteenth transistor M13B, a gate of the thirteenth transistor M13B is coupled to the second pull-down node PD2, and a first electrode and a second electrode of the thirteenth transistor M13B are respectively coupled to the fourth power supply terminal LVGL and the first signal output terminal.

[0115] When the first part is in the working state, when the corresponding row of pixels does not need to be displayed, the first pull-down node PD1 returns to a high level, the thirteenth transistor M13A is turned on under the control of the first pull-down node PD1, and provides the signal of the fourth power supply terminal LVGL to the first signal output terminal. When the second part is in the working state, when the corresponding row of pixels does not need to be displayed, the second pull-down node PD2 returns to a high level, the thirteenth transistor M13B is turned on under the control of the second pull-down node PD2, and provides the signal of the fourth power supply terminal LVGL to the first signal output terminal.

[0116] In one embodiment, Figure 4 As shown, the output module 13 also includes an eleventh transistor M11 and a second signal output terminal. The gate of the eleventh transistor M11 is coupled to the pull-up node PU, the first electrode of the eleventh transistor M11 is coupled to the clock signal terminal CLK, and the second electrode of the eleventh transistor M11 is coupled to the second signal output terminal. Exemplarily, the eleventh transistor M11 is turned on under the control of the pull-up node PU, and the signal of the clock signal terminal CLK can be provided to the second signal output terminal OC out.

[0117] In the GOA circuit, the first signal output terminal Gout can be coupled to the corresponding gate line to provide a gate drive signal to the corresponding row of pixels. The second signal output terminal OC out can be coupled to the signal input terminal INPUT of the next-stage shift register to trigger the next-stage shift register; the second signal output terminal OC out can also be coupled to the reset signal terminal RST of the previous-stage shift register to reset the previous-stage shift register. The second signal output terminal OC out is used as the cascade signal of the GOA circuit to avoid affecting the output signal of the second signal output terminal Gout and to avoid affecting the display.

[0118] Exemplarily, the output pull-down module 14 further includes a twelfth transistor M12A, the gate of the twelfth transistor M12A is coupled to the first pull-down node PD1, the first electrode of the twelfth transistor M12A is coupled to the third power supply terminal VGL, and the second electrode of the twelfth transistor M12A is coupled to the second signal output terminal. Exemplarily, the output pull-down module 14 further includes a twelfth transistor M12B, the gate of the twelfth transistor M12B is coupled to the second pull-down node PD2, the first electrode of the twelfth transistor M12B is coupled to the third power supply terminal VGL, and the second electrode of the twelfth transistor M12B is coupled to the second signal output terminal.

[0119] When the first part is in the working state, the first power supply terminal VDDA provides a high level signal, the second power supply terminal VDDB provides a low level signal, and when the corresponding row of pixels does not need to be displayed, the first pull-down node PD1 restores the high level, and the twelfth transistor M12A is turned on under the control of the first pull-down node PD1, and provides the signal of the fourth power supply terminal LVGL to the second signal output terminal. When the second part is in the working state, the second power supply terminal VDDB provides a high level signal, the first power supply terminal VDDA provides a low level signal, and when the corresponding row of pixels does not need to be displayed, the second pull-down node PD2 restores the high level, and the twelfth transistor M12B is turned on under the control of the second pull-down node PD2, and provides the signal of the fourth power supply terminal LVGL to the second signal output terminal.

[0120] In one embodiment, Figure 2 to Figure 4 As shown, the shift register may further include a reset module 12, which is respectively coupled to the reset signal terminal RST, the third power supply terminal VGL and the pull-up node PU, and the reset module 12 is configured to provide a signal of the third power supply terminal VGL to the pull-up node PU under the control of the reset signal terminal RST.

[0121] Exemplarily, the reset module 12 may include a second transistor M2, a gate of the second transistor M2 is coupled to the reset signal terminal RST, and a first electrode and a second electrode of the second transistor M2 are respectively coupled to the third power supply terminal VGL and the pull-up node PU. Exemplarily, the second transistor M2 is turned on under the control of the reset signal terminal RST, and provides a signal of the third power supply terminal VGL to the pull-up node PU to reset the pull-up node PU.

[0122] Exemplarily, the thin film transistors in the shift register are all oxide transistors, for example, the material of the active layers of the thin film transistors is all oxide.

[0123] Exemplarily, the thin film transistors in the shift register are all NMOS transistors, such as Figure 4 When the transistors in the shift register are NMOS transistors, the effective level of each transistor is a high level signal.

[0124] In one implementation, the width of the conductive channel of the first transistor M1 may be in the range of 180 μm to 220 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the first transistor M1 is 200 μm, and the length is 5 μm.

[0125] The width of the conductive channel of the second transistor M2 may be in the range of 20 μm to 30 μm, and the length may be in the range of 8 μm to 12 μm; illustratively, the width of the conductive channel of the second transistor M2 is 25 μm, and the length is 10 μm.

[0126] The width of the conductive channel of the third transistor M3 may be in the range of 1100 μm to 1300 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the third transistor M3 is 1200 μm, and the length is 5 μm.

[0127] The width of the conductive channel of the fifth transistor M5 may be in the range of 4 μm to 6 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the fifth transistor M5 is 5 μm, and the length is 5 μm.

[0128] The width of the conductive channel of the sixth transistor M6 (A, B) may be in the range of 35 μm to 45 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the sixth transistor M6 (A, B) is 40 μm, and the length is 5 μm.

[0129] The width of the conductive channel of the seventh transistor M7 (A, B) may be in the range of 15 μm to 25 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the seventh transistor M7 (A, B) is 20 μm, and the length is 5 μm.

[0130] The width of the conductive channel of the eighth transistor M8 (A, B) may be in the range of 120 μm to 160 μm, and the length may be in the range of 8 μm to 12 μm; illustratively, the width of the conductive channel of the eighth transistor M8 (A, B) is 140 μm, and the length is 10 μm.

[0131] The width of the conductive channel of the eleventh transistor M11 may be in the range of 550 μm to 650 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the eleventh transistor M11 is 608 μm, and the length is 5 μm.

[0132] The width of the conductive channel of the twelfth transistor M12 (A, B) may be in the range of 8 μm to 12 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the twelfth transistor M12 (A, B) is 10 μm, and the length is 5 μm.

[0133] The width of the conductive channel of the thirteenth transistor M13 (A, B) may be in the range of 35 μm to 45 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the thirteenth transistor M13 (A, B) is 40 μm, and the length is 5 μm.

[0134] The width of the conductive channel of the fourteenth transistor M14 (A, B) may be in the range of 18 μm to 22 μm, and the length may be in the range of 4 μm to 6 μm; illustratively, the width of the conductive channel of the fourteenth transistor M14 (A, B) is 20 μm, and the length is 5 μm.

[0135] It should be noted that, in the shift register in the embodiment of the present disclosure, in actual use, the type of each transistor is not limited. Each transistor can be set as an NMOS tube or a PMOS tube as needed, and the effective level of the signal input terminal INPUT, the first power supply terminal VDDA, the second power supply terminal VDDB, the third power supply terminal VGL, and the fourth power supply terminal LVGL is set accordingly. In the case where the transistors in the shift register are PMOS tubes, the effective level of each transistor is a low level signal.

[0136] Exemplarily, in the display stage of the display device, the signals of the third power terminal VGL and the fourth power terminal LVGL are the same. In the shutdown stage of the display device, the signal of the fourth power terminal LVGL is the same as the signal of the first power terminal VDDA. That is, when the display device is shut down, the signal of the fourth power terminal LVGL is pulled up to a high-level signal, and then changes with the change of the high-level signal, so as to discharge the pixels in the display area. For example, when the first part is shut down in the working state, the signal of the fourth power terminal LVGL is pulled up to the potential of the first power terminal VDDA, and then changes with the change of the potential of the first power terminal VDDA, so as to discharge the pixels in the display area.

[0137] It should be noted that Figure 4 The exemplary structure of each module or submodule is shown in FIG. 1 . Those skilled in the art will appreciate that each module or submodule is not limited to Figure 4 The structure shown will suffice as long as it can achieve its function.

[0138] Figure 5 1 is a working timing diagram of the shift register in the embodiment of the present disclosure. Figure 4 and Figure 5 ,by Figure 5Taking the first part in working state as an example, the working process of the shift register is explained in detail.

[0139] In the first stage, i.e., stage T1, the signal input terminal INPUT provides a high-level signal, and the first transistor M1 is turned on under the control of the signal input terminal INPUT, and provides the high-level signal of the signal input terminal INPUT to the pull-up node PU, so as to charge the pull-up node PU and pull up the potential of the pull-up node PU; the seventh transistor M7A is turned on under the control of the signal input terminal INPUT, and provides the signal of the third power supply terminal VGL to the first pull-down node PD1, so that the first pull-down node PD1 is discharged through the seventh transistor M7A, thereby lowering the potential of the first pull-down node PD1; when the potential of the pull-up node PU is greater than the threshold voltage of the sixth transistor M6A, the sixth transistor M6A is turned on under the control of the pull-up node PU, and provides the signal of the third power supply terminal VGL to the first pull-down node PD1, so that the first pull-down node PD1 is discharged through the sixth transistor M6A, thereby further lowering the potential of the first pull-down node PD1.

[0140] The first power supply terminal VDDA provides a high-level signal to control the fourteenth transistor M14A to be turned on, and provides the signal of the third power supply terminal VGL to the second pull-down node PD2, so that the second pull-down node PD2 is discharged through the fourteenth transistor M14A, and the second pull-down node PD2 is pulled down to the signal of the third power supply terminal VGL, so that the second pull-down node PD2 maintains the same potential as the third power supply terminal VGL, that is, the second pull-down node PD2 is pulled down to the third power supply terminal VGL level. Furthermore, the low potential of the second pull-down node PD2 can completely turn off the eighth transistor M8B, avoiding leakage of the pull-up node PU through the eighth transistor M8B, and reducing leakage of the pull-up node PU.

[0141] When the second pull-down node PD2 is pulled down to the level of the third power supply terminal VGL, the source and drain voltages of the sixth transistor M6B are both equal to the voltage of the third power supply terminal VGL, so that the I ds =0, the drift of the sixth transistor M6B can be reduced. Thus, in the non-display stage of the corresponding row of pixels, i.e., the third stage T3, the leakage of the second pull-down node PD2 through the sixth transistor M6B can be reduced, so that the eighth transistor M8B can be fully opened, reducing the noise of the pull-up node PU. Similarly, when the second part is in the working state, when the first pull-down node PD1 is pulled down to the third power supply terminal VGL level, the source and drain voltages of the sixth transistor M6A are both the voltage of the third power supply terminal VGL, so that the I of the sixth transistor M6A ds= 0, the drift of the sixth transistor M6A can be reduced. Thus, in the non-display phase of the corresponding row of pixels, i.e., the third phase T3, the leakage of the first pull-down node PD1 through the sixth transistor M6A can be reduced, so that the eighth transistor M8A can be fully opened, reducing the noise of the pull-up node PU.

[0142] When the potential of the pull-up node PU is greater than the threshold voltage of the third transistor M3 and the eleventh transistor M11, the third transistor M3 and the eleventh transistor M11 are turned on under the control of the pull-up node PU, and provide the signal of the clock signal terminal CLK to the first signal output terminal Gout and the second signal output terminal OC out respectively. In the embodiment of the present disclosure, the output signals of the first signal output terminal Gout and the second signal output terminal OC out are the same.

[0143] In the second stage, i.e., stage T2, the clock signal terminal CLK provides a high level signal, so that the first signal output terminal Gout and the second signal output terminal OC out respectively output high level signals. Under the action of the bootstrap capacitor, the potential of the pull-up node PU is raised again, so that the third transistor M3 and the eleventh transistor M11 are fully turned on, so that the first signal output terminal Gout and the second signal output terminal OC out can output stable high level signals.

[0144] In the third stage, i.e., stage T3, the reset signal of the reset signal terminal RST controls the second transistor M2 to turn on, and provides the signal of the third power supply terminal VGL to the pull-up node PU, so that the pull-up node PU is reset to a low level signal, and the sixth transistor M6A, the third transistor M3, and the eleventh transistor M11 are all turned off. The first power supply terminal VDDA controls the fifth transistor M5A to turn on, and provides the signal of the first power supply terminal VDDA to the first pull-down node PD1. The second pull-down node PD2 maintains the signal at the third power supply terminal VGL through the fourteenth transistor M14A.

[0145] The thirteenth transistor M13A is turned on under the control of the first pull-down node PD1, and provides the signal of the fourth power supply terminal LVGL to the first signal output terminal Gout, and the first signal output terminal Gout outputs a low level signal; the twelfth transistor M12A is turned on under the control of the first pull-down node PD1, and provides the signal of the third power supply terminal VGL to the second signal output terminal OC out, and the second signal output terminal OC out outputs a low level signal.

[0146] The embodiment of the present disclosure further provides a driving method of a shift register, wherein the shift register is the shift register in any embodiment of the present disclosure. The driving method of the shift register includes:

[0147] In the first stage, i.e., stage T1, the input module 11 provides a high-level signal to the pull-up node PU under the control of the signal input terminal INPUT; the first pull-down module 21 provides a signal of the third power supply terminal VGL to the first pull-down node PD1 under the control of the signal input terminal INPUT and / or the pull-up node PU; the first node control module 24 provides a signal of the third power supply terminal VGL to the second pull-down node PD2 under the control of the first power supply terminal VDDA, so that the second pull-down node PD2 is pulled down to the potential of the third power supply terminal VGL; the output module 13 provides a signal of the clock signal terminal CLK to the first signal output terminal Gout under the control of the pull-up node PU.

[0148] In the second stage, ie, stage T2, the clock signal terminal CLK provides a high level signal, so that the first signal output terminal Gout outputs a high level signal.

[0149] In the third stage, i.e., stage T3, the reset module 12, under the control of the reset signal terminal RST, provides the third power terminal VGL signal to the pull-up node PU, resets the pull-up node PU, and the first signal output terminal stops outputting the signal of the clock signal terminal CLK. The output pull-down module 14, under the control of the first pull-down node PD1, provides the signal of the fourth power terminal LVGL to the first signal output terminal Gout, so that the first signal output terminal Gout outputs the signal of the fourth power terminal LVGL.

[0150] In one embodiment, in the first stage, i.e., stage T1, the output module 13 provides the signal of the clock signal terminal CLK to the second signal output terminal OC out under the control of the pull-up node PU. In the second stage, i.e., stage T2, the clock signal terminal CLK provides a high-level signal, so that the second signal output terminal OC out outputs a high-level signal. In the third stage, i.e., stage T3, the output pull-down module 14 provides the signal of the third power supply terminal VGL to the second signal output terminal OC out under the control of the first pull-down node PD1, so that the second signal output terminal OC out outputs the signal of the third power supply terminal VGL.

[0151] The specific process of the shift register driving method may be as described above.

[0152] The present disclosure also provides a gate drive circuit. Figure 6 As shown, Figure 6 1 is a structural block diagram of a gate driving circuit in an embodiment of the present disclosure. The gate driving circuit may include a plurality of shift registers as in any embodiment of the present disclosure, and the plurality of shift registers are cascade-coupled.

[0153] Exemplarily, the gate drive circuit includes n-stage cascaded shift registers. The output module 13 includes a first signal output terminal Gout and a second signal output terminal OC out, the first signal output terminal Gout of the j-stage shift register is coupled to the gate line, the second signal output terminal OC out of the j-stage shift register is coupled to the signal input terminal INPUT of the j+1-stage shift register, and the second signal output terminal of the j-stage shift register is coupled to the reset signal terminal RST of the j-1-stage shift register. Wherein, j is greater than 1 and less than n. The signal input terminal INPUT of the first-stage shift register is coupled to the trigger signal terminal STV.

[0154] The embodiments of the present disclosure further provide a display device, comprising the shift register in any embodiment of the present disclosure or the gate driving circuit in any embodiment of the present disclosure.

[0155] Based on the inventive concept of the above embodiments, the embodiments of the present disclosure further provide a display device, which includes a display panel using the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0156] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0157] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0158] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0159] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0160] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0161] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: An input module, coupled to the signal input terminal and the pull-up node respectively, and configured to provide the signal of the signal input terminal to the pull-up node under the control of the signal input terminal; A first pull-down module is coupled to the signal input terminal, the first pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the first pull-down node under the control of the signal input terminal and / or the pull-up node; A first pull-down control module is coupled to the first power supply terminal and the first pull-down node respectively, and is configured to provide a signal of the first power supply terminal to the first pull-down node under the control of the first power supply terminal when the first pull-down module stops working; A second noise reduction module is coupled to the second pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of the second pull-down node; A first node control module is coupled to the first power terminal, the second pull-down node and the third power terminal respectively, and is configured to provide a signal of the third power terminal to the second pull-down node under the control of the first power terminal; An output module, respectively connected to the pull-up node, the clock signal terminal and the first signal output terminal, and configured to provide the signal of the clock signal terminal to the first signal output terminal under the control of the pull-up node; The output pull-down module is coupled to the first pull-down node, the second pull-down node, the fourth power supply terminal and the first signal output terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first signal output terminal under the control of the first pull-down node or the second pull-down node.

2. The shift register according to claim 1, characterized in that: Also includes: A second pull-down module is coupled to the signal input terminal, the second pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide the signal of the third power supply terminal to the second pull-down node under the control of the signal input terminal and / or the pull-up node; A second pull-down control module is coupled to the second power supply terminal and the second pull-down node respectively, and is configured to provide a signal of the second power supply terminal to the second pull-down node under the control of the second power supply terminal when the second pull-down module stops working, and the second power supply terminal and the first power supply terminal are at opposite potentials at the same time; A first noise reduction module is coupled to the first pull-down node, the pull-up node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of the first pull-down node; The second node control module is coupled to the second power supply terminal, the first pull-down node and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the first pull-down node under the control of the second power supply terminal.

3. The shift register according to claim 2, characterized in that: The first pull-down module includes a first pull-down submodule and a first auxiliary pull-down submodule, and the second pull-down module includes a second pull-down submodule and a second auxiliary pull-down submodule; A first pull-down submodule is coupled to the pull-up node, the third power supply terminal and the first pull-down node respectively, and is configured to provide a signal of the third power supply terminal to the first pull-down node under the control of the pull-up node; A first auxiliary pull-down submodule, coupled to the signal input terminal, the third power terminal and the first pull-down node respectively, and configured to provide the signal of the third power terminal to the first pull-down node under the control of the signal input terminal; A second pull-down submodule is coupled to the pull-up node, the third power supply terminal and the second pull-down node respectively, and is configured to provide a signal of the third power supply terminal to the second pull-down node under the control of the pull-up node; The second auxiliary pull-down submodule is coupled to the signal input terminal, the third power terminal and the second pull-down node respectively, and is configured to provide the signal of the third power terminal to the second pull-down node under the control of the signal input terminal.

4. The shift register according to claim 3, characterized in that: Include at least one of the following: The input module comprises a first transistor, a gate of the first transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the first transistor are respectively coupled to the signal input terminal and the pull-up node; The first pull-down submodule includes a sixth transistor A, a gate of the sixth transistor A is coupled to the pull-up node, and a first electrode and a second electrode of the sixth transistor A are respectively coupled to the third power supply terminal and the first pull-down node; The first auxiliary pull-down submodule includes a seventh transistor A, a gate of the seventh transistor A is coupled to the signal input terminal, and a first electrode and a second electrode of the seventh transistor A are coupled to the third power supply terminal and the first pull-down node respectively; The first pull-down control module includes a fifth transistor A, a gate of the fifth transistor A is coupled to the first power supply terminal, and a first electrode and a second electrode of the fifth transistor A are coupled to the first power supply terminal and the first pull-down node respectively; The first noise reduction module includes an eighth transistor A, a gate of the eighth transistor A is coupled to the first pull-down node, and a first electrode and a second electrode of the eighth transistor A are respectively coupled to the third power supply terminal and the pull-up node; The second noise reduction module includes an eighth transistor B, a gate of the eighth transistor B is coupled to the second pull-down node, and a first electrode and a second electrode of the eighth transistor B are respectively coupled to the third power supply terminal and the pull-up node; The first node control module includes a fourteenth transistor A, a gate of the fourteenth transistor A is coupled to the first power supply terminal, and a first electrode and a second electrode of the fourteenth transistor A are respectively coupled to the third power supply terminal and the second pull-down node; The second pull-down submodule includes a sixth transistor B, a gate of the sixth transistor B is coupled to the pull-up node, and a first electrode and a second electrode of the sixth transistor B are respectively coupled to the third power supply terminal and the second pull-down node; The second auxiliary pull-down submodule includes a seventh transistor B, a gate of the seventh transistor B is coupled to the signal input terminal, and a first electrode and a second electrode of the seventh transistor B are coupled to the third power supply terminal and the second pull-down node respectively; The second pull-down control module includes a fifth transistor B, a gate of the fifth transistor B is coupled to the second power supply terminal, and a first electrode and a second electrode of the fifth transistor B are coupled to the second power supply terminal and the second pull-down node respectively; The second node control module includes a fourteenth transistor B, a gate of the fourteenth transistor B is coupled to the second power supply terminal, and a first electrode and a second electrode of the fourteenth transistor B are coupled to the third power supply terminal and the first pull-down node respectively.

5. The shift register according to any one of claims 1 to 4, characterized in that: The output module includes a third transistor and a bootstrap capacitor, the gate of the third transistor is coupled to the pull-up node, the first electrode of the third transistor is coupled to the clock signal terminal, the second electrode of the third transistor is coupled to the first signal output terminal, and the first electrode and the second electrode of the bootstrap capacitor are respectively coupled to the pull-up node and the first signal output terminal; The output pull-down module includes a thirteenth transistor A, a gate of the thirteenth transistor A is coupled to the first pull-down node, and a first electrode and a second electrode of the thirteenth transistor A are respectively coupled to the fourth power supply terminal and the first signal output terminal.

6. The shift register according to claim 5, characterized in that: The output pull-down module further includes a thirteenth transistor B, a gate of the thirteenth transistor B is coupled to the second pull-down node, and a first electrode and a second electrode of the thirteenth transistor B are respectively coupled to the fourth power supply terminal and the first signal output terminal.

7. The shift register according to claim 5, characterized in that: The output module further includes an eleventh transistor and a second signal output terminal, a gate of the eleventh transistor is coupled to the pull-up node, a first electrode of the eleventh transistor is coupled to the clock signal terminal, and a second electrode of the eleventh transistor is coupled to the second signal output terminal; The output pull-down module further includes a twelfth transistor A, a gate of the twelfth transistor A is coupled to the first pull-down node, a first electrode of the twelfth transistor A is coupled to the third power supply terminal, and a second electrode of the twelfth transistor A is coupled to the second signal output terminal; The output pull-down module also includes a twelfth transistor B, a gate of the twelfth transistor B is coupled to the second pull-down node, a first electrode of the twelfth transistor B is coupled to the third power supply terminal, and a second electrode of the twelfth transistor B is coupled to the second signal output terminal.

8. The shift register according to claim 1, characterized in that: It also includes a reset module, which is coupled to the reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the reset signal terminal.

9. The shift register according to claim 1, characterized in that: In the display stage of the display device, the signals at the third power end and the fourth power end are the same. In the shutdown stage of the display device, the signal at the fourth power end is the same as the signal at the first power end.

10. A shift register driving method, characterized in that: Applied to the shift register according to any one of claims 1 to 9, the method comprising: In the first stage, the signal input terminal provides a high-level signal, and the input module provides a high-level signal to the pull-up node under the control of the signal input terminal; the first pull-down module provides a signal from the third power supply terminal to the first pull-down node under the control of the signal input terminal and / or the pull-up node; the first node control module provides a signal from the third power supply terminal to the second pull-down node under the control of the first power supply terminal, so that the second pull-down node is pulled down to the potential of the third power supply terminal; the output module provides a signal from the clock signal terminal to the first signal output terminal under the control of the pull-up node; In the second stage, the clock signal terminal provides a high level signal, so that the first signal output terminal outputs a high level signal.

11. A gate drive circuit, characterized in that: A shift register comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 9.

12. A display device, characterized in that: A shift register comprising any one of claims 1 to 9 or a gate drive circuit comprising claim 11.

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