A driving circuit, a driving method and a display device of a display panel

Abstract

This invention discloses a driving circuit, driving method, and display device for a display panel. In the driving circuit, for each group of Gate Array (GOA) units, based on any column of pixels with the largest total number of positive and negative polarities, N GOA units are connected in driving order to the gate lines of pixels defined as having a first polarity and to the gate lines of pixels defined as having a second polarity, so that pixels with the same defined polarity are driven adjacently. The first and second polarities are either positive or negative, and are different polarities. When the N GOA units sequentially output gate driving signals, multiple data lines are configured to output data signals with polarities matching the gate driving signals, ensuring that pixels with the same defined polarity are charged adjacently. This invention can reduce the overall power consumption of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit and a driving method of a display panel and a display device. Background Art

[0002] Dual Gate products can reduce the number of data lines, thereby reducing the number of source driver chips, which can significantly reduce costs and improve product competitiveness. However, according to the existing Dual Gate pixel driving method, it is difficult to further reduce power consumption during the driving process. Summary of the invention

[0003] In view of the above problems, the present invention provides a driving circuit, a driving method and a display device of a display panel, which can reduce the overall power consumption of the display panel.

[0004] In the first aspect, the present application provides the following technical solution through an embodiment:

[0005] A driving circuit for a display panel, comprising: a plurality of data lines and a plurality of GOA unit groups, each of the GOA unit groups comprising N GOA units arranged in sequence, N being the number of clock signals, N being the number of clock signal lines, and N being an even number greater than or equal to 6;

[0006] For each GOA unit group, taking any column of pixels defined as having the largest total number of positive polarities and negative polarities as a reference, the N GOA units are respectively connected to the gate lines of the pixels defined as the first polarity and the gate lines of the pixels defined as the second polarity in a driving order, so that the driving order of the pixels defined as having the same polarity is adjacent, the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities;

[0007] Among them, when the N GOA units output gate drive signals in sequence, the multiple data lines are configured to output data signals whose polarities match the gate drive signals, so that the charging order of pixels with the same polarity is defined to be adjacent.

[0008] Optionally, the polarity inversion mode of the display panel is 2-pixel point inversion;

[0009] The N GOA units correspond to N gate lines arranged in sequence, the N gate lines include a first gate line group, a second gate line group, a third gate line group and a fourth gate line group; the first gate line group includes the 4*K1+1th gate line of the N gate lines, the second gate line group includes the 4*K2+2th gate line of the N gate lines, the third gate line group includes the 4*K3+3th gate line of the N gate lines, and the fourth gate line group includes the 4*K4+4th gate line of the N gate lines, wherein K1, K2, K3 and K4 are all natural numbers, and 4*K1+1, 4*K2+2, 4*K3+3 and 4*K+4 are not greater than N, and K1, K2, K3 and K4 are taken from small to large in sequence;

[0010] The N GOA units are sequentially connected to each gate line in the first gate line group, each gate line in the second gate line group, each gate line in the third gate line group, and each gate line in the fourth gate line group.

[0011] Optionally, when the value of N is 8, the connection order of the N GOA units and the N gate lines is:

[0012] The 1st GOA unit is connected to the 1st gate line, the 2nd GOA unit is connected to the 5th gate line, the 3rd GOA unit is connected to the 2nd gate line, the 4th GOA unit is connected to the 6th gate line, the 5th GOA unit is connected to the 3rd gate line, the 6th GOA unit is connected to the 7th gate line, the 7th GOA unit is connected to the 4th gate line, and the 8th GOA unit is connected to the 8th gate line.

[0013] In the second aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0014] A display panel driving method, used for driving a display panel; the display panel comprises a plurality of groups of gate lines and a plurality of data lines, each group of gate lines comprises N gate lines arranged in sequence, N is the number of clock signals, N is the number of clock signal lines, and N is an even number greater than or equal to 6;

[0015] For each group of gate lines, taking any column of pixels defined as positive polarity and pixels defined as negative polarity with the largest total number as a reference, the driving method includes:

[0016] Outputting gate drive signals to the N gate lines to sequentially drive the pixel points defined as a first polarity in the column of pixel points, and sequentially driving the pixel points defined as a second polarity in the column of pixel points after the driving of the pixel points of the first polarity is completed; the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities;

[0017] For each of the gate lines, based on the gate driving signal, a data signal having a polarity matching the gate driving signal is output to the data line, so that the charging sequence of pixels with the same defined polarity is adjacent.

[0018] Optionally, the polarity inversion mode of the display panel is 2-pixel point inversion; the N gate lines include a first gate line group, a second gate line group, a third gate line group and a fourth gate line group; the first gate line group includes the 4*K1+1th of the N gate lines, the second gate line group includes the 4*K2+2th of the N gate lines, the third gate line group includes the 4*K3+3th of the N gate lines, and the fourth gate line group includes the 4*K4+4th of the N gate lines, wherein K1, K2, K3 and K4 are all natural numbers, and 4*K1+1, 4*K2+2, 4*K3+3 and 4*K+4 are not greater than N, and K1, K2, K3 and K4 are taken in ascending order;

[0019] The outputting gate driving signals to the N gate lines comprises:

[0020] The gate driving signal is output to the N gate lines in the order of the first gate line group, the second gate line group, the third gate line group, and the fourth gate line group.

[0021] Optionally, when the value of N is 8, the outputting gate driving signals to the N gate lines includes:

[0022] The gate driving signals are output to the eight gate lines in the order of the first gate line, the fifth gate line, the second gate line, the sixth gate line, the third gate line, the seventh gate line, the fourth gate line, and the eighth gate line.

[0023] Optionally, when the value of N is 6, outputting a gate driving signal to the N gate lines includes:

[0024] The gate driving signals are output to the six gate lines in the order of the first gate line, the fifth gate line, the second gate line, the sixth gate line, the third gate line, and the fourth gate line.

[0025] Optionally, when the value of N is 16, outputting a gate driving signal to the N gate lines includes:

[0026] The gate driving signals are output to the 16 gate lines in the order of the 1st gate line, the 5th gate line, the 9th gate line, the 13th gate line, the 2nd gate line, the 6th gate line, the 10th gate line, the 14th gate line, the 3rd gate line, the 7th gate line, the 11th gate line, the 15th gate line, the 4th gate line, the 8th gate line, the 12th gate line and the 16th gate line.

[0027] In the third aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0028] A driving circuit of a display panel, comprising a timing controller, a source driver and a gate driver, wherein the source driver and the gate driver are both connected to the timing controller; the display panel comprises a plurality of groups of gate lines and a plurality of data lines, each group of the gate lines comprises N gate lines arranged in sequence, N is the number of clock signals, N is the number of clock signal lines, and N is an even number greater than or equal to 6;

[0029] For each group of gate lines, the pixel column with the largest number of pixels defined as positive polarity and pixels defined as negative polarity is used as the benchmark:

[0030] The timing controller is used to control the gate driver to output gate drive signals to the N gate lines, so as to sequentially drive the pixel points defined as a first polarity in the column of pixel points, and after the pixel points of the first polarity are driven, sequentially drive the pixel points defined as a second polarity in the column of pixel points; the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities;

[0031] For each of the gate lines, the timing controller is used to control the source driver to output a data signal whose polarity matches the gate drive signal to the data line based on the gate drive signal, so that the charging order of pixels with the same defined polarity is adjacent.

[0032] In the fourth aspect, based on the same inventive concept, the present application provides the following technical solution through an embodiment:

[0033] A display device comprises the driving circuit of the display panel as described in any one of the first aspect and the third aspect.

[0034] The driving circuit of the display panel in the embodiment of the present invention ensures that when N GOA units output gate driving signals in sequence, multiple data lines are configured to output data signals matching the gate driving signals through the connection between the GOA units and the gate lines, so that the charging order of pixels with the same polarity defined is adjacent; thereby ensuring that the opening order of pixels with the same polarity is adjacent, and the pixel points of another polarity will not be turned on until the pixel points of one polarity are fully turned on. In this process, the number of reversals of the polarity of the data signal is greatly reduced, which can significantly reduce the power consumption of the display panel using the driving circuit.

[0035] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0037] Figure 1 A schematic structural diagram of a driving circuit of a first display panel in an embodiment of the present invention is shown;

[0038] Figure 2 A schematic diagram showing wiring between a GOA unit and a gate line of a display panel in an embodiment of the present invention is shown;

[0039] Figure 3 A schematic diagram showing a comparison of the data signal polarity change timings of the present solution and the prior solution under a white / grayscale screen of the first pixel architecture in an embodiment of the present invention;

[0040] Figure 4 A schematic diagram showing a comparison of the data signal polarity change timing of the present solution and the existing solution under the YCM mixed color screen of the first pixel architecture in the embodiment of the present invention;

[0041] Figure 5 A schematic diagram showing a comparison of the data signal polarity change timings of the present solution and the prior solution under the RGB monochrome screen of the first pixel architecture in the embodiment of the present invention;

[0042] Figure 6 A schematic diagram showing the principle of the effect of sequentially turning on adjacent gate lines on the voltage of a pixel point in an embodiment of the present invention;

[0043] Figure 7 A timing diagram of pulse signals corresponding to some gate lines under an 8CLK clock signal in an embodiment of the present invention is shown;

[0044] Figure 8 A schematic diagram comparing the pixel charging effects of the present solution and the existing solution in an embodiment of the present invention is shown;

[0045] Fig. 9 A schematic diagram showing a comparison of the data signal polarity change timings of the present solution and the prior solution under a white / grayscale screen of the second pixel architecture in an embodiment of the present invention;

[0046] Fig.10 A schematic diagram showing a comparison of the data signal polarity change timing of the present solution and the existing solution under the YCM mixed color screen of the second pixel architecture in the embodiment of the present invention;

[0047] Fig.11 A schematic diagram showing a comparison of the timing of data signal polarity changes between the present solution and the prior solution under the RGB monochrome screen of the second pixel architecture in the embodiment of the present invention;

[0048] Fig.12 A flow chart of a method for driving a display panel according to an embodiment of the present invention is shown;

[0049] Fig.13 A schematic structural diagram of a driving circuit of a second display panel in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0050] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0051] See also Figure 1In one embodiment of the present invention, a driving circuit 100 for a display panel is provided, which can be used to drive a display panel 200. The driving circuit 100 includes: a plurality of data lines 111 and a plurality of GOA (Gate Driver on Array, array substrate gate drive) unit groups, each of the GOA unit groups includes N GOA units arranged in sequence, N is the number of clock signal lines, and N is an even number greater than or equal to 6. The plurality of data lines 111 are used to transmit data signals, which can be generated by a source driver; the plurality of GOA unit groups 121 can be used to generate a gate drive signal to turn on or off the pixels of the corresponding rows. Each row of pixels of the same color can be connected by the same gate line 122, and the gate drive signal transmitted by the gate line 122 can turn these pixels on or off.

[0052] In this embodiment, the pixel point of the display panel is the smallest unit of light-emitting point. For example, a pixel (Pixel) is composed of three monochrome light-emitting units of red (R), green (G) and blue (B), and the pixel point is these monochrome light-emitting units of red, green and blue. When the display panel displays a picture, each pixel point therein has a corresponding polarity, and the polarity of these pixel points is defined by the display panel type or pre-designed specifications. For example, in a display panel with 2dot (pixel point) inversion, the polarity repetition method defined for the pixel points in a certain column can be: ++--++--.

[0053] Furthermore, N GOA units can be used to receive N clock signals respectively. Since there is a cascade relationship between multiple GOA unit groups, multiple GOA unit groups can transmit gate drive signals to corresponding gate lines in turn under the control of a scan start signal (STV); it can be understood that after one GOA unit group completes scanning, the next GOA unit group starts scanning, and so on; of course, this is only an example and is not limited to this.

[0054] For any GOA unit group, the pulse sequence of the gate drive signal output by the N GOA units can be arranged in sequence; that is, the pulse timing of the 1st GOA unit to the Nth GOA unit is arranged from first to last. In the present embodiment, no matter which frame of image the display panel refreshes, its image composition is composed of a white / grayscale image, a YCM (yellow, cyan, magenta) mixed color image and an RGB monochrome image. Therefore, in the present embodiment, based on the characteristics of the polarity distribution of the pixel points, the GOA unit is connected to the gate line. Specifically, taking any column of pixels defined as having the largest total number of positive and negative polarities as a reference (which can be any frame of image), the N GOA units are connected to the gate lines of the pixels defined as the first polarity and the gate lines of the pixels defined as the second polarity in a driving order, so that the driving order of the pixels defined with the same polarity is adjacent. Among them, the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities. For example, in Figure 2 In the figure, the column of pixels defined as having the largest total number of positive and negative polarities is the pixel points corresponding to any column of data lines S1, S2, S4, and S5. The total number of positive and negative polarities defined in each column is 4, and the number of positive and negative polarity pixels defined corresponding to data lines S3 and S6 is 0.

[0055] Such a connection method can ensure that when N GOA units output gate drive signals in sequence, multiple data lines are configured to output data signals that match the gate drive signals, so that the charging order of pixels with the same polarity is defined to be adjacent. In other words, since the opening order of pixels with the same polarity is adjacent, the pixels of another polarity will be turned on only after the pixels of one polarity are fully turned on. In this process, the polarity of the data signal only needs to be reversed once. Therefore, this connection structure can greatly reduce the number of polarity jumps of the data signal, and can significantly reduce the power consumption of the display panel using the drive circuit.

[0056] In some display panels with a polarity inversion mode of 2dot inversion (two-point liquid crystal inversion), N GOA units in a GOA unit group correspond to N gate lines. The N gate lines include a first gate line group, a second gate line group, a third gate line group, and a fourth gate line group. The first gate line group includes the 4*K1+1th gate line of the N gate lines, the second gate line group includes the 4*K2+2th gate line of the N gate lines, the third gate line group includes the 4*K3+3th gate line of the N gate lines, and the fourth gate line group includes the 4*K4+4th gate line of the N gate lines, wherein K1, K2, K3, and K4 are all natural numbers, and 4*K1+1, 4*K2+2, 4*K3+3, and 4*K+4 are not greater than N, and K1, K2, K3, and K4 are taken from small to large in sequence; that is, the gate lines in each gate line group are arranged in order from small to large. To ensure that the driving order of pixels with the same defined polarity can be adjacent when a GOA group is scanned, N GOA units are sequentially connected to each gate line in the first gate line group, each gate line in the second gate line group, each gate line in the third gate line group, and each gate line in the fourth gate line group.

[0057] It can be understood that the connection method can be adjusted accordingly in display panels with other types of inversion methods. For example, in a 4dot inversion display panel, N gate lines are divided into 8 groups; the first gate line group is the 8*K1+1th gate line among the N gate lines, the second gate line group includes the 8*K2+2th gate line among the N gate lines, the third gate line group includes the 8*K3+3th gate line among the N gate lines, and so on; the eighth gate line group includes the 8*K8+8th gate line among the N gate lines, where K1, K2, K3, K4, ···, K8 are all natural numbers, and 4*K1+1, 4*K2+2, 4*K3+3, 4*K+4, ···, 8*K8+8 are all not greater than N, and K1, K2, K3, ···, K8 take values ​​from small to large.

[0058] In some implementations, when N is 8, the clock signal corresponding to driving the display panel is a GOA architecture of 8CLK. Figure 2 , taking the Dual Gate Colum (a dual gate drive architecture) architecture as an example, in this pixel architecture, in the first row of pixels, the red pixels are connected to the gate lines in the order of G1, G2, G1, G2, in turn; the green pixels are connected to the gate lines in the order of G2, G1, G2, G1, in turn; the blue pixels are connected to the gate lines in the order of G1, G2, G1, G2, such as Figure 2 At this time, the connection sequence of N GOA units and N gate lines is as follows:

[0059] The first GOA unit (GOA1) is connected to the first gate line (G1), the second GOA unit (GOA2) is connected to the fifth gate line (G5), the third GOA unit (GOA3) is connected to the second gate line (G2), the fourth GOA unit (GOA4) is connected to the sixth gate line (G6), the fifth GOA unit (GOA5) is connected to the third gate line (G3), the sixth GOA unit (GOA6) is connected to the seventh gate line (G7), the seventh GOA unit (GOA7) is connected to the fourth gate line (G4), and the eighth GOA unit (GOA8) is connected to the eighth gate line (G8), as shown in FIG. Figure 2 shown.

[0060] When driving, the opening order of the 8 GOA units is from the 1st GOA unit to the 8th GOA unit, that is, Figure 2 GOA1 to GOA8 shown in the figure are turned on in sequence; at this time, the corresponding gate line turning on sequence is: the 1st gate line, the 5th gate line, the 2nd gate line, the 6th gate line, the 3rd gate line, the 7th gate line, the 4th gate line, the 8th gate line, that is, Figure 2 G1, G5, G2, G6, G3, G7, G4, and G8 shown in the figure are turned on in sequence; thereby, the driving order of the pixels with the same defined polarity is adjacent, and therefore, the number of polarity changes of the data signal transmitted by the data line can be reduced.

[0061] For ease of understanding, the following uses different display screen examples to illustrate the beneficial effects of the solution of this embodiment:

[0062] See also Figure 3(a), when the display panel displays a white / grayscale image, when driven according to the existing circuit structure, GOA1 is connected to G1, GOA2 is connected to G2, GOA3 is connected to G3, GOA4 is connected to G4, GOA5 is connected to G5, GOA6 is connected to G6, GOA7 is connected to G7, and GOA8 is connected to G8; when each GOA unit is turned on in sequence, GOA1 and GOA2 are turned on in sequence first, and since the polarity of the defined pixel point is positive, the data line S1 is a data signal of positive polarity at this time; then GOA3 and GOA4 are turned on in sequence, and since the polarity of the defined pixel point is negative, the data line S1 is a data signal of negative polarity at this time; the data signal of the data line S1 needs to be reversed once to change from positive polarity to negative polarity; by analogy, when GOA5 and GOA6 are turned on, the polarity of the data signal of the data line S1 will be reversed once again to become positive polarity; when GOA7 and GOA8 are turned on, the polarity of the data signal of the data line S1 will be reversed once again to become negative polarity. That is to say, during the driving process, the polarity timing change of the data signal of the data line S1 can be expressed as: ++--++--; the polarity timing change of the data signal of the data line S2 can be expressed as: --++--++, such as Figure 3 (c) as shown.

[0063] When driven according to the driving circuit of the display panel in this embodiment, when each GOA unit is turned on in sequence, when GOA1, GOA2, GOA3 and GOA4 are turned on in sequence, since the gate lines connected thereto are G1, G5, G2 and G6 respectively; and the pixels corresponding to the four gate lines and the data line S1 are all defined as positive polarity; therefore, when GOA1, GOA2, GOA3 and GOA4 are turned on, the data signal of the data line S1 does not need to be inverted; similarly, when GOA5, GOA6, GOA7 and GOA8 are turned on, since the gate lines connected thereto are G3, G7, G4 and G8 respectively, the pixels corresponding to the four gate lines and the data line S1 are all defined as negative polarity, and the data signal of the data line S1 does not need to be inverted; in the process of turning on these eight GOA units, polarity inversion will occur only between the last GOA unit of the previous group and GOA1 of the current group, and polarity inversion will occur between GOA4 and GOA5. The polarity timing change of the data signal of the data line S1 can be expressed as: ++++----; the polarity timing change of the data signal of the data line S2 can be expressed as: ----++++, such as Figure 3 (b) shows. That is to say, during the driving process, the polarity reversal effect of the data signal of the data lines S1 and S2 is equivalent to a 4-dot reversal, and the reversal frequency can be reduced by 50% compared with the 2-dot reversal of the data signal in the prior art. Based on the power consumption formula Power = ∑ n f source *C*(V H―V L ) 2 , it can be determined that the power consumption of the source driver can be significantly reduced by 50%, where Power is the power consumption of the source driver, f source is the polarity reversal frequency of the data signal, C is the storage capacitor capacity of the pixel, V H is the voltage with positive polarity of data signal, V L The voltage of the data signal has a negative polarity.

[0064] See also Figure 4 (a), when the YCM mixed color screen of the display panel is driven according to the existing circuit structure, when GOA1~GOA8 are turned on in sequence, that is, G1, G2, G3, G4, G5, G6, G7, G8 are turned on in sequence, and the corresponding pixels. For data line S1, the timing change of the polarity of the data signal can be expressed as: ++--++--; for data line S2, the timing change of the polarity of the data signal can be expressed as: 0-0+0-0+; for data line S3, the timing change of the polarity of the data signal can be expressed as: +0-0+0-0, such as Figure 4 (c) as shown.

[0065] If the driving circuit in this embodiment is used for driving, when GOA1 to GOA8 are turned on in sequence, the pixels corresponding to G1, G5, G2, G6, G3, G7, G4, and G8 are turned on in sequence. For data line S1, the timing change of the polarity of the data signal can be expressed as: ++++----; for data line S2, the timing change of the polarity of the data signal can be expressed as: 00--00++; for data line S3, the timing change of the polarity of the data signal can be expressed as: ++00—00, such as Figure 4 As shown in (b). It can be seen that after the circuit structure in this embodiment is used to realize driving, the number of polarity reversals of the data signal transmitted by the data line is also significantly reduced. Based on the power consumption formula Power = ∑ n f source *C*(V H ―V L ) 2 By calculation, it can be determined that the power consumption of the source driver can also be significantly reduced by 50%.

[0066] See also Figure 5(a), when the panel displays RGB monochrome images, it is driven according to the existing circuit structure. When GOA1 to GOA8 are turned on in sequence, G1, G2, G3, G4, G5, G6, G7, and G8 are turned on in sequence, and the corresponding pixels are turned on in sequence. For data line S1, the timing change of the polarity of the data signal can be expressed as: +0-0+0-0; for data line S2, the timing change of the polarity of the data signal can be expressed as: 0-0+0-0+; for data line S3, the timing change of the polarity of the data signal can be expressed as: 00000000, such as Figure 5 (c) as shown.

[0067] If the circuit structure in this embodiment is used for driving, when GOA1 to GOA8 are turned on in sequence, the pixels corresponding to G1, G5, G2, G6, G3, G7, G4, and G8 are turned on in sequence. For data line S1, the timing change of the polarity of the data signal can be expressed as: ++00--00; for data line S2, the timing change of the polarity of the data signal can be expressed as: 00--00++; for data line S3, the timing change of the polarity of the data signal can be expressed as: 00000000, such as Figure 5 As shown in (b). It can be seen that after the circuit structure in this embodiment is used to realize driving, the number of polarity reversals of the data signal transmitted by the data line is also significantly reduced. Based on the power consumption formula Power = ∑ n f source *C*(V H ―V L ) 2 Calculation shows that the power consumption of the source driver can also be significantly reduced by 33%.

[0068] Moreover, in the RGB monochrome screen, the gate lines are driven in the order of G1, G5, G2, G6, G3, G7, G4, G8 after the circuit structure is adjusted, so that the gate lines are not turned on sequentially. Therefore, the problem of some pixels being affected by parasitic capacitance (C gp ) coupling is different, resulting in poor image quality, such as vertical stripes on the screen.

[0069] See also Figure 6 According to the existing method, when G1 to G8 are driven in sequence, taking the pixel point R1 corresponding to G1S1 as an example, after the pixel point R1 is charged, G1 is turned off because there is a parasitic capacitance C between G1 and the pixel point R1 during the charging process. gp 1, so that the electrode of the pixel point R1 is pulled by coupling to produce the first voltage deviation △Vp. After 1H time (the length of time to scan a line), G2 is turned off. At this time, there is a parasitic capacitance C between G2 and the pixel point R1. gp2, will be affected by the voltage deviation △Vp again. For the pixel R2 corresponding to G1S2, since G1 is turned off first and G2 is turned off later, the pixel R2 is only affected by the parasitic capacitance C when G2 is turned off. gp 2, resulting in a voltage deviation △Vp, such as Figure 6 In other words, during the charging process of pixel S1, it will be affected by the opening of G1 and G2, but during the charging process of pixel S2, it will only be affected by the opening of G2 (the C corresponding to data line S2). gp 1 will not be affected), pixel R1 and pixel R2 are affected differently, resulting in different charging voltages. In other words, the two columns of red pixels corresponding to data line S1 and data line S2 will have brightness differences, resulting in vertical stripes on the red screen. Similarly, it can be seen that the same problem exists for green and blue pixels, so vertical stripes will also appear when displaying green or red images.

[0070] In this embodiment, the driving sequence is G1, G5, G2, G6, G3, G7, G4, G8. Figure 7 As shown. When G1 is turned on, only the pixel R1 is charged. When G1 is turned off, the pixel R1 is pulled, resulting in a voltage deviation △Vp. When G5 is turned on for pre-charging, since G5 and G1 are separated by G2, G3, and G4, the turning on and off of G5 will not have any effect on the charging process of the pixel R1. When G2 is turned on, the pixel R1 has completed the charging process, and G1 is turned off and will not be affected by G1. In other words, the pixel R2 is only pulled to produce a voltage deviation △Vp when G2 is turned off. As a result, the amount of influence of the gate line on the pixel R1 and the pixel R2 is the same, which avoids charging differences, can better improve the picture quality, and suppress vertical stripes.

[0071] Furthermore, the driving circuit in this embodiment greatly reduces the number of inversions of the data signal due to the influence of the charging sequence, and the gate line is turned on for alternate lines, especially for the YCM mixed color screen, which increases the pre-charging time and charging rate of some pixels, reduces the charging difference between adjacent columns under the screen, and improves the image quality. Figure 8 (a), where O is good charging, △ is charging, X is poor charging, and X↓ indicates poor charging and low due to parasitic capacitance. When charging with the existing solution, the parasitic capacitance C caused by the driving sequence gp The influence of polarity reversal causes the red pixels in the first column to have a charging difference with the required standard voltage, and is also affected by the parasitic capacitance C gpSimilarly, the green pixels in the fifth column also have a charging difference with the required standard voltage, and are also affected by the parasitic capacitance and are low. When the driving circuit of this embodiment is adopted, the number of data signal inversions is reduced, the charging rate can be significantly improved, and the adverse effects caused by the parasitic capacitance can be avoided; Figure 8 As shown in (b), the adverse effects caused by parasitic capacitance are eliminated, and at the same time, the number of pixels in the first and fifth columns that are in a charge difference state is reduced by half.

[0072] See also Fig. 9 , taking the display panel of Dual Gate Colum2 (a dual gate drive architecture) architecture as an example, under this pixel architecture, in the first row of pixels, red pixels are connected to G1 when connected to the gate line; green pixels are connected to G2 ring when connected to the gate line; blue pixels are connected to the gate line in the order of G2, G1, G2, G1, such as Fig. 9 At this time, the connection sequence of N GOA units and N gate lines is the same as the display panel example of the Dual Gate Colum architecture described above, and will not be repeated. Similarly, different display screens are used for explanation, as follows:

[0073] Please continue reading Fig. 9 , when the display panel displays a white / grayscale image, it is driven according to the existing circuit structure. When GOA1 to GOA8 are turned on in sequence, the polarity timing change of the data signal of data line S1 can be expressed as: ++--++--; the polarity timing change of the data signal of data line S2 can be expressed as: --++--++. When driven according to the driving circuit of the display panel in this embodiment, the polarity timing change of the data signal of data line S1 can be expressed as: ++++----; the polarity timing change of the data signal of data line S2 can be expressed as: ----++++. Based on the power consumption formula Power = ∑ n f source *C*(V H ―V L ) 2 , it can be determined that the power consumption of the source driver can be significantly reduced by up to 50%.

[0074] See also Fig.10, when the YCM mixed color screen of the display panel is driven according to the existing circuit structure, when GOA1~GOA8 are turned on in sequence, for the data line S1, the timing change of the polarity of the data signal can be expressed as: ++--++--; for the data line S2, the timing change of the polarity of the data signal can be expressed as: -0+0-0+0; for the data line S3, the timing change of the polarity of the data signal can be expressed as: 0+0-0+0-. When driven according to the driving circuit in this embodiment, for the data line S1, the timing change of the polarity of the data signal can be expressed as: ++++----; for the data line S2, the timing change of the polarity of the data signal can be expressed as: -00++00; for the data line S3, the timing change of the polarity of the data signal can be expressed as: 00++00--. It can be seen that after the circuit structure in this embodiment is used to realize the drive, the number of polarity reversals of the data signal transmitted by the data line is also significantly reduced. Based on the power consumption formula Power=∑ n f source *C*(V H ―V L ) 2 By calculation, it can be determined that the power consumption of the source driver can also be significantly reduced by 50%.

[0075] See also Fig.11 , when the panel displays RGB monochrome images, it is driven according to the existing circuit structure. When GOA1~GOA8 are turned on in sequence, for data line S1, the timing change of the polarity of the data signal can be expressed as: +0-0+0-0; for data line S2, the timing change of the polarity of the data signal can be expressed as: -0+0-0+0; for data line S3, the timing change of the polarity of the data signal can be expressed as: 00000000. If driven according to the circuit structure in this embodiment, for data line S1, the timing change of the polarity of the data signal can be expressed as: ++00--00; for data line S2, the timing change of the polarity of the data signal can be expressed as: -00++00; for data line S3, the timing change of the polarity of the data signal can be expressed as: 00000000. Based on the power consumption formula Power=∑ n f source *C*(V H ―V L ) 2 Calculation shows that the power consumption of the source driver can also be significantly reduced by 33%.

[0076] Similarly, under the Dual Gate Colum2 architecture, the driving circuit can also suppress the vertical streak defects caused by parasitic capacitance and improve the charging rate. The relevant principles can be found in the above-mentioned Dual Gate Colum architecture example, which will not be repeated here.

[0077] In some implementations, when N is 16, that is, the clock signal corresponding to the display panel is driven by a GOA architecture of 16CLK. In this architecture, the connection sequence of N GOA units and N gate lines is as follows:

[0078] The 1st GOA unit is connected to the 1st gate line, the 2nd GOA unit is connected to the 5th gate line, the 3rd GOA unit is connected to the 9th gate line, the 4th GOA unit is connected to the 13th gate line, the 5th GOA unit is connected to the 2nd gate line, the 6th GOA unit is connected to the 6th gate line, the 7th GOA unit is connected to the 10th gate line, the 8th GOA unit is connected to the 14th gate line, the 9th GOA unit is connected to the 3rd gate line, the 10th GOA unit is connected to the 7th gate line, the 11th GOA unit is connected to the 11th gate line, the 12th GOA unit is connected to the 15th gate line, the 13th GOA unit is connected to the 4th gate line, the 14th GOA unit is connected to the 8th gate line, the 15th GOA unit is connected to the 12th gate line, and the 16th GOA unit is connected to the 16th gate line.

[0079] Through the above connection method, in a 2dot inversion display panel, when the source driver generates a data signal, an 8dot inversion effect can be achieved. For example, in a white / grayscale screen, when the existing solution is used for driving, the timing change of the polarity of the data signal of the data line S1 can be expressed as: ++--++--++--++--; when the driving circuit of this embodiment is used, the timing change of the polarity of the data signal of the data line S1 can be expressed as: ++++++++--------. The display panel with a 16CLK clock signal can further reduce power consumption by 50% compared to the 8CLK display panel in the aforementioned embodiment.

[0080] Similarly, in the 16CLK GOA architecture, the drive circuit can also suppress the vertical streak defects caused by parasitic capacitance and improve the charging rate. The relevant principles can be found in the above 8CLK GOA architecture example, which will not be repeated here.

[0081] It should also be noted that in some implementations, when implementing the driving circuit of the display panel in this embodiment, it is only necessary to adjust the wiring between the GOA unit and the gate line, which hardly causes an increase in manufacturing cost.

[0082] In summary, a driving circuit of a display panel provided in this embodiment changes the connection structure between the GOA unit and the gate line so that the charging order of pixels with the same polarity is defined to be adjacent. When multiple data lines transmit data signals matching the corresponding gate lines, the number of inversions of the data signal can be reduced, thereby effectively reducing the power consumption of the display panel.

[0083] Of course, in some embodiments, the same driving result as the driving circuit of the above embodiment can be achieved by controlling the order of outputting gate driving signals to the gate lines. Based on the same inventive concept, another embodiment of the present invention also provides a method for driving a display panel.

[0084] See also Fig.12 A display panel driving method provided in this embodiment can be used to drive a display panel; further, it can be applied to a display panel driving circuit. The display panel includes multiple groups of gate lines and multiple data lines, each group of gate lines includes N gate lines arranged in sequence, N is the number of clock signal lines, and N is an even number greater than or equal to 6.

[0085] For each group of gate lines, taking any column of pixels defined as positive polarity and pixels defined as negative polarity with the largest total number as a reference, the driving method includes:

[0086] Step S10: outputting gate drive signals to the N gate lines to sequentially drive the pixel points defined as a first polarity in the column of pixel points, and after the pixel points of the first polarity are driven, sequentially drive the pixel points defined as a second polarity in the column of pixel points; the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities;

[0087] Step S20: for each of the gate lines, based on the gate driving signal, outputting a data signal having a polarity matching the gate driving signal to the data line, so that the charging sequence of the pixels having the same defined polarity is adjacent.

[0088] It should be noted that the order of execution of step S10 and step S20 is not distinguished. Step S10 and step S20 cooperate with each other during the execution process. It can be understood that the N gate lines output gate drive signals according to a certain timing, and the gate drive signal can be a pulse. After any gate line outputs a drive signal, a data signal with a polarity matching the gate drive signal is also output to the data line accordingly. In other words, if the gate drive signal output of a gate line is executed in step S10, the corresponding data signal output is executed in step S20, and finally the charging order of the pixels with the same defined polarity is ensured to be adjacent. Thereby, the number of data signal inversions is reduced, and the power consumption of the display panel is reduced.

[0089] In some optional embodiments, the polarity inversion mode of the display panel may be a 2-pixel point inversion; the N gate lines include a first gate line group, a second gate line group, a third gate line group and a fourth gate line group; the first gate line group includes the 4*K1+1th gate line among the N gate lines, the second gate line group includes the 4*K2+2th gate line among the N gate lines, the third gate line group includes the 4*K3+3th gate line among the N gate lines, and the fourth gate line group includes the 4*K4+4th gate line among the N gate lines, wherein K1, K2, K3 and K4 are all natural numbers, and 4*K1+1, 4*K2+2, 4*K3+3 and 4*K+4 are all not greater than N, and K1, K2, K3 and K4 take values ​​from small to large.

[0090] At this time, step S10 may specifically include:

[0091] The gate driving signals are output to the N gate lines in the order of the first gate line group, the second gate line group, the third gate line group, and the fourth gate line group.

[0092] In some optional implementations, when N is 8, corresponding to the 8CLK GOA architecture, step S10 may specifically include:

[0093] The gate driving signals are output to the eight gate lines in the order of the first gate line, the fifth gate line, the second gate line, the sixth gate line, the third gate line, the seventh gate line, the fourth gate line, and the eighth gate line.

[0094] In some optional implementations, when the value of N is 6, corresponding to a 6CLK GOA architecture, step S10 may specifically include:

[0095] The gate driving signals are output to the six gate lines in the order of the first gate line, the fifth gate line, the second gate line, the sixth gate line, the third gate line, and the fourth gate line.

[0096] In some optional implementations, when the value of N is 16, corresponding to a 16CLK GOA architecture, step S10 specifically includes:

[0097] Gate driving signals are output to the 16 gate lines in the order of the 1st gate line, the 5th gate line, the 9th gate line, the 13th gate line, the 2nd gate line, the 6th gate line, the 10th gate line, the 14th gate line, the 3rd gate line, the 7th gate line, the 11th gate line, the 15th gate line, the 4th gate line, the 8th gate line, the 12th gate line and the 16th gate line.

[0098] It should be noted that the difference between the present embodiment and the aforementioned driving circuit embodiment is that the driving method in the present embodiment adjusts the timing of outputting pulses to the gate line, thereby changing the gate line opening timing, so as to reduce the number of data signal inversions of the data line. The method of adjusting the timing of outputting pulses to the gate line is not limited, and can be achieved by changing the connection method between the GOA unit and the gate line, such as the driving circuit structure in the aforementioned embodiment. The timing of outputting pulses to the gate line can also be adjusted by changing the pulse timing of the clock signal through the timing controller (TCON).

[0099] In addition, the beneficial effects and related principles of the display panel driving method in this embodiment can be found in the display panel driving circuit in the above-mentioned embodiment, which will not be described in detail here.

[0100] See also Fig.13 Based on the same inventive concept, in another embodiment of the present invention, a display panel driving circuit 300 is provided, which can be used to drive a display panel 500. The driving circuit includes a timing controller 310, a source driver 320 and a gate driver 330. The source driver 320 and the gate driver 330 are both connected to the timing controller 310. The display panel includes a plurality of groups of gate lines 331 and a plurality of data lines 321. Each group of gate lines 331 includes N gate lines 331 arranged in sequence, where N is the number of clock signal lines, and N is an even number greater than or equal to 6. For each group of gate lines 331, taking any column of pixels defined as positive polarity and defined as negative polarity with the largest total number as a reference:

[0101] The timing controller 310 is used to control the gate driver 330 to output a gate drive signal to the N gate lines 331, so as to sequentially drive the pixel points defined as the first polarity in the column of pixels, and after the pixel points of the first polarity are driven, sequentially drive the pixel points defined as the second polarity in the column of pixels; the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities; for each gate line 331, the timing controller 310 is used to control the source driver 320 to output a data signal whose polarity matches the gate drive signal to the data line 321 based on the gate drive signal, so that the charging order of the pixel points defined with the same polarity is adjacent.

[0102] It should be noted that the driving circuit 300 of a display panel provided in the embodiment of the present invention, wherein the timing controller 310, the gate driver 330 and the source driver 320, the working process of controlling the gate line 331 to be turned on or off, and the working process of controlling the data signal transmitted by the data line 321 are the same as those of the driving circuit 100 in the aforementioned embodiment. In addition, the technical effects produced are also the same as those of the aforementioned embodiment of the driving circuit 100. For the sake of brief description, for the parts not mentioned in this embodiment, reference may be made to the corresponding contents in the aforementioned embodiment of the driving circuit 100.

[0103] Based on the same inventive concept, a display device is provided in another embodiment of the present invention, including a driving circuit of the display panel described in any of the above embodiments. The display device in this embodiment may be a display panel, or a laptop computer, a television, a car display screen, etc. using the display panel. The display device in this embodiment includes the driving circuit in the above embodiments, and its beneficial effects can be found in the above driving circuit embodiments. For the sake of brief description, for matters not mentioned in the device embodiment, reference can be made to the corresponding contents in the above method embodiments.

[0104] The term "and / or" that appears in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship; the word "comprising" does not exclude the existence of elements or steps that are not listed in the claims. The word "one" or "an" placed before an element does not exclude the existence of multiple such elements. The present invention can be implemented with the aid of hardware including several different elements and with the aid of appropriately programmed computers. In a unit claim that lists several devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

[0105] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0106] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0107] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0108] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0109] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0110] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A driving circuit for a display panel, characterized in that: include: A plurality of data lines and a plurality of GOA unit groups, each of the GOA unit groups includes N GOA units arranged in sequence, N is the number of clock signal lines, and N is an even number greater than or equal to 6; For each of the GOA unit groups, taking any column of pixels defined as having the largest total number of positive polarities and negative polarities as a reference, the N GOA units are respectively connected to the gate lines of the pixels defined as the first polarity and the gate lines of the pixels defined as the second polarity in a driving order, so that the driving order of the pixels defined as having the same polarity is adjacent, the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities; Wherein, when the N GOA units sequentially output gate drive signals, the plurality of data lines are configured to output data signals whose polarities match the gate drive signals, so that the charging order of the pixels defined with the same polarity is adjacent; The N GOA units correspond to N gate lines arranged in sequence. When N is 8, the connection order of the N GOA units and the N gate lines is: the first GOA unit is connected to the first gate line, the second GOA unit is connected to the fifth gate line, the third GOA unit is connected to the second gate line, the fourth GOA unit is connected to the sixth gate line, the fifth GOA unit is connected to the third gate line, the sixth GOA unit is connected to the seventh gate line, the seventh GOA unit is connected to the fourth gate line, and the eighth GOA unit is connected to the eighth gate line; When the 1st GOA unit, the 2nd GOA unit, the 3rd GOA unit and the 4th GOA unit are turned on in sequence, the gate lines connected thereto are the 1st gate line, the 5th gate line, the 2nd gate line and the 6th gate line respectively, and the pixel points corresponding to these 4 gate lines and the data line (S1) are all defined as positive polarity.

2. The driving circuit according to claim 1, characterized in that: The polarity inversion mode of the display panel is 2-pixel point inversion; The N gate lines include a first gate line group, a second gate line group, a third gate line group and a fourth gate line group; the first gate line group includes the 4*K1+1th gate line of the N gate lines, the second gate line group includes the 4*K2+2th gate line of the N gate lines, the third gate line group includes the 4*K3+3th gate line of the N gate lines, and the fourth gate line group includes the 4*K4+4th gate line of the N gate lines, wherein K1, K2, K3 and K4 are all natural numbers, and 4*K1+1, 4*K2+2, 4*K3+3 and 4*K+4 are not greater than N, and K1, K2, K3 and K4 are taken in ascending order; The N GOA units are sequentially connected to each gate line in the first gate line group, each gate line in the second gate line group, each gate line in the third gate line group, and each gate line in the fourth gate line group.

3. A method for driving a display panel, characterized in that: Used to drive a display panel; the display panel includes a plurality of groups of gate lines and a plurality of data lines, each group of the gate lines includes N gate lines arranged in sequence, N is the number of clock signal lines, and N is an even number greater than or equal to 6; For each group of gate lines, taking any column of pixels defined as positive polarity and pixels defined as negative polarity with the largest total number as a reference, the driving method includes: Outputting gate drive signals to the N gate lines to sequentially drive the pixel points defined as a first polarity in the column of pixel points, and sequentially driving the pixel points defined as a second polarity in the column of pixel points after the driving of the pixel points of the first polarity is completed; the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities; For each of the gate lines, based on the gate drive signal, outputting a data signal having a polarity matching the gate drive signal to the data line, so that the charging sequence of the pixels having the same defined polarity is adjacent; The N GOA units correspond to N gate lines arranged in sequence. When N is 8, the connection order of the N GOA units and the N gate lines is: the first GOA unit is connected to the first gate line, the second GOA unit is connected to the fifth gate line, the third GOA unit is connected to the second gate line, the fourth GOA unit is connected to the sixth gate line, the fifth GOA unit is connected to the third gate line, the sixth GOA unit is connected to the seventh gate line, the seventh GOA unit is connected to the fourth gate line, and the eighth GOA unit is connected to the eighth gate line; When the 1st GOA unit, the 2nd GOA unit, the 3rd GOA unit and the 4th GOA unit are turned on in sequence, the gate lines connected thereto are the 1st gate line, the 5th gate line, the 2nd gate line and the 6th gate line respectively, and the pixel points corresponding to these 4 gate lines and the data line (S1) are all defined as positive polarity.

4. The driving method according to claim 3, characterized in that: The polarity inversion mode of the display panel is 2-pixel point inversion; the N gate lines include a first gate line group, a second gate line group, a third gate line group and a fourth gate line group; the first gate line group includes the 4*K1+1th gate line of the N gate lines, the second gate line group includes the 4*K2+2th gate line of the N gate lines, the third gate line group includes the 4*K3+3th gate line of the N gate lines, and the fourth gate line group includes the 4*K4+4th gate line of the N gate lines, wherein K1, K2, K3 and K4 are all natural numbers, and 4*K1+1, 4*K2+2, 4*K3+3 and 4*K+4 are not greater than N, and K1, K2, K3 and K4 are taken from small to large in sequence; The outputting gate driving signals to the N gate lines comprises: The gate driving signal is output to the N gate lines in the order of the first gate line group, the second gate line group, the third gate line group, and the fourth gate line group.

5. The driving method according to claim 4, characterized in that: When the value of N is 8, the outputting gate driving signals to the N gate lines includes: The gate driving signals are output to the eight gate lines in the order of the first gate line, the fifth gate line, the second gate line, the sixth gate line, the third gate line, the seventh gate line, the fourth gate line, and the eighth gate line.

6. The driving method according to claim 4, characterized in that: When the value of N is 6, the outputting gate driving signals to the N gate lines includes: The gate driving signals are output to the six gate lines in the order of the first gate line, the fifth gate line, the second gate line, the sixth gate line, the third gate line, and the fourth gate line.

7. The driving method according to claim 4, characterized in that: When the value of N is 16, the outputting gate driving signals to the N gate lines includes: The gate driving signals are output to the 16 gate lines in the order of the 1st gate line, the 5th gate line, the 9th gate line, the 13th gate line, the 2nd gate line, the 6th gate line, the 10th gate line, the 14th gate line, the 3rd gate line, the 7th gate line, the 11th gate line, the 15th gate line, the 4th gate line, the 8th gate line, the 12th gate line and the 16th gate line.

8. A driving circuit for a display panel, characterized in that: The display panel comprises a timing controller, a source driver and a gate driver, wherein the source driver and the gate driver are both connected to the timing controller; the display panel comprises a plurality of groups of gate lines and a plurality of data lines, each group of the gate lines comprises N gate lines arranged in sequence, where N is the number of clock signal lines, and N is an even number greater than or equal to 6; For each group of gate lines, the pixel column with the largest number of pixels defined as positive polarity and pixels defined as negative polarity is used as the benchmark: The timing controller is used to control the gate driver to output gate drive signals to the N gate lines, so as to sequentially drive the pixel points defined as a first polarity in the column of pixel points, and after the pixel points of the first polarity are driven, sequentially drive the pixel points defined as a second polarity in the column of pixel points; the first polarity and the second polarity are either positive polarity or negative polarity, and the first polarity and the second polarity are different polarities; For each of the gate lines, the timing controller is used to control the source driver to output a data signal with a polarity matching the gate drive signal to the data line based on the gate drive signal, so that the charging sequence of the pixels with the same defined polarity is adjacent; The N GOA units correspond to N gate lines arranged in sequence. When N is 8, the connection order of the N GOA units and the N gate lines is: the first GOA unit is connected to the first gate line, the second GOA unit is connected to the fifth gate line, the third GOA unit is connected to the second gate line, the fourth GOA unit is connected to the sixth gate line, the fifth GOA unit is connected to the third gate line, the sixth GOA unit is connected to the seventh gate line, the seventh GOA unit is connected to the fourth gate line, and the eighth GOA unit is connected to the eighth gate line; When the 1st GOA unit, the 2nd GOA unit, the 3rd GOA unit and the 4th GOA unit are turned on in sequence, the gate lines connected thereto are the 1st gate line, the 5th gate line, the 2nd gate line and the 6th gate line respectively, and the pixel points corresponding to these 4 gate lines and the data line (S1) are all defined as positive polarity.

9. A display device, characterized in that: A driving circuit for a display panel comprising any one of claims 1-2 and claim 8.

Images