Memory driving circuit, driving method, memory and storage system

Abstract

An embodiment of the present disclosure provides a driving circuit of a memory, comprising: a first current mirror unit, at least two first switches, a voltage source, a second current mirror unit, a second switch and a charging unit, wherein the first current mirror unit generates an output current to the second current mirror unit based on a reference current transmitted by the voltage source during a period when the first switch is turned on; the second current mirror unit comprises: a first semiconductor circuit and a second semiconductor circuit; one end of the charging unit is respectively coupled to the second switch and the first end of the second semiconductor circuit, and the other end is coupled to the third end of the second semiconductor circuit, and during a period when the second switch is turned on, the charging unit is charged according to the output current so that the voltage of the first end of the second semiconductor circuit is equal to the voltage of the first end of the first semiconductor circuit; the charging unit is discharged during a period when the second switch is turned off to maintain the voltage of the first end of the second semiconductor circuit unchanged; and the second semiconductor circuit outputs a driving current to the memory unit during a period when the first switch and the second switch are turned off.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a drive circuit and a drive method of a memory, a memory, and a storage system. Background Art

[0002] For a current-driven storage array, when implementing a read, program or erase operation, a drive current generating circuit needs to generate a drive current and transmit it to the storage unit. The drive current generating circuit has a problem of high power consumption during use. Summary of the invention

[0003] According to a first aspect of an embodiment of the present disclosure, a memory driving circuit is provided, comprising: a first current mirror unit, at least two first switches, a voltage source, a second current mirror unit, a second switch, and a charging unit; wherein,

[0004] The first current mirror unit has an input end coupled to the voltage source through a first first switch, an output end coupled to the input end of the second current mirror unit through a second first switch, and an output end of the second current mirror unit is used to couple to a storage unit;

[0005] The first current mirror unit is configured to generate an output current based on a reference current transmitted by the voltage source and transmit the output current to the second current mirror unit during a period in which a first first switch and a second first switch are turned on;

[0006] The second current mirror unit comprises: a first semiconductor circuit and a second semiconductor circuit; wherein a first end of the first semiconductor circuit is coupled to a first node of the second switch, a first end of the second semiconductor circuit is coupled to a second node of the second switch, a second end of the first semiconductor circuit is coupled to a second first switch, a second end of the second semiconductor circuit is coupled to the storage unit, and a third end of the first semiconductor circuit is coupled to a third end of the second semiconductor circuit;

[0007] The charging unit has one end coupled to the second switch and the first end of the second semiconductor circuit respectively, and the other end coupled to the third end of the second semiconductor circuit, and is configured to charge according to the output current during the conduction period of the second switch, so that the voltage of the first end of the second semiconductor circuit is equal to the voltage of the first end of the first semiconductor circuit;

[0008] The charging unit is further configured to discharge during the period when the second switch is turned off, so as to maintain the voltage of the first terminal of the second semiconductor circuit unchanged;

[0009] The second semiconductor circuit is configured to output a driving current when a first first switch, a second first switch, and the second switch are turned off; wherein the driving current is transmitted to the storage unit.

[0010] In some embodiments, the drive circuit of the memory further includes a first enable signal line, a second enable signal line and a drive control unit;

[0011] The first enable signal line is configured to transmit a first enable signal;

[0012] The second enable signal line is configured to transmit a second enable signal;

[0013] The first switch is coupled to the first enable signal line and is configured to be turned on when the first enable signal is at a high level and turned off when the first enable signal is at a low level;

[0014] The second switch is coupled to the second enable signal line and is configured to be turned on when the second enable signal is at a high level and turned off when the second enable signal is at a low level;

[0015] The drive control unit is coupled to the first enable signal line and the second enable signal line, respectively, and is configured to control the first enable signal line to transmit a first enable signal and control the second enable signal line to transmit a second enable signal according to a read operation instruction, a program operation instruction or an erase operation instruction.

[0016] In some embodiments, the first current mirror unit includes: a first current mirror and a second current mirror; wherein,

[0017] The first current mirror and the second current mirror have the same structure;

[0018] The input end of the first current mirror is coupled to the voltage source through the first first switch, the output end of the first current mirror is coupled to the input end of the second current mirror, and the output end of the second current mirror is coupled to the input end of the second current mirror unit through the second first switch.

[0019] In some embodiments, the drive circuit of the memory further includes: a third first switch, the first current mirror includes a first transistor and a second transistor, and the second current mirror includes a third transistor and a fourth transistor; wherein,

[0020] The gate of the first transistor is coupled to the gate of the second transistor, the source of the first transistor is coupled to the source of the second transistor, the gate of the first transistor is also coupled to the drain of the first transistor, the drain of the first transistor is coupled to the voltage source through the first first switch, and the drain of the second transistor is coupled to the drain of the third transistor through the third first switch;

[0021] The gate of the third transistor is coupled to the gate of the fourth transistor, the source of the third transistor is coupled to the source of the fourth transistor, the gate of the third transistor is also coupled to the drain of the third transistor, and the drain of the fourth transistor is coupled to a second first switch;

[0022] The first transistor and the second transistor include P-type transistors, and the third transistor and the fourth transistor include N-type transistors.

[0023] In some embodiments, the first semiconductor circuit includes a fifth transistor, and the second semiconductor circuit includes a sixth transistor; wherein,

[0024] The gate of the fifth transistor is coupled to the second switch, the drain of the fifth transistor is coupled to a second first switch, and the gate of the fifth transistor is also coupled to the drain of the fifth transistor;

[0025] The gate of the sixth transistor is coupled to the second switch, and the drain of the sixth transistor is used to couple to the storage unit;

[0026] A source of the fifth transistor is coupled to a source of the sixth transistor;

[0027] The fifth transistor and the sixth transistor include P-type transistors.

[0028] In some embodiments, the drive circuit of the memory further includes: a voltage follower and a fourth of the first switches; wherein,

[0029] The first input terminal of the voltage follower is coupled to the first terminal of the first semiconductor circuit, the second input terminal of the voltage follower is coupled to the output terminal of the voltage follower, the output terminal of the voltage follower is also coupled to the second switch, the first voltage terminal of the voltage follower is coupled to the positive voltage terminal through the fourth first switch, the voltage of the positive voltage terminal is greater than 0, the second voltage terminal of the voltage follower is coupled to the negative voltage terminal, the voltage of the negative voltage terminal is less than 0;

[0030] The voltage follower is configured to transmit the output current to the charging unit to charge the charging unit during the conduction period of the first first switch, the second first switch, the fourth first switch and the second switch.

[0031] In some embodiments, the charging unit includes: a capacitor; wherein,

[0032] The first plate of the capacitor is coupled to the second switch and the first end of the second semiconductor circuit respectively, and the second plate of the capacitor is coupled to the third end of the first semiconductor circuit and the third end of the second semiconductor circuit.

[0033] According to a second aspect of an embodiment of the present disclosure, a memory is provided, including:

[0034] A driving circuit of the memory according to the above embodiment; and

[0035] A plurality of storage units are coupled to the drive circuit of the memory and are configured to implement a read, program or erase operation according to a drive current output by the drive circuit of the memory.

[0036] According to a third aspect of an embodiment of the present disclosure, there is provided a storage system, including:

[0037] The memory according to the above embodiment; and

[0038] A memory controller, coupled to the memory, is configured to control the memory.

[0039] According to a fourth aspect of an embodiment of the present disclosure, a method for driving a memory is provided, the method being used to drive the memory as described in the above embodiment, the driving method comprising:

[0040] Controlling the first first switch and the second first switch to be turned on; wherein the voltage source is sequentially coupled to the first current mirror unit, the second first switch and the second current mirror unit through the first first switch;

[0041] During the conduction period of the first first switch and the second first switch, the first current mirror unit generates an output current based on the reference current transmitted by the voltage source and transmits the output current to the second current mirror unit;

[0042] Control the second switch to be turned on; wherein the second current mirror unit comprises: a first semiconductor circuit and a second semiconductor circuit, a first end of the first semiconductor circuit is coupled to a first node of the second switch, a first end of the second semiconductor circuit is coupled to a second node of the second switch, a second end of the first semiconductor circuit is coupled to a second first switch, a second end of the second semiconductor circuit is used to couple to a storage unit, and a third end of the first semiconductor circuit and a third end of the second semiconductor circuit are at the same potential;

[0043] During the conduction period of the second switch, the charging unit is charged according to the output current so that the voltage of the first terminal of the second semiconductor circuit is equal to the voltage of the first terminal of the first semiconductor circuit; wherein the charging unit has one end coupled to the second switch and the first end of the second semiconductor circuit respectively, and the other end coupled to the third end of the first semiconductor circuit and the third end of the second semiconductor circuit;

[0044] Controlling the second switch to turn off;

[0045] During the period when the second switch is turned off, the voltage at the first terminal of the second semiconductor circuit is maintained unchanged by discharging through the charging unit;

[0046] Controlling a first of the first switches and a second of the first switches to be turned off;

[0047] During the period when a first first switch, a second first switch, and the second switch are turned off, a driving current is output to the storage unit through the second semiconductor circuit.

[0048] In the embodiment of the present disclosure, a first switch, a second switch and a charging unit are provided in the driving circuit, and the working duration of the first current mirror unit and the second current mirror unit is controlled by the first switch and the second switch. When the first switch and the second switch are both turned on, the first current mirror unit and the second current mirror unit work, during which the charging unit is charged so that the first terminal voltage of the second semiconductor circuit in the second current mirror unit is equal to the first terminal voltage of the first semiconductor circuit in the second current mirror unit, so that the required driving current can be output to the storage unit through the second semiconductor circuit, thereby driving the storage unit to perform a read, program or erase operation. After the first terminal voltage of the second semiconductor circuit is equal to the first terminal voltage of the first semiconductor circuit, each switch in the driving circuit is turned off, and the first current mirror unit and the second current mirror unit stop working. The intermittent operation of the first current mirror unit and the second current mirror unit is realized by controlling the on and off of the first switch and the second switch, which is conducive to reducing the static power consumption of the driving circuit, and because the charging unit can be discharged during the switch off period to maintain the first terminal voltage of the second semiconductor circuit unchanged, the second semiconductor circuit can continuously and stably output the driving current to the storage unit to meet the driving current demand of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 is a schematic diagram of a driving current generating circuit according to an exemplary embodiment;

[0050] Figure 2 A schematic diagram of a driving current generating circuit of a memory according to an exemplary embodiment;

[0051] Figure 3 A schematic diagram of a driving circuit of a memory according to an embodiment of the present disclosure;

[0052] Figure 4 A timing diagram of an enable signal according to an embodiment of the present disclosure;

[0053] Figure 5 A schematic diagram of a driving circuit of another memory according to an embodiment of the present disclosure;

[0054] Figure 6 is a schematic diagram of a memory according to an exemplary embodiment;

[0055] Figure 7 is a schematic diagram of a memory system according to an exemplary embodiment;

[0056] Figure 8a is a schematic diagram of a memory card according to an exemplary embodiment;

[0057] Figure 8bis a schematic diagram of a solid state drive (SSD) according to an exemplary embodiment;

[0058] Fig. 9 The figure is a flowchart of a method for driving a memory according to an exemplary embodiment. DETAILED DESCRIPTION

[0059] The technical solution of the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments of the specification. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0060] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0061] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, but are not used to describe a specific order or sequence.

[0062] In the embodiments of the present disclosure, the term “A is in contact with B” includes the situation where A is in direct contact with B, or the situation where A is in indirect contact with B with other components interposed between A and B.

[0063] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. Furthermore, a layer may include multiple sublayers.

[0064] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning of “on” something with intervening features or layers.

[0065] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0066] A drive current generating circuit is used in a semiconductor integrated circuit to generate a constant drive current. In a semiconductor integrated circuit using a drive current generating circuit, the operating accuracy of the semiconductor integrated circuit depends on the ability of the drive current generating circuit to provide a constant drive current. For example, the smaller the change in the drive current provided by the drive current generating circuit, the higher the operating accuracy of the semiconductor integrated circuit, and the more stable the performance of the semiconductor integrated circuit. Therefore, the drive current generating circuit is required to stably generate a constant drive current.

[0067] In a conventional drive current generating circuit, a reference current Iref is generated in a voltage source, and then a current mirror is used to proportionally amplify the reference current Iref to the required drive current. Figure 1 As shown, Figure 1 The driving current generating circuit shown includes a first-stage current mirror, a second-stage current mirror and a third-stage current mirror, wherein the first-stage current mirror includes a transistor M1 and a transistor M2 with a common source and a common gate, and the source of the transistor M1 and the transistor M2 is coupled to the VSS terminal (0V), the second-stage current mirror includes a transistor M3 and a transistor M4 with a common source and a common gate, and the source of the transistor M3 and the transistor M4 is coupled to the VP terminal (greater than 0V), and the third-stage current mirror includes a transistor M5 and a transistor M6 with a common source and a common gate, and the source of the transistor M5 and the transistor M6 is coupled to the VN terminal (less than 0V), VA represents the gate voltage of the transistor M5, and VB represents the gate voltage of the transistor M6. Specifically, the voltage source VDD generates a reference current Iref, and outputs the driving current Iout after passing through the first-stage current mirror, the second-stage current mirror and the third-stage current mirror.

[0068] Further, refer to Figure 1 For a current-driven memory array, there is usually a long metal wire between transistor M6 and transistor M5 in the driving current generating circuit, which may cause current transmission loss. Therefore, an amplifier circuit is required in the driving current generating circuit to ensure stable transmission of current on the long metal wire. For example, refer to Figure 2 As shown, compared to Figure 1 The driving current generating circuit shown, Figure 2 The driving current generating circuit shown in the figure is provided with a voltage follower as an amplifying circuit. Figure 2 The connection relationship of the current mirrors at each level in the driving current generating circuit shown can be referred to Figure 1 Reference Figure 2The voltage source VDD generates a reference current Iref, which is transmitted to the transistor M5 in the third-stage current mirror after passing through the first-stage current mirror and the second-stage current mirror. Since there is a long metal wiring (metal) between the transistor M5 and the transistor M6 in the third-stage current mirror, a voltage follower is added between the transistor M5 and the transistor M6 to ensure the stable transmission of the current. Finally, the driving current Iout is output through the transistor M6 to the storage unit in the current-type driven storage array.

[0069] For current-driven storage arrays, multiple currents from multiple power domains are required to implement read, program, or erase operations. Figure 1 or Figure 2 The driving current generating circuit shown constitutes a driving circuit, which consumes a large amount of power during use, especially when in standby mode.

[0070] In view of this, an embodiment of the present disclosure provides a driving circuit of a memory.

[0071] refer to Figure 3 , Figure 3 1 is a schematic diagram of a memory driving circuit 100 according to an embodiment of the present disclosure, comprising: a first current mirror unit 101, at least two first switches SW1, a voltage source VDD, a second current mirror unit 102, a second switch SW2 and a charging unit 103; wherein,

[0072] The first current mirror unit 101 has an input end coupled to the voltage source VDD through a first first switch SW1, and an output end coupled to the input end of the second current mirror unit 102 through a second first switch SW1, and an output end of the second current mirror unit 102 is used to couple to the storage unit;

[0073] The first current mirror unit 101 is configured to generate an output current based on a reference current transmitted by a voltage source VDD and transmit the output current to the second current mirror unit 102 during a period when the first first switch SW1 and the second first switch SW1 are turned on;

[0074] The second current mirror unit 102 includes: a first semiconductor circuit and a second semiconductor circuit; wherein a first end of the first semiconductor circuit is coupled to a first node of a second switch SW2, a first end of the second semiconductor circuit is coupled to a second node of the second switch SW2, a second end of the first semiconductor circuit is coupled to a second first switch SW1, a second end of the second semiconductor circuit is coupled to a storage unit, and a third end of the first semiconductor circuit is coupled to a third end of the second semiconductor circuit;

[0075] The charging unit 103 has one end coupled to the second switch SW2 and the first end of the second semiconductor circuit respectively, and the other end coupled to the third end of the second semiconductor circuit, and is configured to charge according to the output current during the conduction period of the second switch SW2, so that the voltage of the first end of the second semiconductor circuit is equal to the voltage of the first end of the first semiconductor circuit;

[0076] The charging unit 103 is further configured to discharge during the period when the second switch SW2 is turned off, so as to maintain the voltage at the first end of the second semiconductor circuit unchanged;

[0077] The second semiconductor circuit is configured to output a driving current when the first first switch SW1 , the second first switch SW1 , and the second switch SW2 are turned off; wherein the driving current is transmitted to the storage unit.

[0078] Here, the drive circuit of the memory is described using a two-stage current mirror structure, which includes a first current mirror unit 101 and a second current mirror unit 102, wherein the first current mirror unit 101 and the second current mirror unit 102 are connected to each other, and the drive current output by the second current mirror unit 102 is finally coupled to the storage unit. The drive circuit of the memory can also use other current mirror structures, such as gate filter current mirror, DC feedback current mirror or genetic evolution current mirror and other structures, which are not limited by the present disclosure.

[0079] refer to Figure 3 A first first switch SW1 may be provided between the first current mirror unit 101 and the voltage source VDD, and a second first switch SW1 may be provided between the first current mirror unit 101 and the second current mirror unit 102. Whether the first current mirror unit 101 works and whether current is output to the second current mirror unit 102 is controlled by turning on and off the first first switch SW1 and the second first switch SW1.

[0080] Specifically, when the first first switch SW1 is turned on, the voltage source VDD generates a reference current Iref, which is then transmitted to the first current mirror unit 101 through the first first switch SW1. The first current mirror unit 101 can copy or scale the reference current Iref according to the mirror ratio and then output it. Here, the mirror ratio of the input current to the output current of the first current mirror unit 101 can be 1:1, and the first current mirror unit 101 copies the reference current Iref according to the mirror ratio and then outputs the first current.

[0081] refer to Figure 3When the second first switch SW1 is turned on, the first current output by the first current mirror unit 101 is transmitted to the second current mirror unit 102 through the second first switch SW1. In one embodiment, the second current mirror unit 102 includes: a first semiconductor circuit and a second semiconductor circuit, a long metal wire is provided between the first end of the first semiconductor circuit and the first end of the second semiconductor circuit, and a second switch SW2 is provided on the metal wire.

[0082] Exemplarily, the second switch SW2 includes a first node and a second node, the first end of the first semiconductor circuit is coupled to the first node of the second switch SW2, and the first end of the second semiconductor circuit is coupled to the second node of the second switch SW2, wherein the first node and the second node are electrically connected when the second switch SW2 is turned on, and are electrically insulated when the second switch SW2 is turned off.

[0083] Specifically, when the second switch SW2 is turned on, the first end of the first semiconductor circuit is connected to the first end of the second semiconductor circuit. At this time, the first current output by the first current mirror unit 101 is transmitted to the first end of the second semiconductor circuit through the first semiconductor circuit and the second switch SW2, so as to output the driving current to the storage unit through the second semiconductor circuit. The second current mirror unit 102 can copy or scale the first current according to the mirror ratio and output it. The mirror ratio of the input current and the output current of the second current mirror unit 100 can be 1:1. The second current mirror unit 102 copies the first current according to the mirror ratio and outputs the second current. The second current is transmitted to the storage unit as the required driving circuit.

[0084] It should be noted that the mirror ratio of the first current mirror unit 101 and the second current mirror unit 102 may also adopt other ratios, which is not limited in the present disclosure.

[0085] In order to reduce the power consumption of the memory driving circuit, when the voltage at the first terminal of the second semiconductor circuit is equal to the voltage at the first terminal of the first semiconductor circuit, the second switch SW2 can be turned off. However, turning off the second switch SW2 will cause the voltage at the first terminal of the second semiconductor circuit (e.g. Figure 1 or Figure 2 The gate voltage VB of the transistor M6 is reduced, and the second semiconductor circuit may not be able to output the required driving current to the storage unit. Figure 3 In this embodiment, a charging unit 103 is additionally provided. One end of the charging unit 103 is respectively coupled to the second switch SW2 and the first end of the second semiconductor circuit, and the other end is coupled to the third end of the second semiconductor circuit. The charging unit 103 is charged during the conduction period of the second switch SW2, so that the voltage of the first end of the second semiconductor circuit (such as Figure 3 VD) and the first terminal voltage of the first semiconductor circuit (such as Figure 3In this way, the charging unit 103 can maintain the first terminal voltage of the second semiconductor circuit (such as Figure 3 Therefore, the second semiconductor circuit can continuously and stably output the driving current to the storage unit to meet the driving requirements of the storage unit.

[0086] In the embodiment of the present disclosure, a first switch, a second switch and a charging unit are provided in the driving circuit, and the working duration of the first current mirror unit and the second current mirror unit is controlled by the first switch and the second switch. When the first switch and the second switch are both turned on, the first current mirror unit and the second current mirror unit work, during which the charging unit is charged so that the first terminal voltage of the second semiconductor circuit in the second current mirror unit is equal to the first terminal voltage of the first semiconductor circuit in the second current mirror unit, so that the second semiconductor circuit can output a driving current to the storage unit to drive the storage unit to perform a reading, programming or erasing operation. Subsequently, the switches in the driving circuit are turned off, and the first current mirror unit and the second current mirror unit stop working. The intermittent operation of the first current mirror unit and the second current mirror unit is realized by controlling the on and off of the first switch and the second switch, which is conducive to reducing the static power consumption of the driving circuit, and because the charging unit can discharge during the switch off period to maintain the first terminal voltage of the second semiconductor circuit unchanged, the second semiconductor circuit can continuously and stably output a driving current to the storage unit to meet the driving requirements of the storage unit.

[0087] In some embodiments, reference Figure 3 , the driving circuit of the memory further includes a first enable signal line EN1, a second enable signal line EN2 and a driving control unit;

[0088] A first enable signal line EN1, configured to transmit a first enable signal;

[0089] A second enable signal line EN2, configured to transmit a second enable signal;

[0090] The first switch SW1 is coupled to the first enable signal line EN1 and is configured to be turned on when the first enable signal is at a high level and turned off when the first enable signal is at a low level;

[0091] The second switch SW2 is coupled to the second enable signal line EN2 and is configured to be turned on when the second enable signal is at a high level and turned off when the second enable signal is at a low level;

[0092] The driving control unit is coupled to the first enable signal line EN1 and the second enable signal line EN2 respectively, and is configured to control the first enable signal line EN1 to transmit the first enable signal and control the second enable signal line EN2 to transmit the second enable signal according to a read operation instruction, a program operation instruction or an erase operation instruction.

[0093] refer to Figure 3 , the first enable signal line EN1 can control the on / off of the first first switch SW1, the second first switch SW1, the third first switch SW1 and the fourth first switch SW1, and the second enable signal line EN2 can control the on / off of the second switch SW2. Specifically, referring to Figure 4 , the first enable signal line EN1 is at a high level in the first cycle (Ton), at which time the first switch SW1 is turned on, and the first enable signal line EN1 is at a low level in the second cycle (Toff), at which time the first switch SW1 is turned off. The second enable signal line EN2 is at a high level in the third cycle (ton), at which time the second switch SW2 is turned on, and the second enable signal line EN2 is at a low level in the fourth cycle (toff), at which time the second switch SW2 is turned off.

[0094] Here, reference Figure 4 , the duration of the third cycle (ton) in the second enable signal line EN2 is less than the duration of the first cycle (Ton) in the first enable signal line EN1, and the charging unit 103 can be charged to the target voltage during the conduction period of the second switch SW2 by first turning on the first switch SW1 and then turning on the second switch SW2. Here, the charging unit 103 can stop charging when the voltage at the first terminal of the second semiconductor circuit is equal to the voltage at the first terminal of the first semiconductor circuit. At this time, the voltage of the charging unit 103 is the target voltage.

[0095] In one embodiment, the driving circuit of the memory further includes a driving control unit (not shown), which is used to control the reading, programming or erasing operations on the selected memory cells. The reading, programming or erasing operations require different driving currents to be applied to the memory cells. The driving control unit controls the first enable signal line EN1 to transmit the first enable signal and controls the second enable signal line EN2 to transmit the second enable signal, so that the first current mirror unit 101 and the second current mirror unit 102 output the required driving current to the memory cells.

[0096] In the disclosed embodiment, the driving control unit controls the first switch SW1 and the second switch SW2 through the first enable signal line EN1 and the second enable signal line EN2, so that the first current mirror unit 101 and the second current mirror unit 102 work intermittently, which is beneficial to reducing the static power consumption of the driving circuit.

[0097] In some embodiments, reference Figure 3 , the first current mirror unit 101 includes: a first current mirror and a second current mirror; wherein,

[0098] The first current mirror and the second current mirror have the same structure;

[0099] The input of the first current mirror is coupled to the voltage source VDD through the first first switch SW1 , the output of the first current mirror is coupled to the input of the second current mirror, and the output of the second current mirror is coupled to the input of the second current mirror unit 102 through the second first switch SW1 .

[0100] Here, the first current mirror unit 101 may include two-stage current mirrors, and the first current mirror unit 101 includes a first current mirror and a second current mirror. Based on the embodiment of the present disclosure, increasing the number of current mirrors accordingly still falls within the scope of the present disclosure.

[0101] In one example, the first current mirror and the second current mirror have the same structure. For example, the first current mirror and the second current mirror both use a common-source common-gate current mirror structure, which can reduce the error of the current in the driving circuit and improve the output accuracy of the driving circuit. In another example, the first current mirror and the second current mirror have different structures.

[0102] In one example, the mirror ratios of the first current mirror and the second current mirror are the same, for example, the mirror ratios of the first current mirror and the second current mirror are both 1: 1. In another example, the mirror ratios of the first current mirror and the second current mirror are different, for example, the mirror ratio of the first current mirror is 1: 1, and the mirror ratio of the second current mirror is 1: 3. Here, the mirror ratio of the first current mirror and the second current mirror can be set according to the actual demand of the driving current.

[0103] In the embodiment of the present disclosure, when the first first switch SW1 and the second first switch SW1 are turned on, the reference current Iref is amplified by the first current mirror and the second current mirror in the first current mirror unit 101 according to the mirror ratio, and then the first current is output and transmitted to the second current mirror unit 102. Here, it is preferred that the first current mirror and the second current mirror have the same structure, for example, the first current mirror and the second current mirror both adopt a common source and common gate current mirror structure, which can reduce the error of the current in the driving circuit and improve the output accuracy of the driving circuit.

[0104] In some embodiments, reference Figure 3 , the drive circuit of the memory further includes: a third first switch SW1, a first current mirror including a first transistor Q1 and a second transistor Q2, and a second current mirror including a third transistor Q3 and a fourth transistor Q4; wherein,

[0105] The gate of the first transistor Q1 is coupled to the gate of the second transistor Q2, the source of the first transistor Q1 is coupled to the source of the second transistor Q2, the gate of the first transistor Q1 is also coupled to the drain of the first transistor Q1, the drain of the first transistor Q1 is coupled to the voltage source VDD through the first first switch SW1, and the drain of the second transistor Q2 is coupled to the drain of the third transistor Q3 through the third first switch SW1;

[0106] The gate of the third transistor Q3 is coupled to the gate of the fourth transistor Q4, the source of the third transistor Q3 is coupled to the source of the fourth transistor Q4, the gate of the third transistor Q3 is also coupled to the drain of the third transistor Q3, and the drain of the fourth transistor Q4 is coupled to the second first switch SW1;

[0107] The first transistor Q1 and the second transistor Q2 include P-type transistors, and the third transistor Q3 and the fourth transistor Q4 include N-type transistors.

[0108] In one example, reference Figure 3 , the first current mirror includes a first transistor Q1 and a second transistor Q2, the second current mirror includes a third transistor Q3 and a fourth transistor Q4, a third first switch SW1 is provided between the first current mirror and the second current mirror, and the third first switch SW1 is used to control the current path from the first current mirror to the second current mirror. In another example, the first current mirror unit 101 may include a first current mirror, a second current mirror and a third current mirror, a first switch SW1 may be provided between the first current mirror and the second current mirror, and another first switch SW1 may be provided between the second current mirror and the third current mirror. Here, the above-mentioned first switches SW1 are all controlled by the first enable signal line EN1, and are turned on and off synchronously.

[0109] On the basis of the embodiments of the present disclosure, increasing the number of first switches SW1 accordingly according to increasing the number of current mirrors still falls within the conceptual scope of the present disclosure.

[0110] Here, the first current mirror includes two P-type transistors and the second current mirror includes two N-type transistors. The specific transistor types and connection methods of the first current mirror and the second current mirror can be set according to the actual demand of the driving current, and the present disclosure does not limit this.

[0111] Specifically, refer to Figure 3 , the source of the first transistor Q1 and the source of the second transistor Q2 are coupled to the ground terminal VSS (0V), the source of the third transistor Q3 and the fourth transistor Q4 are coupled to the positive voltage terminal VP, and the voltage of the positive voltage terminal VP is greater than 0. The first transistor Q1 and the second transistor Q2 include P-type transistors, the third transistor Q3 and the fourth transistor Q4 include N-type transistors, the first transistor Q1 and the second transistor Q2 are connected in a communal source and communal gate manner, and the third transistor Q3 and the fourth transistor Q4 are connected in a communal source and communal gate manner. The communal source and communal gate structure can reduce the influence of the channel length modulation effect of the current mirror in the driving circuit, thereby reducing the error of the mirror current in the driving circuit of the memory.

[0112] It should be noted that the reference Figure 3The inclined arrow on the fourth transistor Q4 indicates that the fourth transistor Q4 is an adjustable transistor, and the width-to-length ratio of the transistor is adjustable. Here, the width-to-length ratio can be adjusted according to the actual demand of the driving current. Figure 3 The transistor shown in FIG. 1 is configured as an adjustable transistor, and the present disclosure is not limited thereto.

[0113] In the disclosed embodiment, the transistors in each current mirror are connected in a common source and common gate manner, which can reduce the error of the current in the driving circuit, improve the output accuracy of the driving circuit, and thus improve the memory performance.

[0114] In some embodiments, reference Figure 3 , the first semiconductor circuit includes a fifth transistor Q5, and the second semiconductor circuit includes a sixth transistor Q6; wherein,

[0115] The gate of the fifth transistor Q5 is coupled to the second switch SW2, the drain of the fifth transistor Q5 is coupled to the second first switch SW1, and the gate of the fifth transistor Q5 is also coupled to the drain of the fifth transistor Q5;

[0116] The gate of the sixth transistor Q6 is coupled to the second switch SW2, and the drain of the sixth transistor Q6 is used to couple to the storage unit;

[0117] A source of the fifth transistor Q5 is coupled to a source of the sixth transistor Q6;

[0118] The fifth transistor Q5 and the sixth transistor Q6 include P-type transistors.

[0119] In one example, reference Figure 3 The second current mirror unit 102 includes a fifth transistor Q5 and a sixth transistor Q6 , a second switch SW2 is provided between the fifth transistor Q5 and the sixth transistor Q6 , and the second switch SW2 is used to control a current path from the fifth transistor Q5 to the sixth transistor Q6 in the second current mirror unit 102 .

[0120] Here, the second current mirror unit 102 includes two P-type transistors for illustration. The specific transistor types and connection methods of the second current mirror unit 102 can be set according to the actual demand of the driving current, and the present disclosure does not limit this.

[0121] Specifically, refer to Figure 3 , the source of the fifth transistor Q5 and the source of the sixth transistor Q6 are coupled to the negative voltage terminal VN, and the voltage of the negative voltage terminal VN is less than 0. The fifth transistor Q5 and the sixth transistor Q6 are connected in a cascode structure, and the cascode structure can reduce the influence of the channel length modulation effect of the current mirror in the driving circuit, thereby reducing the error of the mirror current in the driving circuit of the memory.

[0122] In the disclosed embodiment, the transistors in the second current mirror unit 102 are connected in a common source and common gate manner, which can reduce the error of the current in the driving circuit and improve the output accuracy of the driving circuit, thereby improving the memory performance.

[0123] In some embodiments, reference Figure 3 , the drive circuit of the memory further includes: a voltage follower 104 and a fourth first switch SW1; wherein,

[0124] The first input terminal of the voltage follower 104 is coupled to the first terminal of the first semiconductor circuit, the second input terminal of the voltage follower 104 is coupled to the output terminal of the voltage follower 104, the output terminal of the voltage follower 104 is also coupled to the second switch SW2, the first voltage terminal of the voltage follower 104 is coupled to the positive voltage terminal VP through the fourth first switch SW1, the voltage of the positive voltage terminal VP is greater than 0, the second voltage terminal of the voltage follower 104 is coupled to the negative voltage terminal VN, the voltage of the negative voltage terminal VN is less than 0;

[0125] The voltage follower 104 is configured to transmit the output current to the charging unit 103 during the conduction period of the first first switch SW1 , the second first switch SW1 , the fourth first switch SW1 , and the second switch SW2 , so as to charge the charging unit 103 .

[0126] In this embodiment, for the current-driven storage array, refer to Figure 3 There is a long metal wire between the fifth transistor Q5 and the sixth transistor Q6, which may cause current transmission loss. An amplification circuit is required to ensure stable transmission of current on the long metal wire. Figure 3 As shown, a voltage follower 104 is added between the fifth transistor Q5 and the sixth transistor Q6 to ensure stable current transmission, and finally the driving current Iout is output to the storage unit through the sixth transistor Q6.

[0127] Here, the voltage follower 104 is used as an amplifier circuit between the first semiconductor circuit and the second semiconductor circuit for illustration. Other types of amplifier circuits may also be used, and the present disclosure does not limit this.

[0128] In the embodiment of the present disclosure, the voltage follower 104 is used to reduce the loss of the transmission current on the metal wiring between the fifth transistor Q5 and the sixth transistor Q6, thereby improving the output accuracy of the driving circuit and enhancing the memory performance.

[0129] In some embodiments, reference Figure 3 , the charging unit 103 includes: a capacitor C; wherein,

[0130] The first plate of the capacitor C is coupled to the second switch SW2 and the first end of the second semiconductor circuit respectively, and the second plate of the capacitor C is coupled to the third end of the first semiconductor circuit and the third end of the second semiconductor circuit.

[0131] It should be noted that in order to reduce the power consumption of the drive circuit of the memory, the switch in the drive circuit needs to be turned off after the drive circuit works for a period of time. However, turning off the switch in the drive circuit, such as the second switch SW2, will cause the first terminal voltage of the second semiconductor circuit (reference Figure 3 , the gate voltage VD of the sixth transistor Q6 is reduced, and the second semiconductor circuit may not be able to output the required driving current to the storage unit. Therefore, in this embodiment, a charging unit 103 is additionally provided, and the charging unit 103 is charged during the conduction period of the second switch SW2 so that the first terminal voltage of the second semiconductor circuit is equal to the first terminal voltage of the first semiconductor circuit. In this way, the charging unit 103 can maintain the gate voltage VD of the sixth transistor Q6 unchanged during the off period of the second switch SW2. Therefore, the second semiconductor circuit can continuously and stably output the driving current to the storage unit to meet the driving requirements of the storage unit.

[0132] Here, the charging unit 103 preferably includes: a capacitor C, and the capacity of the capacitor C needs to satisfy the requirement that during the charging of the capacitor C, the first terminal voltage of the second semiconductor circuit gradually rises to be equal to the first terminal voltage of the first semiconductor circuit, and when the first terminal voltage of the second semiconductor circuit is equal to the first terminal voltage of the first semiconductor circuit, the capacitor C stops charging.

[0133] In the disclosed embodiment, the gate voltage VD of the sixth transistor Q6 is maintained unchanged by the capacitor C during the period when the second switch SW2 is turned off. Therefore, the driving circuit can continuously and stably output the driving current to the storage unit to meet the driving requirements of the storage unit and reduce the power consumption of the driving circuit.

[0134] In some embodiments, reference Figure 5 The memory driving circuit 500 includes n such as Figure 3 The memory driving circuit 100 shown in FIG. 1 can provide n different currents (eg, Figure 5 Iout1 to Ioutn) to the storage unit.

[0135] It should be noted that the voltage from the positive voltage terminal VP to the positive voltage terminal VPn in the memory driving circuit 500 is different, the voltage from the negative voltage terminal VN to the negative voltage terminal VNn is different, and the capacitance of the capacitor C1 to the capacitor Cn is different. For other components in the memory driving circuit 500, refer to the specific description of the above-mentioned memory driving circuit 100.

[0136] In the embodiments of the present disclosure, refer to Figure 3The memory driving circuit shown reduces the power consumption of the memory driving circuit 100 during use through the first switch SW1, the second switch SW2 and the charging unit 103. Since the power consumption of each memory driving circuit 100 in the memory driving circuit 500 is reduced, the power consumption of the memory driving circuit 500 in this embodiment can be greatly reduced.

[0137] Figure 6 FIG. 1 is a schematic diagram of a memory according to an exemplary embodiment. Based on the driving circuit structure of the above memory, the embodiment of the present disclosure provides a memory, such as Figure 6 As shown, the memory 600 includes:

[0138] A drive circuit of the memory according to the above embodiment; and

[0139] A plurality of memory cells are coupled to a drive circuit of the memory and are configured to implement a read, program or erase operation according to a drive current output by the drive circuit of the memory.

[0140] In one embodiment, reference Figure 6 , a plurality of storage cells are coupled to a drive circuit of the memory, and a drive current is output to the storage cells through the drive circuit of the memory to implement a read, program or erase operation on the storage cells. In another embodiment, the drive circuit of the memory may include n sub-drive circuits, each storage cell may be coupled to a sub-drive circuit, and the drive circuit of the memory may provide n different currents to the storage cells to implement a read, program or erase operation.

[0141] Figure 7 FIG. 1 is a schematic diagram of a memory system according to an exemplary embodiment. Based on the above memory structure, the present disclosure provides a memory system, such as Figure 7 As shown, it includes the memory as described in the above embodiment, and a memory controller; wherein,

[0142] Memory 600;

[0143] The memory controller 706 , coupled to the memory 600 , is configured to control the memory 600 .

[0144] The memory system 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0145] like Figure 7As shown in , the memory system 700 may include a host 708 and a storage subsystem 702, the storage subsystem 702 has one or more memories 600, and the storage subsystem further includes a memory controller 706. The host 708 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 708 may be configured to send data to the memory 600. Alternatively, the host 708 may be configured to receive data from the memory 600.

[0146] The memory 600 may be any memory disclosed in the present disclosure.

[0147] According to some embodiments, the memory controller 706 is also coupled to the host 708. The memory controller 706 may manage data stored in the memory 600 and communicate with the host 708.

[0148] In some embodiments, the memory controller 706 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0149] In some embodiments, the memory controller 706 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smart phones, tablet computers, laptops, etc., as well as enterprise storage arrays.

[0150] The memory controller 706 may be configured to control operations of the memory 600, such as read and write operations. The memory controller 706 may also be configured to manage various functions regarding data stored or to be stored in the memory 600, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 600.

[0151] The memory controller 706 may also perform any other suitable functions, for example, formatting the memory 600. The memory controller 706 may communicate with an external device (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 706 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0152] The memory controller 706 and one or more memories 600 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 700 can be implemented and packaged into different types of terminal electronic products.

[0153] In such Figure 8a In one example shown in FIG. 8 , the memory controller 706 and the single memory 600 may be integrated into a memory card 802. The memory card 802 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a processor that connects the memory card 802 to a host (e.g., Figure 7 A memory card connector 804 coupled to a host 708).

[0154] In such Figure 8b In another example shown in FIG. 8 , the memory controller 706 and the plurality of memories 600 may be integrated into a solid state drive (SSD) 806. The solid state drive 806 may also include a processor that interfaces the solid state drive 806 with a host (e.g., Figure 7 In some implementations, the storage capacity and / or operating speed of the solid-state drive 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0155] It can be understood that the memory controller 706 can execute the reading method provided by any embodiment of the present disclosure.

[0156] Fig. 9FIG. 1 is a flow chart of a method for driving a memory according to an exemplary embodiment. The method for driving a memory is used to drive the memory as described in the above embodiment. The embodiment of the present disclosure provides a method for driving a memory, such as Fig. 9 As shown, including:

[0157] S100: Control the first first switch and the second first switch to be turned on; wherein the voltage source is sequentially coupled to the first current mirror unit, the second first switch and the second current mirror unit through the first first switch;

[0158] S200: During a period when the first first switch and the second first switch are turned on, the first current mirror unit generates an output current based on a reference current transmitted by a voltage source and transmits the output current to the second current mirror unit;

[0159] S300: Control the second switch to be turned on; wherein the second current mirror unit comprises: a first semiconductor circuit and a second semiconductor circuit, a first end of the first semiconductor circuit is coupled to a first node of the second switch, a first end of the second semiconductor circuit is coupled to a second node of the second switch, a second end of the first semiconductor circuit is coupled to a second first switch, a second end of the second semiconductor circuit is used to couple to a storage unit, and a third end of the first semiconductor circuit and a third end of the second semiconductor circuit are at the same potential;

[0160] S400: During the conduction period of the second switch, charging the charging unit according to the output current, so that the voltage of the first terminal of the second semiconductor circuit is equal to the voltage of the first terminal of the first semiconductor circuit; wherein the charging unit has one end coupled to the second switch and the first end of the second semiconductor circuit respectively, and the other end coupled to the third end of the first semiconductor circuit and the third end of the second semiconductor circuit;

[0161] S500: Control the second switch to turn off;

[0162] S600: During the period when the second switch is turned off, the voltage at the first terminal of the second semiconductor circuit is maintained unchanged by discharging through the charging unit;

[0163] S700: Control the first first switch and the second first switch to be turned off;

[0164] S800: Outputting a driving current to a storage unit through a second semiconductor circuit while the first first switch, the second first switch, and the second switch are turned off.

[0165] For example, refer to Figure 3 As shown, the memory driving circuit 100 includes: a first current mirror unit 101 , at least two first switches SW1 , a voltage source VDD, a second current mirror unit 102 , a second switch SW2 , and a charging unit 103 .

[0166] The first current mirror unit 101, at least two first switches SW1, the voltage source VDD, the second current mirror unit 102, the second switch SW2 and the charging unit 103 formed in this embodiment can all be manufactured using conventional integrated circuit processing technology. There are no special requirements for the process conditions and it is compatible with conventional integrated circuit processing technology, which is convenient for simplifying the process flow and saving manufacturing costs.

[0167] In one embodiment, the memory further includes a driving control unit. The driving control unit may be an executor of the driving method of the memory. The driving control unit applies different driving currents to the selected storage cells to perform reading, programming or erasing operations.

[0168] Specifically, refer to Figure 3 , a first first switch SW1 may be provided between the first current mirror unit 101 and the voltage source VDD, and a second first switch SW1 may be provided between the first current mirror unit 101 and the second current mirror unit 102. The driving control unit controls the first first switch SW1 and the second first switch SW1 to be turned on, so that the first current mirror unit 101 generates an output current based on a reference current transmitted by the voltage source VDD and transmits the output current to the second current mirror unit 102.

[0169] In one embodiment, the second current mirror unit 102 includes: a first semiconductor circuit and a second semiconductor circuit, a long metal wire exists between the first end of the first semiconductor circuit and the first end of the second semiconductor circuit, and a second switch SW2 is arranged on the metal wire. Specifically, the driving control unit controls the second switch SW2 to be turned on, and charges the charging unit so that the voltage at the first end of the second semiconductor circuit is equal to the voltage at the first end of the first semiconductor circuit, and then the driving control unit controls the second switch SW2 to be turned off, so that the charging unit 103 can maintain the voltage at the first end of the second semiconductor circuit unchanged during the period when the second switch SW2 is turned off, and therefore, the second semiconductor circuit can continuously and stably output the driving current to the storage unit to meet the driving requirements of the storage unit.

[0170] In the disclosed embodiment, the first current mirror unit and the second current mirror unit are intermittently operated by controlling the on and off of the first switch and the second switch through the driving control unit, which is beneficial to reducing the static power consumption of the driving circuit. In addition, since the charging unit can discharge during the switch-off period to maintain the first terminal voltage of the second semiconductor circuit unchanged, the second semiconductor circuit can continuously and stably output the driving current to the storage unit to meet the driving current demand of the storage unit.

[0171] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A memory driving circuit, characterized in that: include: A first current mirror unit, at least two first switches, a voltage source, a second current mirror unit, a second switch and a charging unit; wherein, The first current mirror unit has an input end coupled to the voltage source through a first first switch, an output end coupled to the input end of the second current mirror unit through a second first switch, and an output end of the second current mirror unit is used to couple to a storage unit; The first current mirror unit is configured to generate an output current based on a reference current transmitted by the voltage source and transmit the output current to the second current mirror unit during a period in which a first first switch and a second first switch are turned on; The second current mirror unit comprises: a first semiconductor circuit and a second semiconductor circuit; wherein a first end of the first semiconductor circuit is coupled to a first node of the second switch, a first end of the second semiconductor circuit is coupled to a second node of the second switch, a second end of the first semiconductor circuit is coupled to a second first switch, a second end of the second semiconductor circuit is coupled to the storage unit, and a third end of the first semiconductor circuit is coupled to a third end of the second semiconductor circuit; The charging unit has one end coupled to the second switch and the first end of the second semiconductor circuit respectively, and the other end coupled to the third end of the second semiconductor circuit, and is configured to charge according to the output current during the conduction period of the second switch, so that the voltage of the first end of the second semiconductor circuit is equal to the voltage of the first end of the first semiconductor circuit; The charging unit is further configured to discharge during the period when the second switch is turned off, so as to maintain the voltage of the first terminal of the second semiconductor circuit unchanged; The second semiconductor circuit is configured to output a driving current when a first first switch, a second first switch, and the second switch are turned off; wherein the driving current is transmitted to the storage unit.

2. The memory driving circuit according to claim 1, characterized in that: The drive circuit of the memory further includes a first enable signal line, a second enable signal line and a drive control unit; The first enable signal line is configured to transmit a first enable signal; The second enable signal line is configured to transmit a second enable signal; The first switch is coupled to the first enable signal line and is configured to be turned on when the first enable signal is at a high level and turned off when the first enable signal is at a low level; The second switch is coupled to the second enable signal line and is configured to be turned on when the second enable signal is at a high level and turned off when the second enable signal is at a low level; The drive control unit is coupled to the first enable signal line and the second enable signal line, respectively, and is configured to control the first enable signal line to transmit a first enable signal and control the second enable signal line to transmit a second enable signal according to a read operation instruction, a program operation instruction or an erase operation instruction.

3. The memory driving circuit according to claim 1, characterized in that: The first current mirror unit includes: a first current mirror and a second current mirror; wherein, The first current mirror and the second current mirror have the same structure; The input end of the first current mirror is coupled to the voltage source through the first first switch, the output end of the first current mirror is coupled to the input end of the second current mirror, and the output end of the second current mirror is coupled to the input end of the second current mirror unit through the second first switch.

4. The memory driving circuit according to claim 3, characterized in that: The drive circuit of the memory further includes: a third first switch, the first current mirror includes a first transistor and a second transistor, and the second current mirror includes a third transistor and a fourth transistor; wherein, The gate of the first transistor is coupled to the gate of the second transistor, the source of the first transistor is coupled to the source of the second transistor, the gate of the first transistor is also coupled to the drain of the first transistor, the drain of the first transistor is coupled to the voltage source through the first first switch, and the drain of the second transistor is coupled to the drain of the third transistor through the third first switch; The gate of the third transistor is coupled to the gate of the fourth transistor, the source of the third transistor is coupled to the source of the fourth transistor, the gate of the third transistor is also coupled to the drain of the third transistor, and the drain of the fourth transistor is coupled to a second first switch; The first transistor and the second transistor include P-type transistors, and the third transistor and the fourth transistor include N-type transistors.

5. The memory driving circuit according to claim 1, characterized in that: The first semiconductor circuit includes a fifth transistor, and the second semiconductor circuit includes a sixth transistor; wherein, The gate of the fifth transistor is coupled to the second switch, the drain of the fifth transistor is coupled to a second first switch, and the gate of the fifth transistor is also coupled to the drain of the fifth transistor; The gate of the sixth transistor is coupled to the second switch, and the drain of the sixth transistor is used to couple to the storage unit; A source of the fifth transistor is coupled to a source of the sixth transistor; The fifth transistor and the sixth transistor include P-type transistors.

6. The memory driving circuit according to claim 1, characterized in that: The drive circuit of the memory further includes: a voltage follower and a fourth of the first switches; wherein, The first input terminal of the voltage follower is coupled to the first terminal of the first semiconductor circuit, the second input terminal of the voltage follower is coupled to the output terminal of the voltage follower, the output terminal of the voltage follower is also coupled to the second switch, the first voltage terminal of the voltage follower is coupled to the positive voltage terminal through the fourth first switch, the voltage of the positive voltage terminal is greater than 0, the second voltage terminal of the voltage follower is coupled to the negative voltage terminal, the voltage of the negative voltage terminal is less than 0; The voltage follower is configured to transmit the output current to the charging unit to charge the charging unit during the conduction period of the first first switch, the second first switch, the fourth first switch and the second switch.

7. The memory driving circuit according to claim 1, characterized in that: The charging unit comprises: a capacitor; wherein, The first plate of the capacitor is coupled to the second switch and the first end of the second semiconductor circuit respectively, and the second plate of the capacitor is coupled to the third end of the first semiconductor circuit and the third end of the second semiconductor circuit.

8. A memory, characterized in that: include: The drive circuit of the memory according to any one of claims 1 to 7; as well as A plurality of storage units are coupled to the drive circuit of the memory and are configured to implement a read, program or erase operation according to a drive current output by the drive circuit of the memory.

9. A storage system, characterized in that: include: The memory according to claim 8; as well as A memory controller, coupled to the memory, is configured to control the memory.

10. A method for driving a memory, characterized in that: The method is used to drive the memory as claimed in claim 8, and the driving method comprises: Controlling the first first switch and the second first switch to be turned on; wherein the voltage source is sequentially coupled to the first current mirror unit, the second first switch and the second current mirror unit through the first first switch; During the conduction period of the first first switch and the second first switch, the first current mirror unit generates an output current based on the reference current transmitted by the voltage source and transmits the output current to the second current mirror unit; Control the second switch to be turned on; wherein the second current mirror unit comprises: a first semiconductor circuit and a second semiconductor circuit, a first end of the first semiconductor circuit is coupled to a first node of the second switch, a first end of the second semiconductor circuit is coupled to a second node of the second switch, a second end of the first semiconductor circuit is coupled to a second first switch, a second end of the second semiconductor circuit is used to couple to a storage unit, and a third end of the first semiconductor circuit and a third end of the second semiconductor circuit are at the same potential; During the conduction period of the second switch, the charging unit is charged according to the output current so that the voltage of the first terminal of the second semiconductor circuit is equal to the voltage of the first terminal of the first semiconductor circuit; wherein the charging unit has one end coupled to the second switch and the first end of the second semiconductor circuit respectively, and the other end coupled to the third end of the first semiconductor circuit and the third end of the second semiconductor circuit; Controlling the second switch to turn off; During the period when the second switch is turned off, the voltage at the first terminal of the second semiconductor circuit is maintained unchanged by discharging through the charging unit; Controlling a first of the first switches and a second of the first switches to be turned off; During the period when a first first switch, a second first switch, and the second switch are turned off, a driving current is output to the storage unit through the second semiconductor circuit.

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