Interconnect structure with cobalt-implanted ruthenium liner and cobalt cap

Abstract

An interconnect structure and method for forming the same include forming a recess in a dielectric layer and conformally depositing a barrier layer in the recess. A cobalt-implanted ruthenium liner is formed over the barrier layer. A cobalt-containing ruthenium liner is formed by stacking a second liner over the first liner, the first liner being located over the barrier layer. The first liner comprises ruthenium, while the second liner comprises cobalt. Cobalt atoms migrate from the second liner to the first liner, forming a cobalt-implanted ruthenium liner. A conductive material is deposited over the cobalt-implanted ruthenium liner to fill the recess, followed by a capping layer made of cobalt.

Description

Technical Field

[0001] The present invention relates generally to the field of complementary metal oxide semiconductor (CMOS) devices and, more particularly, to fabricating a copper interconnect structure having a cobalt-implanted ruthenium liner and a cobalt cap. Background Art

[0002] Typical components of an integrated circuit (IC) include transistors, capacitors, and the like. In semiconductor chip manufacturing, these IC components are coupled via interconnect structures that conduct current through different circuit layers. These interconnect structures typically take the form of wires, trenches, or through-holes formed in dielectric layers on the metallization levels of a microelectronic device or IC. Interconnect structures are typically formed by depositing a dielectric layer, etching grooves in the dielectric layer, and filling the grooves with metal. Typically, interconnect structures are made of copper and can be formed using either a single or dual damascene manufacturing process. In a single damascene process, interconnect structures are manufactured independently, while in a dual damascene process, interconnect structures are manufactured simultaneously.

[0003] Typically, interconnect structures are lined with a barrier layer located at the interface between the dielectric layer and the underlying metal layer. The presence of the barrier layer can reduce electromigration (EM) issues in ICs. Electromigration can be defined as the migration of material caused by electron flow during operation under current. The interface between the interconnect structure and the surrounding dielectric is the primary path for material migration in metal lines. In 7nm technology and larger, ruthenium (Ru) liners are used for better copper (Cu) fill. However, cobalt (Co) from the cobalt cap used to encapsulate the copper fill can diffuse into the ruthenium liner, causing EM degradation and thus representing a critical electromigration resistance (yield) issue for back-end-of-line (BEOL) technologies. Therefore, alternative designs and techniques for forming the interconnect structure would be desirable. Summary of the Invention

[0004] The shortcomings of the prior art are overcome and additional advantages are provided by providing a method for forming an interconnect structure, the method comprising forming a recess in a dielectric layer, conformally depositing a barrier layer in the recess, and forming a cobalt-implanted ruthenium liner over the barrier layer. The cobalt-implanted ruthenium liner comprises a first liner over the barrier layer and a second liner over the first liner. The first liner comprises ruthenium and the second liner comprises cobalt. Cobalt atoms migrate from the second liner to the first liner to form the cobalt-implanted ruthenium liner. A conductive material is deposited over the cobalt-implanted ruthenium liner to fill the recess, and a capping layer is subsequently formed on a top surface of the conductive material, the capping layer comprising cobalt. The formation of the cobalt-implanted ruthenium liner reduces a cobalt concentration gradient between the capping layer and the first liner, which prevents cobalt from migrating from the capping layer.

[0005] Another embodiment of the present invention provides an alternative method for forming an interconnect structure, the method comprising forming a recess in a dielectric layer, conformally depositing a barrier layer in the recess, then conformally depositing a first liner on the barrier layer, and conformally depositing a second liner on the first liner. The first liner comprises ruthenium, and the second liner comprises cobalt. A third liner is then formed over the second liner, the third liner comprising ruthenium. Migration of cobalt atoms from the second liner to the first liner and the third liner forms a cobalt-implanted ruthenium liner. A conductive material is formed over the cobalt-implanted ruthenium liner to fill the recess, and then a capping layer is deposited over the top surface of the conductive material, the capping layer comprising cobalt. The formation of the cobalt-implanted ruthenium liner reduces a cobalt concentration gradient between the capping layer and the first and third liners, which prevents cobalt from migrating from the capping layer.

[0006] Another embodiment of the present invention provides a semiconductor structure comprising an interconnect structure within a dielectric layer, the interconnect structure comprising a barrier layer on a bottom surface and sidewalls of the interconnect structure, a first liner directly above the barrier layer, the first liner comprising ruthenium, a second liner directly above the first liner, the second liner comprising cobalt, a conductive material substantially filling the interconnect structure above the second liner, and a capping layer directly above the conductive material, the capping layer comprising cobalt, wherein migration of cobalt atoms from the second liner to the first liner reduces a concentration gradient between the capping layer and the first liner, the concentration gradient preventing diffusion of cobalt atoms from the capping layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description, which is given by way of example and is not intended to limit the invention thereto, will be best understood in conjunction with the accompanying drawings, in which:

[0008] Figure 1A is a cross-sectional view of a simplified semiconductor structure depicting forming a recess in a dielectric layer and depositing a barrier layer within the recess in accordance with an embodiment of the present invention;

[0009] Figure 1B is a cross-sectional view of a simplified semiconductor structure depicting deposition of a first liner over a barrier layer in accordance with an embodiment of the present invention;

[0010] Figure 1C is a cross-sectional view of a simplified semiconductor structure depicting deposition of a second liner over a first liner in accordance with an embodiment of the present invention;

[0011] Figure 1D is a cross-sectional view of a simplified semiconductor structure depicting deposition of a first conductive material over a second liner in accordance with an embodiment of the present invention;

[0012] Figure 1E is a cross-sectional view of a simplified semiconductor structure after a planarization process according to an embodiment of the present invention;

[0013] Figure 1F is a cross-sectional view of a simplified semiconductor structure according to an embodiment of the present invention, illustrating a first interconnect structure including a first capping layer over a first conductive material;

[0014] Figure 2A is a cross-sectional view of a simplified semiconductor structure depicting forming a recess in a dielectric layer and depositing a barrier layer within the recess according to another embodiment of the present invention;

[0015] Figure 2B is a simplified cross-sectional view of a semiconductor structure according to another embodiment of the present invention, depicting deposition of a first liner over a barrier layer and deposition of a second liner over the first liner;

[0016] Figure 2C is a cross-sectional view of a simplified semiconductor structure depicting deposition of a third liner over a second liner according to another embodiment of the present invention;

[0017] Figure 2D is a cross-sectional view of a simplified semiconductor structure according to another embodiment of the present invention, depicting deposition of a second conductive material over a third liner;

[0018] Figure 2E is a cross-sectional view of a simplified semiconductor structure after a planarization process according to another embodiment of the present invention;

[0019] Figure 2F is a cross-sectional view of a simplified semiconductor structure according to another embodiment of the present invention, illustrating a second final interconnect structure including a second capping layer over a second conductive material;

[0020] Figure 3A is a simplified cross-sectional view of a semiconductor structure depicting forming a recess in a dielectric layer and depositing a barrier layer within the recess according to yet another embodiment of the present invention;

[0021] Figure 3B is a cross-sectional view of a simplified semiconductor structure according to yet another embodiment of the present invention, depicting the deposition of a first liner, a second liner, and a third liner;

[0022] Figure 3C is a simplified cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention, depicting horizontal portions of a first liner, a second liner, and a third liner removed;

[0023] Figure 3D is a cross-sectional view of a simplified semiconductor structure according to another embodiment of the present invention, depicting deposition of a second conductive material over a third liner;

[0024] Figure 3Eis a cross-sectional view of a simplified semiconductor structure after a planarization process according to yet another embodiment of the present invention;

[0025] Figure 3F is a simplified cross-sectional view of a semiconductor structure according to yet another embodiment of the present invention, illustrating a second final interconnect structure including a second capping layer overlying a second conductive material;

[0026] The accompanying drawings are not necessarily to scale. The accompanying drawings are merely schematic representations and are not intended to depict specific parameters of the invention. The accompanying drawings are intended to depict only typical embodiments of the invention. In the accompanying drawings, like reference numerals represent like elements. DETAILED DESCRIPTION

[0027] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in various forms. However, the present invention may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Details of well-known features and techniques may be omitted from the description to avoid unnecessarily obscuring the presented embodiments.

[0028] For purposes of the description below, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the disclosed structures and methods as oriented in the accompanying drawings. Terms such as "above," "overlying," "atop," "on top of," "located at," or "located on top of" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein an intermediate element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element (e.g., a first structure) and a second element (e.g., a second structure) are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0029] It should be understood that although the terms first, second, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the scope of this concept, the first element discussed below can be referred to as the second element.

[0030] In order not to obscure the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and for illustrative purposes, and may not be described in detail in some instances. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description is more focused on the distinguishing features or elements of various embodiments of the present invention.

[0031] For many years, copper (Cu) has been used to manufacture integrated circuit (IC) chips. Copper is a better conductor than aluminum (Al) and allows metal features to be smaller. However, copper can cause problems if it is not properly contained in the interconnect structure. To properly contain the copper, cobalt (Co) has been used in current 7nm (nanometer) interconnects, both as a cobalt liner and as a cobalt cap for copper packaging. Unfortunately, the movement / diffusion of cobalt has been associated with a reduction in electromigration lifetime, especially when the cobalt cap is combined with a ruthenium (Ru) liner, which is commonly used in 7nm technology to enhance the copper fill.

[0032] Therefore, embodiments of the present invention provide a method and related structures for fabricating a copper interconnect structure having a cobalt-containing ruthenium liner and a cobalt cap. The proposed embodiments prevent cobalt atoms from diffusing from the cobalt cap into the ruthenium liner, thereby improving electromigration performance. A method for preventing cobalt from diffusing from the cobalt cap includes forming a tantalum nitride layer, followed by forming a ruthenium liner and a substantially thin cobalt liner capable of saturating the underlying ruthenium liner with cobalt atoms to form a cobalt-containing ruthenium liner, which can stop the driving force for diffusing cobalt from the cobalt cap. Figures 1A-1F The accompanying drawings in detail describe an embodiment of forming a cobalt-ruthenium liner in a copper interconnect structure. Figures 2A-3F The figures in detail describe an alternative embodiment in which a cobalt-ruthenium-containing liner may be formed to prevent cobalt diffusion in copper interconnects.

[0033] Now refer to Figures 1A-1F , shows a simplified depiction of a cross-sectional view of a semiconductor structure 100 during a series of processing steps in accordance with an embodiment of the present invention. Figures 1A to 1F The sequence of processing steps shown in FIG. 1 illustrates the formation of an interconnect structure 160 in a simplified depiction of a semiconductor structure 100 (hereinafter referred to as a “semiconductor structure”).

[0034] refer to Figure 1A At this step in the fabrication process, semiconductor structure 100 includes a dielectric layer 106 in which recesses 108 are formed using standard etching techniques. For purposes of illustration only and not limitation, only two recesses 108 are depicted within dielectric layer 106. As known to those skilled in the art, any number of recesses 108 may be formed depending on circuit design and / or requirements.

[0035] The dielectric layer 106 is typically formed over a device or metal layer (not shown) of the semiconductor structure 100. Specifically, as known to those skilled in the art, a dielectric material layer (e.g., dielectric layer 106) is deposited over an active region (not shown) of the semiconductor structure 100 and then etched to form openings or grooves. The openings or grooves are then filled with a conductive material to form an interconnect structure.

[0036] The dielectric material forming dielectric layer 106 may include, for example, a low-k dielectric material having a dielectric constant k in the range of about 2.4 to about 2.7. In some embodiments, dielectric layer 106 may include silicon oxide, silicon nitride, hydrogenated silicon oxycarbide, a silicon-based low-k dielectric, or a porous dielectric. Dielectric layer 106 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.

[0037] As described above, dielectric layer 106 is etched to form recess 108. Recess 108 can be formed using photolithography and etching processing techniques commonly used in single and dual damascene processes. Recess 108 can be shaped to accommodate various interconnect structures (e.g., trenches, lines, or vias). Typically, recess 108 can extend through dielectric layer 106 to expose an active area (not shown) of semiconductor structure 100. Recess 108 is then filled with a conductive metal, as will be described in detail below.

[0038] As those skilled in the art will know, Figure 1A The recess 108 shown in FIG has been etched into the dielectric layer 106 with a determined aspect ratio (H / D) of height (=H) to width (=D). In some embodiments, the aspect ratio ranges from about 0.5 to about 20, with a preferred aspect ratio of 1 to 10. However, in actual devices, high aspect ratios (H / D) greater than 20:1 may exist.

[0039] Continue to refer Figure 1A , a barrier layer 110 is deposited on the horizontal and vertical surfaces of the dielectric layer 106. In other words, as shown, the barrier layer 110 is deposited on the bottom surface, sidewalls, and top surface of the dielectric layer 106. The barrier layer 110 may include any barrier material suitable for preventing a subsequently deposited metal layer (e.g., cobalt, ruthenium, or copper) from diffusing into the dielectric layer 106. More particularly, the barrier layer 110 may prevent atoms from diffusing from a subsequently formed ruthenium and cobalt liner into the dielectric layer 106 and also act as an adhesion promoting layer, allowing the ruthenium and cobalt liner to bond to the dielectric layer 106. Experimental results have shown that depositing ruthenium directly on a dielectric material may result in poor adhesion and cause reliability issues related to delamination.

[0040] According to an embodiment, barrier layer 110 includes tantalum nitride (TaN). In other embodiments, barrier layer 110 may include alternative metal nitrides, including, for example, titanium nitride (TiN), tungsten nitride (WN), etc. Barrier layer 110 may be formed using standard deposition processes. For example, in some embodiments, barrier layer 110 may be formed using CVD, PVD, or atomic layer deposition (ALD) processes.

[0041] The thickness of barrier layer 110 may vary from about 0.5 nm to about 5 nm, and therebetween, although thicknesses less than 0.5 nm and greater than 5 nm are also acceptable.

[0042] The process continues by conformally depositing a first liner 120 directly over the barrier layer 110, as shown in FIG. Figure 1B As shown. In a preferred embodiment, the first liner 120 is composed essentially of ruthenium (Ru), if not entirely of ruthenium (Ru), and can be formed by a standard deposition process, such as PVD, CVD, electroless plating, evaporation, or any other deposition method for depositing a conformal thin film. As described above, ruthenium-containing liners, such as the first liner 120, are used in 7nm and above technologies to improve copper (Cu) filling. Specifically, the ruthenium-containing liner can better adhere to the copper seed, allowing the copper seed to be more conformal (i.e., eliminate voids) and thinner.

[0043] The first liner 120 may have a thickness ranging from about 0.5 nm to about 5 nm, and therebetween, although thicknesses less than 0.5 nm and greater than 5 nm are also acceptable. In an embodiment, the first liner 120 may have a thickness of approximately 10 nm.

[0044] After forming the first liner 120, the second liner 130 is formed directly above the first liner 120, as shown in FIG. Figure 1C As shown. The second liner 130 can include a very thin layer of (metallic) material conformally deposited on the first liner 120. In a preferred embodiment, the second liner 130 consists essentially of cobalt (Co), if not entirely of cobalt. Standard deposition processes, such as PVD, CVD, electroless plating, evaporation, or any other deposition method for depositing a conformal thin film, can be used to form the second liner 130.

[0045] By forming the second liner 130 in direct contact with the first liner 120, cobalt atoms from the second liner 130 migrate to the first liner 120 (i.e., the ruthenium liner), saturating the first liner 120 with cobalt so that there is no cobalt for the subsequently formed cobalt cap (e.g., Figure 1F Thus, depletion of the subsequently formed cobalt cap is prevented, which in turn can improve the (first) interconnect structure 160 ( Figure 1F )'s electromigration performance.

[0046] It should be noted that diffusion of cobalt into the ruthenium liner (e.g., first liner 120) typically occurs during thermal treatment of the semiconductor structure 100 during processing steps such as annealing or high temperature film deposition. Since the driving force for cobalt diffusion is the subsequently formed cobalt cap (e.g., Figure 1FTherefore, incorporating cobalt atoms from the second liner 130 into the first liner 120 reduces the cobalt concentration gradient between the cobalt cap and the first liner 120, thereby effectively inhibiting or mitigating cobalt diffusion in the semiconductor structure 100.

[0047] The thickness of the second liner 130 can be less than the thickness of the first liner 120. According to an embodiment, the second liner 130 can have a thickness of less than about 5 nm. In other embodiments, the second liner 130 can have a thickness ranging from about 0.1 nm to about 5 nm. In yet another embodiment, the second barrier liner can be thicker than the first liner 120.

[0048] Now refer to Figure 1D , the first conductive material 142 can be conformally deposited directly on the top surface of the second liner 130. According to an embodiment, the first conductive material 142 includes copper (Cu). In some embodiments, the first conductive material 142 can further include a dopant, such as manganese, magnesium, copper, aluminum, or other known dopants. The first conductive material 142 can be formed by electroplating, electroless plating, PVD, CVD, or any combination thereof.

[0049] The thickness of the first conductive material 142 may be sufficient to completely fill the remaining space within the groove 108. However, in some cases, the thickness of the first conductive material 142 may exceed the depth of the groove 108, such as Figure 1D In these cases, a planarization process may be performed on the semiconductor structure 100 to remove the region of the first conductive material 142 that exceeds the depth of the recess 108, as shown. Figure 1E Described in.

[0050] like Figure 1E As shown, excess portions of the first conductive material 142 may be removed from the semiconductor structure 100 by any planarization method known in the art, including, for example, chemical mechanical polishing (CMP). Furthermore, during the planarization process, (horizontal) portions or regions of the barrier layer 110, the first liner 120, and the second liner 130 that are parallel to the dielectric layer 106 may also be removed.

[0051] The process continues to form Figure 1F1. The first capping layer 156 is substantially, if not entirely, composed of cobalt (Co). The first capping layer 156 can be deposited by any suitable deposition process and can have a thickness ranging from about 0.5 nm to about 5 nm. As known to those skilled in the art, the first capping layer 156 is typically used in back-end-of-line (BEOL) technology to encapsulate copper (Cu) in the first conductive material 142, reduce Cu electromigration in the interconnect structure 160, and improve the overall reliability of the semiconductor structure 100.

[0052] Continue to refer Figure 1F , showing the final step of forming the first interconnect structures 160. According to an embodiment, each of the resulting first interconnect structures 160 includes a first barrier liner 120 directly above the barrier layer 110 and a (thin) second liner 130 directly above the first liner 120, a first conductive material 142 above the second liner 130 substantially filling the first interconnect structure 160, and a first capping layer 156 above the top surface of the first conductive material 142. This configuration can prevent cobalt from diffusing from the first capping layer 156 into the first liner 120. By preventing cobalt atoms from diffusing from the first capping layer 156, depletion of the first capping layer 156 can be avoided, thereby enhancing electromigration performance. More specifically, cobalt from the second liner 130 permeates the first liner 120 made of ruthenium, forming a cobalt-implanted ruthenium liner. Due to the reduced (cobalt) concentration gradient, the cobalt-implanted ruthenium liner can stop the driving force for diffusing cobalt from the first capping layer 156.

[0053] Now refer to Figures 2A-2F , shows a cross-sectional view of a semiconductor structure 100 during an alternative processing sequence for forming an interconnect structure according to another embodiment of the present invention. Figures 2A to 2F The sequence of processing steps shown in FIG. 1 shows an alternative method of forming the second interconnect structure 260 in the semiconductor structure 100. The formation of the second interconnect structure 260 is similar to that described above with reference to FIG. Figures 1A-1F However, in this embodiment, when forming the second barrier liner 130 ( Figure 2B ) thereafter, a third barrier liner 240 is formed directly above the second barrier liner 130, as shown Figure 2C shown.

[0054] like Figure 2CAs can be appreciated, in this embodiment, the second liner 130 is positioned between the first liner 120 and the third liner 240. According to an embodiment, the third liner 240 is made of substantially the same material as the first liner 120 (i.e., ruthenium) and can be formed using a similar deposition process. The third liner 240 can have a thickness ranging from about 0.5 nm to about 5 nm. As described above, ruthenium-containing liners are commonly used in advanced BEOL manufacturing to enhance copper filling. However, the combination of a ruthenium liner and a cobalt cap for copper packaging (e.g., Figure 1F The first capping layer 156 and Figure 2F The second capping layer 256) is associated with a reduced electromigration lifetime.

[0055] Therefore, by inserting the second liner 130 between the first liner 120 and the third liner 240, it is possible to saturate the first liner 120 and the third liner 240 with cobalt atoms of the second liner 130, so that cobalt can be prevented from being introduced into the subsequently formed cobalt capping layer (e.g., Figure 2F In addition, in this embodiment, the ruthenium (Ru) / copper (Cu) interface is maintained, enhancing the copper filling performance of copper electroplating or PVD copper reflow. Specifically, by depositing the third liner 240 on the second liner 130, the Ru / Cu interface is retained after the second conductive material 242 is deposited.

[0056] In some embodiments, after depositing the third liner 240, the semiconductor structure 100 may be subjected to an etching process to selectively remove horizontal portions of the first, second, and third liners 120, 130, and 240 from the dielectric layer 106, as shown in FIG. Figure 3C In other words, portions of the first, second, and third liners 120, 130, and 240 that are parallel to the dielectric layer 106 are selectively removed by any suitable etching process. For example, an argon (Ar) plasma etch may be performed to remove horizontal portions of the first, second, and third liners 120, 130, and 240 from the semiconductor structure 100.

[0057] like Figure 3C , the removal of these portions of the first, second, and third liners 120, 130, and 240 exposes the top (horizontal) surface of the barrier layer 110. In other words, Figure 3C After the etching step, the first, second and third liners 120, 130 and 240 remain only on the opposite sidewalls of the second interconnect structure 260, as shown in FIG. Figure 3F By performing the etching step ( Figure 3C ), in addition to reducing the cobalt diffusion from the second capping layer 256, the resulting second interconnect structure 260 ( Figure 3F) may also exhibit reduced via resistance due to the absence of the first, second, and third pads 120 , 130 , and 240 on the bottom of the second interconnect structure 260 .

[0058] Now refer to Figure 2D , the process continues with depositing a second conductive material 242, similar to Figure 1D The first conductive material 142 in the second conductive material 242 can be made of similar materials and can be made in the same manner as the first conductive material 142 ( Figure 1D ) is deposited in a similar manner. It should be noted that with or without Figure 3C With the etching step depicted in , the process continues with the deposition of a second conductive material 242 .

[0059] like Figure 2E As shown, excess portions of the second conductive material 242 may be removed from the semiconductor structure 100 by any planarization method known in the art, such as CMP. Furthermore, during the planarization process, horizontal portions or regions of the barrier layer 110, the first liner 120, the second liner 130, and the third liner 240 that are parallel to the dielectric layer 106 may also be removed from the semiconductor structure 100.

[0060] The process continues to form Figure 2F The second covering layer 256 is shown. The second covering layer 256 is made of similar materials and is formed in a similar manner to the first covering layer 156 ( Figure 1F ) are deposited in a similar manner.

[0061] Continue to refer Figure 2F , showing the final step of forming the second interconnect structure 260. According to an embodiment, each of the resulting second interconnect structures 260 includes a first liner 120 directly above the barrier layer 110, a (thin) second liner 130 interposed between the first liner 120 and the third liner 240, a second conductive material 242 above the third liner 240 that substantially fills the interconnect structure 260, and a second capping layer 256 above the top surface of the second conductive material 242. As described above, this structure can prevent cobalt from diffusing from the second capping layer 256 into the ruthenium-containing liners (i.e., the first liner 120 and the third liner 240). By preventing cobalt from diffusing from the second capping layer 256, depletion of the second capping layer 256 can be avoided, thereby enhancing electromigration performance. More specifically, cobalt atoms from the second liner 130 saturate the first and third liners 120, 240 made of ruthenium, stopping the driving force for cobalt diffusion from the second capping layer 256.

[0062] Thus, embodiments of the present invention provide copper interconnect structures with enhanced electromigration performance. In an embodiment, improved electromigration performance is achieved by forming a (thin) cobalt liner in direct contact with a ruthenium liner to form a cobalt-infused ruthenium liner caused by the migration of cobalt atoms from the cobalt liner to the ruthenium liner, which in turn can reduce the driving force for cobalt diffusion from the cobalt cap. In another embodiment, a thin cobalt liner is formed within the ruthenium liner or inserted between the ruthenium liners, in which embodiments the Ru / Cu interface can be maintained to further enhance copper filling. In yet another embodiment, in addition to reducing the diffusion of cobalt from the cobalt cap, the cobalt / ruthenium liner can be removed from the bottom surface of the interconnect structure, thereby reducing the path resistance, thereby further enhancing device performance and reliability.

[0063] The description of various embodiments of the present invention has been provided for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, practical applications, or improvements over existing technologies in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming an interconnect structure, comprising: forming a groove in the dielectric layer; conformally depositing a barrier layer within the recess; A cobalt-implanted ruthenium liner is formed over the barrier layer, wherein the cobalt-containing ruthenium liner comprises: a first liner over the barrier layer, the first liner comprising ruthenium; and a second liner overlying the first liner, the second liner comprising cobalt; a third liner overlying the second liner, the third liner comprising ruthenium, wherein migration of cobalt atoms from the second liner to the first liner and the third liner forms a cobalt-implanted ruthenium liner, wherein the cobalt-implanted ruthenium liner reduces a concentration gradient between an overlying layer and the cobalt-implanted ruthenium liner to prevent diffusion of cobalt atoms from the overlying layer; depositing a conductive material over the cobalt-implanted ruthenium liner to fill the recess; and A capping layer is formed over a top surface of the conductive material, the capping layer comprising cobalt.

2. The method according to claim 1, wherein The first liner is conformally deposited; the second liner is conformally deposited; and, The third liner is conformally deposited.

3. The method according to claim 1 or 2, wherein the thickness of the second liner is smaller than the thickness of the first liner. The method according to claim 1 , wherein the thickness of the second liner is greater than the thickness of the first liner. The method according to claim 2 , wherein a thickness of the second liner is smaller than a thickness of the third liner. The method of claim 1 , wherein the conductive material comprises copper.

7. The method of claim 1 or claim 2, wherein the barrier layer comprises tantalum nitride.

8. The method according to claim 1 or claim 2, further comprising performing a planarization process to remove excess conductive material from the interconnect structure.

9. The method of claim 2 , further comprising selectively removing a portion of the first liner, a portion of the second liner, and a portion of the third liner parallel to the dielectric layer from a bottom area of ​​the interconnect structure, wherein remaining portions of the first liner, the second liner, and the third liner remain on sidewalls of the interconnect structure.

10. The method according to claim 9, wherein: Selectively removing portions of the first liner, the second liner, and the third liner parallel to the dielectric layer from the bottom region of the interconnect structure reduces via resistance.

11. A semiconductor structure comprising: An interconnect structure within a dielectric layer, the interconnect structure comprising: a barrier layer disposed on a bottom surface and sidewalls of the interconnect structure; a first liner directly over the barrier layer, the first liner comprising ruthenium; a second liner positioned directly over the first liner, the second liner comprising cobalt; a third liner overlying the second liner, the third liner comprising ruthenium, wherein migration of cobalt atoms from the second liner to the first liner and the third liner forms a cobalt-implanted ruthenium liner; a conductive material over the cobalt-implanted ruthenium liner, the conductive material filling the interconnect structure; and A capping layer is located directly over the conductive material, the capping layer comprising cobalt, wherein the cobalt-implanted ruthenium liner reduces a concentration gradient between the capping layer and the cobalt-implanted ruthenium liner to prevent diffusion of cobalt atoms from the capping layer.

12. The semiconductor structure according to claim 11, wherein A portion of the first liner, a portion of the second liner, and a portion of the third liner remain on sidewalls of the interconnect structure, and a bottom portion of the interconnect structure is covered only by the barrier layer. 13 . The semiconductor structure of claim 12 , wherein a thickness of the second liner is smaller than thicknesses of the first liner and the third liner.

14. The semiconductor structure of claim 11 wherein the conductive material comprises copper and the barrier layer comprises tantalum nitride.

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