A four-array radar synchronized by a single communication cable

Abstract

The present invention discloses a four-sided array radar that realizes synchronization based on a single communication cable. The four-sided array radar includes a radar main array face and three radar slave array faces connected respectively by a communication cable. The main clock chip of the radar main array face is used to provide clock signals to the main FPGA chip, the main radio frequency circuit and the multi-channel interface chip respectively. The radar slave array face obtains the line recovery clock based on the communication cable. The phase-locked loop circuit processes the line recovery clock so that the slave FPGA chip and the slave radio frequency circuit work according to the processed clock signal, thereby realizing the clock synchronization of the radar main array face and the radar slave array face, and realizing the initial scanning synchronization of the two by configuring the radar main array face and the radar slave array face. The present invention realizes the clock synchronization and initial scanning synchronization of the main radar array face through a communication cable, has a simple structure, is easy to install and maintain; the communication cable can be an optical cable, which is not affected by the external electromagnetic environment and has great practical value.

Description

Technical Field

[0001] The present invention relates to the technical field of four-sided array radars, and in particular to a four-sided array radar that realizes synchronization based on a single communication cable. Background Art

[0002] The four-array radar that achieves synchronization based on a single communication cable must ensure strict synchronization of the four radar arrays during operation, that is, clock frequency synchronization and initial scanning synchronization are required. When the clock frequency of the radar is not synchronized, there is a slight frequency difference between the clock sources of each array. Even if the frequency points of each array are staggered, there is still inherent interference between the radars that is difficult to eliminate. When the initial scan of the radar is not synchronized, the pulse radar has hundreds of transmission and reception switches within one second. The transmission of one array can be directly coupled to the receiver of another array, submerging the target's echo signal in the interference signal, causing the radar to fail to work.

[0003] See also Figure 1 The general synchronization method is to connect nine cables, including communication cables, clock cables, and initial scanning cables, to the three slave arrays through the main array. This synchronization method has a complex structure, many cables, is difficult to install and maintain, and has poor reliability. In addition, the clock cable and initial scanning cable cannot be replaced by optical cables, and are easily interfered in complex electromagnetic environments or electronic countermeasures, which may cause the radar to fail to work. Summary of the invention

[0004] The purpose of the present invention is to provide a four-array radar that can achieve synchronization based on a single communication cable in order to address the deficiencies in the prior art.

[0005] To achieve the above-mentioned purpose, the present invention provides a four-sided array radar that realizes synchronization based on a single communication cable, comprising a radar main array surface and three radar slave array surfaces, wherein the radar main array surface is connected to the three radar slave array surfaces respectively through a communication cable, the radar main array surface comprises a master clock chip, a master FPGA chip, a master radio frequency circuit and a multi-channel interface chip, the master clock chip is used to provide clock signals to the master FPGA chip, the master radio frequency circuit and the multi-channel interface chip respectively, the radar slave array surface comprises a slave FPGA chip, a slave radio frequency circuit, an interface chip, a phase-locked loop circuit and a slave clock chip, the interface chip and the multi-channel interface chip are both connected to the communication cable, the interface chip uses the clock signal provided by the slave clock chip to work, and obtains a line recovery clock based on the communication cable, the phase-locked loop circuit processes the line recovery clock to obtain a clock signal synchronized with the clock signal sent by the master clock chip, and provides it to the slave FPGA chip and the slave radio frequency circuit, so that the slave FPGA chip and the slave radio frequency circuit work according to the clock signal;

[0006] The master FPGA chip is used to construct a synchronization message, and the priority of the synchronization message is set higher than that of the data message. The master FPGA chip uses the clock signal provided by the master clock chip to set the first counter inside it, and the unit of the first counter is Xns. The master FPGA chip sets a second counter with a fixed interval of a*Xns based on the first counter, and controls the multi-channel interface chip to send a synchronization message every a*Xns, and the synchronization message contains counting information;

[0007] The slave FPGA chip uses the clock signal output by the phase-locked loop circuit to set the third counter inside it, and the unit of the third counter is Xns. The slave FPGA chip sets a fourth counter with a fixed interval of a*Xns based on the third counter, and sets the receiving port to two receiving queues, one of which is used to process data messages, and the other is used to process synchronization messages. The synchronization messages are not cached. After receiving the synchronization message, the slave FPGA chip sets the third counter to 0, and updates the count value in the synchronization message to the fourth counter. After the state stabilizes, the system's inherent delay calibration is performed, and then the calibrated value is updated to the third counter.

[0008] Furthermore, the interface chip and the multi-channel interface chip communicate based on the Ethernet protocol.

[0009] Furthermore, the communication cable includes an optical cable.

[0010] Furthermore, the value of X is 10.

[0011] Furthermore, the value of a is 10 7 .

[0012] Beneficial effects: The present invention realizes the clock synchronization and initial scanning synchronization of the main radar array through a communication cable, has a simple structure, is easy to install and maintain; the communication cable can be an optical cable, which is not affected by the external electromagnetic environment and has great practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the structure of an existing four-sided array radar;

[0014] Figure 2 1 is a schematic diagram of the structure of a four-sided array radar according to an embodiment of the present invention;

[0015] Figure 3 It is a principle block diagram of the radar main array surface of an embodiment of the present invention;

[0016] Figure 4 It is a principle block diagram of the radar array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0018] like Figures 2 to 4 As shown, an embodiment of the present invention provides a four-array radar that achieves synchronization based on a single communication cable, including a radar main array surface 1 and three radar secondary array surfaces 2, and the radar main array surface 1 and the three radar secondary array surfaces 2 are respectively connected by a communication cable.

[0019] The radar main array 1 of the embodiment of the present invention includes a main clock chip 11, a main FPGA chip 12, a main radio frequency circuit 13 and a multi-channel interface chip 14. Among them, the main clock chip 11 is connected to the main FPGA chip 12, the main radio frequency circuit 13 and the multi-channel interface chip 14 respectively, and the main clock chip 11 is used to provide clock signals to the main FPGA chip 12, the main radio frequency circuit 13 and the multi-channel interface chip 14 respectively. The main clock chip 11 preferably adopts a high-precision clock chip, and then provides high-precision clock signals to the main FPGA chip 12, the main radio frequency circuit 13 and the multi-channel interface chip 14 respectively. The main FPGA chip 12 is connected to the multi-channel interface chip 14 to control the multi-channel interface chip 14 to realize data reception. The main FPGA chip 12 is connected to the main radio frequency circuit 13 to control the main radio frequency circuit 13 to realize the transmission and reception of detection signals.

[0020] The radar slave face of the embodiment of the present invention includes a slave FPGA chip 21, a slave RF circuit 22, an interface chip 23, a phase-locked loop circuit 24 and a slave clock chip 25. The interface chip 23 and the multi-channel interface chip 14 are both connected to the communication cable, so as to realize the communication between the radar main face 1 and the radar slave face 2. The interface chip 23 is connected to the slave FPGA chip 21, the slave clock chip 25 and the phase-locked loop circuit 24 respectively. The slave clock chip 25 is used to provide a clock signal to the interface chip 23, so that the interface chip 23 works with the clock signal provided by the slave clock chip 25. The slave clock chip 25 does not need to require high precision like the master clock chip 11, and its precision can be lower than the master clock chip 11. The interface chip 23 obtains the line recovery clock based on the communication cable, and the phase-locked loop circuit 24 processes the line recovery clock to obtain a clock signal synchronized with the clock signal sent by the master clock chip 11, and provides the clock signal to the slave FPGA chip 21 and the slave RF circuit 22, and makes the slave FPGA chip 21 and the slave RF circuit 22 work according to the clock signal. This enables the clock frequency synchronization of the radar main array 1 and the three radar slave arrays.

[0021] The transmission time width of the radar generally ranges from a few microseconds to hundreds of microseconds. The shorter the transmission time width, the higher the requirement for initial scanning synchronization. From engineering tests, the interference between the array surfaces can be ignored when it reaches one-tenth of the transmission time width. Taking the radar transmission time width of 1 microsecond as an example, the initial scanning time of the radar should differ by less than 0.1 microsecond. In order to achieve initial scanning synchronization, the main FPGA chip 12 is also used to construct synchronization messages and set the priority of synchronization messages and data messages, where the priority of synchronization messages is higher than the priority of data messages, that is, synchronization messages are sent first. The main FPGA chip 12 uses the clock signal provided by the main clock chip 11 to set the first counter inside it. The unit of the first counter is Xns, where the value of X is preferably 10, that is, the unit of the first counter is 10ms. The main FPGA chip 12 also sets a second counter with a fixed interval of a*Xns based on the first counter, and controls the multi-channel interface chip 14 to send a synchronization message every a*Xns. The synchronization message contains counting information. The value of a is preferably 10 7 , that is, the fixed time interval of the second counter is 100ms.

[0022] The FPGA chip 21 uses the clock signal output by the phase-locked loop circuit 24 to set the third counter inside it. The unit of the third counter is also Xns. The FPGA chip 21 sets the fourth counter with a fixed interval of a*Xns based on the third counter, and sets the receiving port to two receiving queues, one of which is used to process data messages, and the other is used to process synchronization messages. Synchronization messages are not cached and are processed immediately after being received. After receiving the synchronization message, the FPGA chip 21 sets the third counter to 0, and updates the count value in the synchronization message to the fourth counter. After the state is stable, perform the inherent delay calibration of the system, and then update the calibrated value to the third counter.

[0023] The interface chip 23 and the multi-channel interface chip 14 of the embodiment of the present invention preferably communicate based on the Ethernet protocol. At present, most of the chips supporting the Ethernet interface on the market support the function of recovering the clock from the data line. The communication cable preferably adopts an optical cable, which is not affected by the external electromagnetic environment and has great practical value.

[0024] The following is a scenario in an actual test. Referring to the initial counter value between the master FPGA chip 12 and the slave FPGA chip 21 in Table 1, the master FPGA chip 12 and the slave FPGA chip 21 differ by more than ten seconds.

[0025]

[0026] Table 1

[0027] Referring to the counter values ​​between the master FPGA chip 12 and the slave FPGA chip 21 after stabilization in Table 2, the slave FPGA and the master FPGA differ by 20ns.

[0028]

[0029] After testing in various scenarios, the time difference between the radar main array 1 and the radar secondary array 2 is less than 60ns, meeting the most stringent index requirements for four-sided array radars.

[0030] The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, other parts not specifically described belong to the prior art or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A four-sided radar array based on a single communication cable for synchronization, comprising a radar main array and three radar secondary arrays, characterized in that: The radar main array surface is connected to the three radar slave array surfaces through a communication cable respectively. The radar main array surface includes a master clock chip, a master FPGA chip, a master radio frequency circuit and a multi-channel interface chip. The master clock chip is used to provide clock signals to the master FPGA chip, the master radio frequency circuit and the multi-channel interface chip respectively. The radar slave array surface includes a slave FPGA chip, a slave radio frequency circuit, an interface chip, a phase-locked loop circuit and a slave clock chip. The interface chip and the multi-channel interface chip are both connected to the communication cable. The interface chip uses the clock signal provided by the slave clock chip to work, and obtains a line recovery clock based on the communication cable. The phase-locked loop circuit processes the line recovery clock to obtain a clock signal synchronized with the clock signal sent by the master clock chip, and provides it to the slave FPGA chip and the slave radio frequency circuit, so that the slave FPGA chip and the slave radio frequency circuit work according to the clock signal; The master FPGA chip is used to construct a synchronization message, and the priority of the synchronization message is set higher than that of the data message. The master FPGA chip uses the clock signal provided by the master clock chip to set the first counter inside it, and the unit of the first counter is Xns. The master FPGA chip sets a second counter with a fixed interval of a*Xns based on the first counter, and controls the multi-channel interface chip to send a synchronization message every a*Xns, and the synchronization message contains counting information; The slave FPGA chip uses the clock signal output by the phase-locked loop circuit to set the third counter inside it, and the unit of the third counter is Xns. The slave FPGA chip sets a fourth counter with a fixed interval of a*Xns based on the third counter, and sets the receiving port to two receiving queues, one of which is used to process data messages, and the other is used to process synchronization messages. The synchronization messages are not cached. After receiving the synchronization message, the slave FPGA chip sets the third counter to 0, and updates the count value in the synchronization message to the fourth counter. After the state stabilizes, the system's inherent delay calibration is performed, and then the calibrated value is updated to the third counter.

2. The four-sided radar for achieving synchronization based on a single communication cable according to claim 1, characterized in that: The interface chip and the multi-channel interface chip communicate based on the Ethernet protocol.

3. The four-sided radar for achieving synchronization based on a single communication cable according to claim 1, characterized in that: The communications cable comprises an optical cable.

4. The four-array radar for achieving synchronization based on a single communication cable according to claim 1, characterized in that: The value of X is 10.

5. The four-array radar for achieving synchronization based on a single communication cable according to claim 4, characterized in that: The value of a is 10 7 .

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