Data storage device and interface circuit therefor

Abstract

A data storage device and an interface circuit thereof are disclosed. The data storage device can include a memory device including a memory cell for storing data, and an interface circuit coupled between a host device and the memory device as an interface and configured to transmit a transmission signal to the host device. The interface circuit includes a delay circuit configured to generate a delay code, and configured to generate an additional signal to be combined with the transmission signal based on the delay code.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and interest in Korean application No. 10-2021-0032790, filed on March 12, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technologies and implementation methods disclosed in this patent document generally relate to a semiconductor integrated device, and more particularly, to a data storage device and its interface circuit. Background Technology

[0004] Data storage devices may include a memory device in which data is stored and a controller that, in response to requests from a host, transmits data to and receives data from the memory device. The memory device and the controller transmit and receive data via interface circuitry and channels. Numerous studies have been conducted to ensure the integrity of data transmitted and received between the memory device and the controller. Summary of the Invention

[0005] In one embodiment, a data storage device may include: a memory device including memory cells for storing data; and an interface circuit connected between a host device and the memory device as an interface, and configured to transmit a transmission signal to the host device. The interface circuit includes a delay circuit configured to generate a delay code, and configured to generate an additional signal to be combined with the transmission signal based on the delay code.

[0006] In one embodiment, a data storage device may include: an interface circuit including input / output control circuitry; and a memory device configured to transmit data to and receive data from a host via the interface circuitry. The input / output control circuitry includes: a delay circuit configured to generate an internal clock signal and a delay code based on a clock signal transmitted from the host; and a plurality of input / output circuits, each configured to receive the delay code and generate an additional signal that will be combined with a transmission signal to be transmitted to the host.

[0007] In one embodiment, an interface circuit is disposed in a storage device including a memory device. The interface circuit includes: a delay circuit configured to generate an internal clock signal and a delay code based on a clock signal transmitted from a host; and a plurality of input / output circuits, each input / output circuit being configured to receive the delay code and generate an additional signal, which will be combined with a transmission signal to be transmitted to the host. Attached Figure Description

[0008] Figure 1This is a configuration diagram of a data storage device according to an embodiment of the disclosed technology.

[0009] Figure 2 This is a configuration diagram of the interface circuit according to an embodiment of the disclosed technology.

[0010] Figure 3 This is a configuration diagram of a delay-locked loop circuit according to an embodiment of the disclosed technology.

[0011] Figure 4 This is a configuration diagram of the input / output circuit according to an embodiment of the disclosed technology.

[0012] Figure 5 This is a configuration diagram of a pre-emphasis circuit according to an embodiment of the disclosed technology.

[0013] Figure 6A and Figure 6B It is a waveform diagram of the transmission signal with or without pre-emphasis, based on the disclosed technology.

[0014] Figure 7 This is a diagram illustrating a data storage system according to an embodiment of the disclosed technology.

[0015] Figure 8 and Figure 9 This is a diagram illustrating a data processing system according to an embodiment of the disclosed technology.

[0016] Figure 10 This is a diagram illustrating a network system including a data storage device according to embodiments of the disclosed technology.

[0017] Figure 11 This is a block diagram illustrating a non-volatile memory device included in a data storage device according to an embodiment of the disclosed technology. Detailed Implementation

[0018] The embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings.

[0019] As the capacity and speed of data storage devices increase, the number of unit input / output circuits set in the interface circuitry also increases. Therefore, more research has been conducted to accurately and efficiently generate the signals to be provided to each input / output circuit.

[0020] Figure 1 This is a configuration diagram of the data storage device 10 according to an embodiment.

[0021] Data storage device 10 may include a host 100 and a storage device 200 connected to or communicating with the host 100 via a channel 300.

[0022] The host 100 may include a memory controller 110 for controlling the storage device 200 and a first interface circuit 120 as a host-side interface circuit IF_H. The storage device 200 may include a memory device 210 and a second interface circuit 220 as a memory-side interface circuit IF_D.

[0023] The host 100 may include a processor and multiple IPs (Intellectual Property Cores) operating under the processor's control. The host 100 may be a system-on-a-chip (SoC), in which multiple functional blocks, such as IPs, operating various functions are implemented as a single chip. The first interface circuit 120 is also a single IP and may be integrated into the host 100, which is implemented as a SoC.

[0024] The memory device 210 may be implemented using a memory element selected from volatile memory elements such as dynamic random access memory (DRAM), static random access memory (SRAM), or thyristor random access memory (TRAM).

[0025] Memory device 210 may be implemented using memory elements. In some embodiments, the memory element may be a non-volatile memory element such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), or spin-transfer torque magnetic RAM (STT-MRAM). In some embodiments, the memory element may be implemented as a solid-state drive (SSD), memory card, universal flash memory (UFS), or other forms. Memory device 210 may include multiple dies, multiple chips, or multiple packages. Memory device 210 may operate as a single-level cell storing one bit of data in a memory cell or a multi-level cell storing multiple bits of data in a memory cell.

[0026] Channel 300 provides a path for transmitting and receiving signals between host 100 and storage device 200.

[0027] The host 100 can transmit at least one of the following signals to the second interface circuit 220: clock signal CLK, command signal CMD, address signal ADD, or other signals. Furthermore, the host 100 can transmit data DQ to the storage device 200 synchronously with the data strobe signal DQS via the first interface circuit 120.

[0028] The storage device 200 can transmit data DQ to the host 100 synchronously with the data strobe signal DQS through the second interface circuit 220.

[0029] The paths through which host 100 transmits data strobe signals DQS and data DQ to storage device 200 can be substantially the same as, and can be shared with, the paths through which storage device 200 transmits data strobe signals DQS and data DQ to host 100. Therefore, the data strobe signals DQS and data DQ output from host 100 to storage device 200 can be referred to as write DQS and write DQ, and the data strobe signals DQS and data DQ output from storage device 200 to host 100 can be referred to as read DQS and read DQ.

[0030] Since the memory device 210 with high operating speed of double data rate (DDR) or higher uses both the rising and falling edges of the internal clock, it is important to keep the duty cycle of the internal clock at 50%.

[0031] To this end, the second interface circuit 220 can perform a duty cycle correction (DCC) training operation to adjust the duty cycle of an internal clock, generated by an external clock signal CLK received from the host 100, to 50% during power-on operation. In an embodiment, the second interface circuit 220 can perform page reads in DDR mode by transmitting a read enable signal RE_t / c to the memory device 210 in synchronization with the external clock signal CLK during the DCC training operation.

[0032] The storage device 200 may also include a DLL (Delay-Locked Loop) circuit for generating a delay-locked internal clock by correcting the skew of a clock signal whose duty cycle is corrected through DCC training. The DLL circuit can correct the amount of delay in the internal clock signal to compensate for delay components generated during the transmission of the internal clock signal to the data output terminals within the semiconductor memory device.

[0033] In an embodiment, the second interface circuit 220 may include multiple input / output (I / O) control circuits 20. The DLL circuit may be implemented as a digital circuit that generates a delay-locked internal clock signal based on a delay code generated in response to the read enable signal RE_t used in DCC training, and may be integrated into the I / O control circuit 20.

[0034] The second interface circuit 220 can perform pre-emphasis operation to substantially prevent signal attenuation or noise effects that may occur during the transmission of data read from memory device 210 to host 100 via channel 300. Pre-emphasis techniques have been proposed to ensure data integrity by substantially preventing signal distortion through channel 300 by adding an additional signal to the portion of the data to be transmitted in which the logic level is converted. The additional signal for pre-emphasis can be generated by delaying the data to be transmitted for a predetermined time. Some aspects of the disclosed techniques allow for precise control of the delay time and more accurate and efficient delivery of the additional signal.

[0035] In this embodiment, the second interface circuit 220 can perform DCC training and pre-emphasis operations. Therefore, the second interface circuit 220 can generate an additional signal for pre-emphasis based on a delay code generated by the DLL circuitry in the I / O control circuitry 20, by delaying the transmitted signal by a target time (1 unit delay). This additional signal will be combined with the transmitted signal.

[0036] As the capacity of memory device 210 increases, I / O control circuit 20 may include multiple I / O circuits. When transmission signals are delayed for pre-emphasis from outside I / O control circuit 20 and provided to I / O control circuit 20, separate delay circuits need to be added, thus requiring additional area for delay circuits and potentially involving additional work such as changes to the arrangement of IPs.

[0037] According to some embodiments of the disclosed technology, a delay code can be generated in the IO control circuit 20, and this delay code can be used to pre-emphasize transmitted data. Therefore, no separate circuitry or IP is needed for delaying the transmission signal, thereby improving regional efficiency and ensuring the reliability of high-speed operation.

[0038] Figure 2 This is a configuration diagram of the interface circuit according to an embodiment of the disclosed technology. For example, Figure 2 The interface circuit shown corresponds to the second interface circuit 220.

[0039] Reference Figure 2 The second interface circuit 220 according to the embodiment may include an IO control circuit 20, which transmits and receives signals between the transmission drivers Tx1 and Tx2 and the receiving drivers Rx1 and Rx2.

[0040] The IO control circuit 20 may include a DLL circuit 201, a timing adjustment circuit 203, and multiple IO circuits 205 (205-1 to 205-n).

[0041] The DLL circuit 201 can receive the read enable signal RE_t used in the DCC training operation to generate a delay code DLL_CODE for locking the delay amount of the internal clock, and output the delay-locked internal clock signal DQS.

[0042] When the internal clock signal DQS is transmitted to the host 100 during a read operation and the data DQ is transmitted synchronously with the internal clock signal DQS, the operation timing of the host 100 and the storage device 200 can be synchronized.

[0043] The timing adjustment circuit 203 can receive the delay code DLL_CODE and generate a delay control signal DL_CAL. To perform a pre-emphasis operation on the transmitted signal during transmission, the transmitted signal is delayed by 1 unit interval (UI) to generate an additional signal. Therefore, the timing adjustment circuit 203 can generate the delay control signal DL_CAL corresponding to 1UI by halving the delay code DLL_CODE, which corresponds to one clock cycle 2UI.

[0044] Each of the multiple I / O circuits 205-1 to 205-n is configured to receive the delay control signal DL_CAL, generate an additional signal by delaying the transmission signal, combine the additional signal with the transmission signal, and transmit the combined signal to the host 100. The following will refer to... Figure 4 and Figure 5 Detailed description of I / O circuits 205-1 to 205-n.

[0045] Figure 3 This is a configuration diagram of a DLL circuit 201 according to an embodiment of the disclosed technology.

[0046] Reference Figure 3 According to the embodiment, the DLL circuit 201 may include an internal clock generator 2011, a delay code generator 2013, a delay-locked clock generator 2015, and a comparator 2017.

[0047] The internal clock generator 2011 can generate an initial clock signal iRE_t from the clock signal used in DCC training, for example, the read enable signal RE_t.

[0048] The delay code generator 2013 can respond to the enable signal CAL_EN and the comparison signal COMP to output a delay code DLL_CODE corresponding to the amount of delay used to delay the initial clock signal iRE_t.

[0049] In an embodiment, the delay code DLL_CODE can be a multi-digit code indicating the time corresponding to one cycle of the ultimately generated internal clock signal DQS.

[0050] The Delay-Locked Clock Generator 2015 can generate the internal clock signal DQS by delaying the read enable signal RE_t by a time corresponding to the delay code DLL_CODE. For example, the delay code DLL_CODE can delay the read enable signal RE_t by a time corresponding to one cycle of the internal clock signal DQS.

[0051] Comparator 2017 can be configured to send a comparison signal COMP, obtained by comparing the phase of the internal clock signal DQS and the read enable signal RE_t, to delay code generator 2013 in order to update delay code DLL_CODE.

[0052] Figure 3 The DLL circuit 201 shown can be implemented as a digital circuit and can be integrated into the aforementioned IO control circuit 20.

[0053] Figure 4 This is a configuration diagram of IO circuit 205 according to an embodiment of the disclosed technology.

[0054] Reference Figure 4 According to the embodiment, the IO circuit 205 may include a pre-emphasis circuit 260 and an output driver 270.

[0055] The pre-emphasis circuit 260 can receive the transmitted data DIN_REF, the enable signal EQ_EN, the first delay control signal DL_ZERO, and the second delay control signal DL_CAL. When the enable signal EQ_EN is inactive, the pre-emphasis circuit 260 can respond to the first delay control signal DL_ZERO by combining the non-delayed transmitted data DIN_REF with the transmitted data DIN_REF to generate an emphasis signal D_EMP. When the enable signal EQ_EN is active, the pre-emphasis circuit 260 can respond to the second delay control signal DL_CAL by delaying the transmitted data DIN_REF by a delay amount 1UI corresponding to the delay control signal DL_CAL to generate an additional signal, and by combining the additional signal with the transmitted data DIN_REF to generate the emphasis signal D_EMP.

[0056] The output driver 270 can drive the emphasis signal D_EMP to apply the data signal to the output pad DOUT and transmit the emphasis signal D_EMP to the host 100.

[0057] Although not shown in the figure, the output driver 270 may include multiple unit drivers (legs) that are turned on / off according to impedance matching codes.

[0058] In one embodiment, the pre-emphasis circuit 260 may be integrated with the output driver 270. In this case, when the driver in the off state is used as a pre-emphasis circuit between multiple unit drivers constituting the output driver 270, there is no need to add separate circuitry for the pre-emphasis operation, thereby reducing the size of the second interface circuit 220.

[0059] Figure 5 This is a configuration diagram of the pre-emphasis circuit 260 according to an embodiment of the disclosed technology.

[0060] Reference Figure 5 According to the embodiment, the pre-emphasis circuit 260 may include a first selection circuit 261, a second selection circuit 263, a bypass circuit 265, a second delay circuit 267, a first driving circuit 2691, and a second driving circuit 2693.

[0061] The bypass circuit 265 is a delay-free circuit and can be configured to receive the transmitted data DIN_REF via bypass and output the transmitted data DIN_REF as the source data DIN, that is, without delaying the transmitted data DIN_REF.

[0062] The first selection circuit 261 can be configured to select either the transmission data DIN_REF or its inverse signal in response to the enable signal EQ_EN, and provide the selected one to the second delay circuit 267. In an embodiment, the first selection circuit 261 can be configured to select the transmission data DIN_REF when the enable signal EQ_EN is inactive, and to select the inverse transmission data DIN_REF when the enable signal EQ_EN is active.

[0063] The second selection circuit 263 can respond to the enable signal EQ_EN to select either the first delay control signal DL_ZERO or the second delay control signal DL_CAL, and provide the selected one to the second delay circuit 267. In an embodiment, the second selection circuit 263 can be configured to select the first delay control signal DL_ZERO with a delay of 0 when the enable signal EQ_EN is inactive, and to select the second delay control signal DL_CAL with a delay of 1UI when the enable signal EQ_EN is active.

[0064] The second delay circuit 267 can generate an additional signal DIN_ZM by delaying the signal provided from the first selection circuit 261, namely the transmission data DIN_REF or its inverse signal, based on the first delay control signal DL_ZERO or the second delay control signal DL_CAL provided from the second selection circuit 263.

[0065] The first drive circuit 2691 amplifies and outputs the source data DIN provided by the bypass circuit 265. The second drive circuit 2693 drives the additional signal DIN_ZM, combines the additional signal DIN_ZM with the source data DIN, and outputs the accented signal D_EMP.

[0066] Since the second delay control signal DL_CAL is generated from the DLL circuit 201 set in the IO control circuit 20 and provided to each IO circuit 205, an additional signal that does not depend on the PVT change can be generated even without adding a separate delay circuit.

[0067] Therefore, data integrity can be ensured without wasting the area used for delay circuitry.

[0068] Figure 6A and Figure 6B It is a waveform diagram based on whether or not pre-emphasis is performed on the transmitted signal.

[0069] Figure 6A This is a waveform diagram of the transmitted signal when pre-emphasis is not performed, that is, when the enable signal EQ_EN is in an inactive state.

[0070] Since the enable signal EQ_EN is inactive, the first selection circuit 261 outputs non-reverse transmission data DIN-REF, and the second selection circuit 263 selects and outputs the first delay control signal DL_ZERO. Because the first delay control signal DL_ZERO is a signal with a delay of 0, the phase and logic level of the additional signal DIN_ZM output from the second delay circuit 267 are essentially the same as the phase and logic level of the source data DIN output from the bypass circuit 265.

[0071] The source data DIN is driven by the first driver circuit 2691, and the additional signal DIN_ZM is driven by the second driver circuit 2693, enabling the output of the emphasis signal D_EMP, where the high level V of the source data DIN... H and low level V L They were respectively enhanced to VCCQ and VSSQ.

[0072] Figure 6B This is a waveform diagram of the transmitted data during pre-emphasis, i.e. when the enable signal EQ_EN is active.

[0073] Since the enable signal EQ_EN is active, the first selection circuit 261 outputs the inverted transmission data DIN_REF, and the second selection circuit 263 selects and outputs the second delay control signal DL_CAL. Because the second delay control signal DL_CAL is a signal with a delay of 1UI, the second delay circuit 267 delays the inverted transmission data DIN_REF by 1UI and outputs an additional signal DIN_ZM with a delay of 1UI from the source data DIN.

[0074] The source data DIN is driven by the first driver circuit 2691, and the additional signal DIN_ZM is driven by the second driver circuit 2693, so that the emphasis signal D_EMP, which enhances VCCQ and VSSQ, can be applied to the high level V of the source data DIN. H and the high level V of the additional signal DIN_ZM H The overlapping portion and the low level V of the source data DIN L and the low level V of the additional signal DIN_ZM L The overlapping portion (i.e., the point in time when the logic level of the source data DIN is transitioned) is output.

[0075] By adding an additional signal to the high-frequency portion where the bit value of the source data DIN is switched, the attenuation of the transmitted signal transmitted via the channel can be largely prevented.

[0076] Figure 7 This is a diagram illustrating a data storage system 1000 according to an embodiment.

[0077] Reference Figure 7 The data storage system 1000 may include a host device 1100 and a data storage device 1200. In an embodiment, the data storage device 1200 may be configured as a solid-state drive (SSD).

[0078] Data storage device 1200 may include controller 1210, multiple non-volatile memory devices 1220-0 to 1220-n, buffer memory device 1230, power supply 1240, signal connector 1101 and power connector 1103.

[0079] Controller 1210 can control the general operation of data storage device 1200. Controller 1210 may include a host interface unit, a control unit, random access memory used as working memory, an error correction code (ECC) unit, and a memory interface unit. In embodiments, controller 1210 may be configured to... Figure 1 and 2 The memory controller 110 shown.

[0080] The host device 1100 can exchange signals with the data storage device 1200 via the signal connector 1101. These signals may include commands, addresses, data, etc.

[0081] The controller 1210 can analyze and process signals received from the host device 1100. The controller 1210 can control the operation of internal function blocks according to the firmware or software used to drive the data storage device 1200.

[0082] The buffer memory device 1230 can temporarily store data to be stored in at least one of the non-volatile memory devices 1220-0 to 1220-n. Furthermore, the buffer memory device 1230 can temporarily store data read from at least one of the non-volatile memory devices 1220-0 to 1220-n. Under the control of the controller 1210, the data temporarily stored in the buffer memory device 1230 can be transferred to the host device 1100 or at least one of the non-volatile memory devices 1220-0 to 1220-n.

[0083] Non-volatile memory devices 1220-0 to 1220-n can be used as storage media for data storage device 1200. Non-volatile memory devices 1220-0 to 1220-n can be connected to controller 1210 via multiple channels CH0 to CHn, respectively. One or more non-volatile memory devices can be connected to one channel. Non-volatile memory devices connected to each channel can be connected to the same signal bus and data bus.

[0084] Power supply 1240 can provide power input via power connector 1103 to the controller 1210, non-volatile memory devices 1220-0 to 1220-n, and buffer memory device 1230 of data storage device 1200. Power supply 1240 may include an auxiliary power supply. The auxiliary power supply can provide power to allow data storage device 1200 to terminate normally in the event of a sudden power outage. The auxiliary power supply may include a large-capacity capacitor sufficient to store the required charge.

[0085] Depending on the interface scheme between the host device 1100 and the data storage device 1200, the signal connector 1101 can be configured as one or more of various types of connectors.

[0086] Depending on the power supply scheme of the host device 1100, the power connector 1103 can be configured as one or more of various types of connectors.

[0087] Figure 8 This is a diagram illustrating a data processing system 3000 according to an embodiment. (Refer to...) Figure 8 The data processing system 3000 may include a host device 3100 and a memory system 3200.

[0088] The host device 3100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal function blocks for performing the functions of the host device.

[0089] The host device 3100 may include connection terminals 3110, such as sockets, slots, or connectors. The memory system 3200 may mate with the connection terminals 3110.

[0090] The memory system 3200 can be configured as a board, such as a printed circuit board. The memory system 3200 can be referred to as a memory module or a memory card. The memory system 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memory devices 3231 and 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0091] The controller 3210 can control the general operation of the memory system 3200. The controller 3210 can be connected to... Figure 1 and Figure 2 The memory controller 110 shown is configured in the same way.

[0092] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memory devices 3231 and 3232. Furthermore, the buffer memory device 3220 can temporarily store data read from the non-volatile memory devices 3231 and 3232. Under the control of the controller 3210, the data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the non-volatile memory devices 3231 and 3232.

[0093] Non-volatile memory devices 3231 and 3232 can be used as storage media in memory system 3200.

[0094] The PMIC 3240 can supply power to the memory system 3200 via the connection terminal 3250. The PMIC 3240 can manage the power of the memory system 3200 under the control of the controller 3210.

[0095] Connection terminal 3250 can be connected to connection terminal 3110 of host device 3100. Through connection terminal 3250, signals such as commands, addresses, and data, as well as power, can be transmitted between host device 3100 and memory system 3200. Depending on the interface scheme between host device 3100 and memory system 3200, connection terminal 3250 can be configured as one or more of various types. Connection terminal 3250 can be located on one side of memory system 3200, as shown in the figure.

[0096] Figure 9 This is a diagram illustrating a data processing system 4000 according to an embodiment. (Refer to...) Figure 9 The data processing system 4000 may include a host device 4100 and a memory system 4200.

[0097] The host device 4100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal function blocks for performing the functions of the host device.

[0098] The memory system 4200 can be configured in a surface-mount package. The memory system 4200 can be mounted to the host device 4100 via solder balls 4250. The memory system 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory device 4230.

[0099] The controller 4210 can control the general operation of the memory system 4200. The controller 4210 can be connected to... Figure 1 and Figure 2 The memory controller 110 shown is configured in the same way.

[0100] The buffer memory device 4220 can temporarily store data to be stored in the non-volatile memory device 4230. Furthermore, the buffer memory device 4220 can temporarily store data read from the non-volatile memory device 4230. Under the control of the controller 4210, the data temporarily stored in the buffer memory device 4220 can be transferred to the host device 4100 or the non-volatile memory device 4230.

[0101] The non-volatile memory device 4230 can be used as the storage medium of the memory system 4200.

[0102] Figure 10 This is a diagram illustrating a network system 5000 including a data storage device according to an embodiment. (Refer to...) Figure 10 The network system 5000 may include a server system 5300 connected via network 5500 and multiple client systems 5410, 5420 and 5430.

[0103] Server system 5300 can serve data in response to requests from multiple client systems 5410 to 5430. For example, server system 5300 can store data provided by multiple client systems 5410 to 5430. As another example, server system 5300 can provide data to multiple client systems 5410 to 5430.

[0104] Server system 5300 may include host device 5100 and storage system 5200. Storage system 5200 may be configured to... Figure 1 Data storage device 10 shown Figure 7 The data storage device 1200 shown Figure 8 The memory system 3200 shown or Figure 9 The memory system 4200 shown is shown.

[0105] Figure 11 This is a block diagram illustrating a non-volatile memory device 300 included in a data storage device such as data storage device 10 according to an embodiment. (Refer to...) Figure 11 The non-volatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read / write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

[0106] The memory cell array 310 may include memory cells MC, which are arranged in the region where word lines WL1 to WLm and bit lines BL1 to BLn intersect.

[0107] The memory cell array 310 may include a three-dimensional memory array. For example, the three-dimensional memory array has a stacked structure with a direction perpendicular to a flat surface of the semiconductor substrate. Furthermore, a three-dimensional memory array refers to a structure comprising NAND strings, wherein memory cells within the NAND strings are stacked perpendicular to a flat surface of the semiconductor substrate.

[0108] The structure of a three-dimensional memory array is not limited to the embodiments described above. The memory array structure can be formed in a highly integrated manner with both horizontal and vertical orientations. In embodiments, in the NAND strings of a three-dimensional memory array, memory cells are arranged in both horizontal and vertical directions relative to the surface of the semiconductor substrate. The memory cells can be spaced differently to provide varying degrees of integration.

[0109] The row decoder 320 can be connected to the memory cell array 310 via word lines WL1 to WLm. The row decoder 320 can operate under the control of control logic 360. The row decoder 320 can decode addresses provided by external devices (not shown). The row decoder 320 can select and drive word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 can provide word line voltages provided by voltage generator 350 to word lines WL1 to WLm.

[0110] The data read / write block 330 can be connected to the memory cell array 310 via bit lines BL1 to BLn. The data read / write block 330 may include read / write circuits RW1 to RWn corresponding to the bit lines BL1 to BLn, respectively. The data read / write block 330 can be operated according to the control of the control logic 360. The data read / write block 330 can operate as a write driver or a sense amplifier depending on the operating mode. For example, in a write operation, the data read / write block 330 can operate as a write driver to store data provided by an external device into the memory cell array 310. As another example, in a read operation, the data read / write block 330 can operate as a sense amplifier to read data from the memory cell array 310.

[0111] The column decoder 340 can operate under the control of the control logic 360. The column decoder 340 can decode addresses provided by external devices. Based on the decoding result, the column decoder 340 can connect the read / write circuits RW1 to RWn of the data read / write blocks 330 corresponding to bit lines BL1 to BLn to the data input / output lines or data input / output buffers.

[0112] Voltage generator 350 generates voltages for internal operations of the non-volatile memory device 300. The voltages generated by voltage generator 350 can be applied to the memory cells of the memory cell array 310. For example, a programming voltage generated during a programming operation can be applied to the word line of the memory cell to which a programming operation is to be performed. As another example, an erase voltage generated during an erase operation can be applied to the well region of the memory cell to which an erase operation is to be performed. Yet another example, a read voltage generated during a read operation can be applied to the word line of the memory cell to which a read operation is to be performed.

[0113] Control logic 360 can control the general operation of non-volatile memory device 300 based on control signals provided by an external device. For example, control logic 360 can control the operation of non-volatile memory device 300, such as read operations, write operations and erase operations of non-volatile memory device 300.

[0114] Although various embodiments of the disclosed technology have been described and illustrated, modifications may be made to the disclosed and / or illustrated embodiments and other embodiments based on the disclosed and / or illustrated content.

Claims

1. A data storage device, wherein the data storage device stores data under the control of a memory controller of a separate host device, comprising: Memory device, including memory units for storing data; as well as An interface circuit, connected between the host device and the memory device as an interface, transmits transmission signals to the host device. The interface circuit includes a delay circuit for generating a delay code, and generates an additional signal to be combined with the transmitted signal based on the delay code. The interface circuit includes: The pre-emphasis circuit generates the additional signal by delaying the transmitted signal by a delay time determined based on the delay code, and combines the transmitted signal and the additional signal.

2. The data storage device according to claim 1, wherein the delay time corresponds to one unit interval of the transmitted signal, i.e., one UI.

3. The data storage device according to claim 1, wherein the interface circuit includes a plurality of input / output circuits, each input / output circuit including the pre-emphasis circuit, and The delay circuit is integrated with the plurality of input / output circuits.

4. The data storage device of claim 1, wherein the delay circuit generates the delay code based on a clock signal used in duty cycle correction after power-on.

5. The data storage device according to claim 1, wherein the interface circuit includes a plurality of input / output circuits, and The delay code is provided to each of the plurality of input / output circuits.

6. The data storage device according to claim 1, wherein the pre-emphasis circuit includes a bypass circuit and an additional delay circuit, the bypass circuit receiving transmitted data and outputting a corresponding signal without delay, and the additional delay circuit receiving the output signal from the delay circuit and outputting the additional signal.

7. A data storage device, comprising: Interface circuitry, including input / output control circuitry; as well as The memory device transmits data to and receives data from the host via the interface circuit. The input / output control circuit includes: A delay circuit that generates an internal clock signal and a delay code based on a clock signal transmitted from the host computer; and Multiple input / output circuits, each receiving the delay code and generating an additional signal, which is then combined with the transmission signal to be sent to the host. Each of the plurality of input / output circuits includes: The pre-emphasis circuit generates the additional signal by delaying the transmitted signal by a delay time determined based on the delay code.

8. The data storage device of claim 7, wherein the pre-emphasis circuit includes a bypass circuit and an additional delay circuit, the bypass circuit receiving transmitted data and outputting a corresponding signal without delay, and the additional delay circuit receiving the output signal from the delay circuit and outputting the additional signal.

9. The data storage device according to claim 7, wherein the delay time corresponds to one unit interval of the transmitted signal, i.e., one UI.

10. The data storage device of claim 7, wherein the delay circuit is integrated with the plurality of input / output circuits.

11. The data storage device of claim 7, wherein the delay circuit generates the delay code based on a clock signal used in duty cycle correction after power-on.

12. An interface circuit disposed in a storage device including a memory device, the interface circuit comprising: The delay circuit generates an internal clock signal and a delay code based on the clock signal transmitted from the host. as well as Multiple input / output circuits, each receiving the delay code and generating an additional signal, which is then combined with the transmission signal to be sent to the host. Each of the plurality of input / output circuits includes: The pre-emphasis circuit generates the additional signal by delaying the transmitted signal by a delay time determined based on the delay code.

13. The interface circuit of claim 12, wherein the pre-emphasis circuit includes a bypass circuit and an additional delay circuit, the bypass circuit receiving transmitted data and outputting a corresponding signal without delay, and the additional delay circuit receiving the output signal from the delay circuit and outputting the additional signal.

14. The interface circuit according to claim 12, wherein the delay time corresponds to a unit interval of the transmitted signal, i.e., one UI.

15. The interface circuit of claim 12, wherein the delay circuit is integrated with the plurality of input / output circuits.

16. The interface circuit of claim 12, wherein the delay circuit generates the delay code based on a clock signal used in duty cycle correction after power-on operation.

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