in-memory computing signal processing circuit

Abstract

The application provides an in-memory computing signal processing circuit, comprising N column analog multiplier-adder units, N current-voltage converter units and a voltage-to-analog converter unit, the column analog multiplier-adder units are used for receiving K input voltages, performing analog multiplication and addition operations on the input voltages and weights to obtain multiplication and addition currents, the current-voltage converter units are connected with the column analog multiplier-adder units one by one, and are used for receiving the multiplication and addition currents to convert the multiplication and addition currents into voltage signals; the voltage-to-analog converter unit is connected with all the current-voltage converter units, and is used for receiving the voltage signals to convert the voltage signals into digital signals, so that the in-memory computing function is realized through the circuit, and the power consumption and time caused by data transfer are reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an in-memory computation signal processing circuit. Background Technology

[0002] The von Neumann architecture is a classic computer structure. Its operating principle is that when a calculation is needed, the data is first stored in the storage unit, and then the data in the storage unit is moved to the logic unit through instructions. After the calculation is completed in the logic unit, the result is stored back in the storage unit.

[0003] However, as the amount of data in deep learning tasks becomes increasingly massive, the huge number of parameters makes the power consumption and latency costs of traditional von Neumann architecture in transferring large amounts of data between memory and CPU increasingly severe, which is also known as the von Neumann memory bottleneck.

[0004] Therefore, it is necessary to provide a novel in-memory computation signal processing circuit to solve the above-mentioned problems existing in the prior art. Summary of the Invention

[0005] The purpose of this invention is to provide an in-memory computing signal processing circuit that reduces power consumption and time caused by data transfer.

[0006] To achieve the above objectives, the in-memory computation signal processing circuit of the present invention includes:

[0007] There are N column analog multiply-accumulator units, each of which receives K input voltages to perform analog multiply-accumulate operations on the input voltages and weights to obtain a multiply-accumulate current, where N and K are natural numbers greater than 0.

[0008] N current-to-voltage converter units, each connected one-to-one with one of the column analog multiplier-accumulator units, are used to receive the multiply-accumulate current and convert it into a voltage signal; and

[0009] A voltage analog-to-digital converter unit, connected to all the current-to-voltage converter units, is used to receive the voltage signal and convert the voltage signal into a digital signal.

[0010] The beneficial effects of the in-memory computing signal processing circuit are as follows: it includes N column analog multiply-accumulator units, K current-to-voltage converter units and voltage-to-digital converter units, and realizes the in-memory computing function through the circuit, reducing the power consumption and time caused by data transfer.

[0011] Optionally, the column analog multiplier-adder unit includes K analog multiplication units. Each analog multiplication unit includes a latch unit, a first inverter, a logic operation unit, and an output unit. The input terminal of the latch unit is used to receive weights, and the output terminal of the latch unit is connected to the first input terminal of the logic operation unit. The input terminal of the first inverter is used to receive input voltage, and the output terminal of the first inverter is connected to the second input terminal of the logic operation unit. The output terminal of the logic operation unit is connected to the control terminal of the output unit, and the output terminal of the output unit outputs a multiplication current.

[0012] Optionally, the latch unit includes a first MOS transistor and a latch. The source of the first MOS transistor is used to receive weights, the drain of the first MOS transistor is connected to the input terminal of the latch, the output terminal of the latch is connected to the first input terminal of the logic operation unit, and the latch is used to store the weights.

[0013] Optionally, the output unit includes a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor. The source of the fourteenth MOS transistor is connected to the negative terminal of the power supply, the gate of the fourteenth MOS transistor is connected to a bias voltage, the drain of the fourteenth MOS transistor is connected to the source of the thirteenth MOS transistor, the gate of the thirteenth MOS transistor is connected to the output terminal of the logic operation unit, the drain of the thirteenth MOS transistor is connected to the source of the twelfth MOS transistor, the gate of the twelfth MOS transistor is connected to a preset voltage, and the drain of the twelfth MOS transistor outputs the multiplication current.

[0014] Optionally, the current-to-voltage converter unit includes a first voltage input arithmetic unit, a second voltage input arithmetic unit, a third voltage input arithmetic unit, a multiply-accumulate current carrying unit, and an arithmetic result processing unit. The multiply-accumulate current carrying unit is connected to the analog multiplier-accumulator unit, the first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit, and is used to receive the multiply-accumulate current. The first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit are used to proportionally replicate the multiply-accumulate current. The arithmetic result processing unit is connected to the first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit, and is used to obtain the voltage signal based on the output current of the first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit.

[0015] Optionally, the multiply-accumulate current carrying unit includes a fifteenth MOS transistor and a sixteenth MOS transistor. The drain of the fifteenth MOS transistor is connected to the column analog multiply-accumulate unit to receive the multiply-accumulate current. The gate of the fifteenth MOS transistor is connected to a bias voltage. The source of the fifteenth MOS transistor is connected to the drain and gate of the sixteenth MOS transistor. The source of the sixteenth MOS transistor is connected to the positive power supply.

[0016] Optionally, the first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit each include a first transmission gate, a second transmission gate, a seventeenth MOS transistor, an eighteenth MOS transistor, and a nineteenth MOS transistor. The input terminal of the first transmission gate is connected to the gate of the sixteenth MOS transistor, and the output terminal of the first transmission gate is connected to the gate of the seventeenth MOS transistor and the drain of the eighteenth MOS transistor. The gate of the eighteenth MOS transistor is connected to a control signal, and the sources of the eighteenth MOS transistor and the seventeenth MOS transistor are both connected to the positive terminal of the power supply. The drain of the seventeenth MOS transistor is connected to the source of the nineteenth MOS transistor, the gate of the nineteenth MOS transistor is connected to a bias voltage, and the drain of the nineteenth MOS transistor is connected to the input terminal of the second transmission gate.

[0017] Optionally, the calculation result processing unit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a capacitor reset unit, and a buffer unit. One end of the first capacitor is connected to the buffer unit, the output terminal of the second transmission gate in the first voltage input calculation unit, one end of the fourth capacitor, and one end of the fifth capacitor. The other end of the fourth capacitor is connected to the output terminal of the second transmission gate in the second voltage input calculation unit and one end of the second capacitor. The other end of the fifth capacitor is connected to the output terminal of the second transmission gate in the third voltage input calculation unit and one end of the third capacitor. The other ends of the first capacitor, the second capacitor, and the third capacitor are connected to the negative terminal of the power supply. The capacitor reset unit is connected to the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor, and is used to reset the voltages of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor.

[0018] Optionally, the buffer unit includes a twentieth MOS transistor and a bias current source. The gate of the twentieth MOS transistor is connected to one end of the first capacitor, the drain of the twentieth MOS transistor is connected to the positive terminal of the power supply, the source of the twentieth MOS transistor is connected to the positive terminal of the bias current source, the negative terminal of the bias current source is connected to the negative terminal of the power supply, and the voltage signal is output at the connection between the source of the twentieth MOS transistor and the positive terminal of the bias current source.

[0019] Optionally, the capacitor reset unit includes a 21st MOS transistor, a 22nd MOS transistor, and a 23rd MOS transistor. The drain of the 21st MOS transistor is connected to one end of the first capacitor, the drain of the 22nd MOS transistor is connected to one end of the second capacitor, and the drain of the 23rd MOS transistor is connected to one end of the third capacitor. The gate of the 21st MOS transistor is connected to a first reset signal, the gate of the 22nd MOS transistor is connected to a second reset signal, and the gate of the 23rd MOS transistor is connected to a third reset signal. The sources of the 21st MOS transistor, the 22nd MOS transistor, and the 23rd MOS transistor are connected to the negative power supply terminal. Attached Figure Description

[0020] Figure 1 This is a block diagram of the in-memory computation signal processing circuit in some embodiments of the present invention;

[0021] Figure 2 This is a schematic diagram of a column analog multiplier-accumulator unit located in the first column in some embodiments of the present invention;

[0022] Figure 3 This is a circuit diagram of the analog multiplication unit in some embodiments of the present invention;

[0023] Figure 4 This is a circuit diagram of a current-to-voltage conversion unit in some embodiments of the present invention;

[0024] Figure 5 This is an enlarged circuit diagram of the first voltage input arithmetic unit in some embodiments of the present invention;

[0025] Figure 6 This is an enlarged circuit diagram of the second voltage input arithmetic unit in some embodiments of the present invention;

[0026] Figure 7 This is an enlarged circuit diagram of the third voltage input arithmetic unit in some embodiments of the present invention;

[0027] Figure 8 This is a schematic diagram of an in-memory computation signal processing circuit in some embodiments of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0029] To address the problems existing in the prior art, embodiments of the present invention provide an in-memory computation signal processing circuit. (Refer to...) Figure 1 The in-memory computation signal processing circuit 100 includes N column analog multiply-accumulator units 101, N current-to-voltage converter units 102, and voltage-to-digital converter units 103. Each column analog multiply-accumulator unit 101 receives K input voltages and performs analog multiplication-accumulation operations on the input voltages and weights to obtain a multiply-accumulated current. The current-to-voltage converter units 102 are connected one-to-one with the column analog multiply-accumulator units 101 and receive the multiply-accumulated current to convert it into a voltage signal. The voltage-to-digital converter units 103 are connected to all the current-to-voltage converter units 102 and receive the voltage signal to convert it into a digital signal. Here, N and K are natural numbers greater than 0.

[0030] Figure 2 This is a schematic diagram of a column-simulated multiplier-accumulator unit located in the first column in some embodiments of the present invention. (Refer to...) Figure 2 The column analog multiply-accumulator unit includes K analog multiplication units, where K is a positive integer. The first analog multiplication unit is connected to the first word line WL1 and the bit line BL1, the second analog multiplication unit is connected to the second word line WL2 and the bit line BL1, and the Kth analog multiplication unit is connected to the Kth word line WLK and the bit line BL1.

[0031] Figure 3 This is a circuit diagram of an analog multiplication unit in some embodiments of the present invention. (Refer to...) Figure 3The analog multiplication unit 1011 includes a latch unit 10112, a first inverter 10113, a logic operation unit 10114, and an output unit 10115. The input terminal of the latch unit 10112 is used to receive the weight W. The output terminal of the latch unit 10112 is connected to the first input terminal of the logic operation unit 10114. The input terminal of the first inverter 10113 is used to receive the input voltage VL. The output terminal of the first inverter 10113 is connected to the second input terminal of the logic operation unit 10114. The output terminal of the logic operation unit 10114 is connected to the control terminal of the output unit 10115. The output terminal IOUT of the output unit 10115 outputs the multiplication current.

[0032] Reference Figure 3 The output unit 10115 includes a twelfth MOSFET M12, a thirteenth MOSFET M13, and a fourteenth MOSFET M14. The source of the fourteenth MOSFET M14 is connected to the negative terminal of the power supply, and the gate of the fourteenth MOSFET M14 is connected to the bias voltage VBIAS. The drain of the fourteenth MOSFET M14 is connected to the source of the thirteenth MOSFET M13. The gate of the thirteenth MOSFET M13 is connected to the output terminal of the logic operation unit 10114. The drain of the thirteenth MOSFET M13 is connected to the source of the twelfth MOSFET M12. The gate of the twelfth MOSFET M12 is connected to the preset voltage VCOPY. The drain of the twelfth MOSFET M12 serves as the output terminal IOUT of the output unit 10115, outputting the multiplication current.

[0033] Reference Figure 3 The latch unit 10112 includes a first MOS transistor M1 and a latch 101121. The source of the first MOS transistor M1 is used to receive the weight W. The drain of the first MOS transistor M1 is connected to the input terminal of the latch 101121. The gate of the first MOS transistor is connected to the weight writing control signal WS. The output terminal of the latch 101121 is connected to the first input terminal of the logic operation unit 10114. The latch 101121 is used to store the weight W.

[0034] Reference Figure 3 The latch 101121 includes a second inverter 1011211 and a third inverter 1011212. The input terminal of the second inverter 1011211 and the output terminal of the third inverter 1011212 are connected to the drain of the first MOS transistor M1. The output terminal of the second inverter 1011211 and the input terminal of the third inverter 1011212 are connected to the first input terminal of the logic operation unit 10114.

[0035] Reference Figure 3 The first inverter 10113 includes a sixth MOSFET M6 and a seventh MOSFET M7. The gate of the sixth MOSFET M6 is connected to the gate of the seventh MOSFET M7, serving as the input terminal of the first inverter 10113. The source of the sixth MOSFET M6 is connected to the positive power supply VDD. The drain of the sixth MOSFET M6 is connected to the drain of the seventh MOSFET M7, serving as the output terminal of the first inverter 10113. The source of the seventh MOSFET M7 is connected to the negative power supply.

[0036] Reference Figure 3 The second inverter 1011211 includes a second MOSFET M2 and a third MOSFET M3. The gate of the second MOSFET M2 is connected to the gate of the third MOSFET M3, serving as the input terminal of the second inverter 1011211. The source of the second MOSFET M2 is connected to the positive power supply VDD. The drain of the second MOSFET M2 is connected to the drain of the third MOSFET M3, serving as the output terminal of the second inverter 1011211. The source of the third MOSFET M3 is connected to the negative power supply.

[0037] Reference Figure 3 The third inverter 1011212 includes a fourth MOSFET M4 and a fifth MOSFET M5. The gate of the fourth MOSFET M4 is connected to the gate of the fifth MOSFET M5, serving as the input terminal of the third inverter 1011212. The source of the fourth MOSFET M4 is connected to the positive power supply VDD. The drain of the fourth MOSFET M4 is connected to the drain of the fifth MOSFET M5, serving as the output terminal of the third inverter 1011212. The source of the fifth MOSFET M5 is connected to the negative power supply.

[0038] Reference Figure 3 The logic operation unit 10114 includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, and an eleventh MOSFET M11. The gate of the eighth MOSFET M8 is connected to the gate of the tenth MOSFET M10, serving as the first input terminal of the logic operation unit 10114. The gate of the ninth MOSFET M9 is connected to the gate of the eleventh MOSFET M11, serving as the second input terminal of the logic operation unit 10114. The source of the eighth MOSFET M8 is connected to the positive power supply VDD. The drain of the eighth MOSFET M8 is connected to the source of the ninth MOSFET M9. The drain of the ninth MOSFET M9 is connected to the drains of the tenth MOSFET M10 and the eleventh MOSFET M11, serving as the output terminal of the logic operation unit 10114. The sources of the tenth MOSFET M10 and the eleventh MOSFET M11 are connected to the negative power supply.

[0039] In some embodiments, the gate of the eighth MOS transistor and the gate of the tenth MOS transistor are connected as the second input terminal of the logic operation unit, and the gate of the ninth MOS transistor and the ridge of the eleventh MOS transistor are connected as the first input terminal of the logic operation unit.

[0040] Figure 4 This is a circuit diagram of a current-to-voltage conversion unit in some embodiments of the present invention. Figure 5 This is an enlarged circuit diagram of the first voltage input arithmetic unit in some embodiments of the present invention. Figure 6 This is an enlarged circuit diagram of the second voltage input arithmetic unit in some embodiments of the present invention. Figure 7 This is an enlarged circuit diagram of the third voltage input arithmetic unit in some embodiments of the present invention. (Refer to...) Figure 4 , Figure 5 , Figure 6 and Figure 7 The current-to-voltage converter unit 102 includes a first voltage input arithmetic unit 1021, a second voltage input arithmetic unit 1022, a third voltage input arithmetic unit 1023, a multiply-accumulate current carrying unit 1024, and an arithmetic result processing unit 1025. The multiply-accumulate current carrying unit 1024 is connected to the column analog multiplier unit, the first voltage input arithmetic unit 1021, the second voltage input arithmetic unit 1022, and the third voltage input arithmetic unit 1023, and is used to receive the multiply-accumulate current I. The first voltage input arithmetic unit 1021, the second voltage input arithmetic unit 1022, and the third voltage input arithmetic unit 1023 are used to proportionally replicate the multiply-accumulate current I. The arithmetic result processing unit 1025 is connected to the first voltage input arithmetic unit 1021, the second voltage input arithmetic unit 1022, and the third voltage input arithmetic unit 1023, and is used to obtain the voltage signal based on the output current of the first voltage input arithmetic unit 1021, the second voltage input arithmetic unit 1022, and the third voltage input arithmetic unit 1023.

[0041] Reference Figure 4 The multiply-accumulate current carrying unit 1024 includes a fifteenth MOS transistor M15 and a sixteenth MOS transistor M16. The drain of the fifteenth MOS transistor M15 is connected to the column analog multiply-accumulate unit to receive the multiply-accumulate current I. The gate of the fifteenth MOS transistor M15 is connected to the bias voltage VBIAS. The source of the fifteenth MOS transistor M15 is connected to the drain and gate of the sixteenth MOS transistor M16. The source of the sixteenth MOS transistor M16 is connected to the positive power supply VDD.

[0042] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7 The first voltage input arithmetic unit 1021, the second voltage input arithmetic unit 1022, and the third voltage input arithmetic unit 1023 each include a first transmission gate 10211, a second transmission gate 10212, a seventeenth MOSFET M17, an eighteenth MOSFET M18, and a nineteenth MOSFET M19. The input terminal of the first transmission gate 10212 is connected to the gate of the sixteenth MOSFET M16, and the output terminal of the first transmission gate 10211 is connected to the gate of the seventeenth MOSFET M17 and the drain of the eighteenth MOSFET M18. The gate of the eighteenth MOSFET M18 is connected to a control signal, and the sources of the eighteenth MOSFET M18 and the seventeenth MOSFET M17 are both connected to the positive power supply VDD. The drain of the seventeenth MOSFET M17 is connected to the source of the nineteenth MOSFET M19, the gate of the nineteenth MOSFET M19 is connected to a bias voltage, and the drain of the nineteenth MOSFET M19 is connected to the input terminal of the second transmission gate 10212.

[0043] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7 The first transmission gate 10211 includes a twenty-fourth MOSFET M24 and a twenty-fifth MOSFET M25. The source of the twenty-fourth MOSFET M24 is connected to the source of the twenty-fifth MOSFET M25 and serves as the input terminal of the first transmission gate 10211. The drain of the twenty-fourth MOSFET M24 is connected to the drain of the twenty-fifth MOSFET M25 and serves as the output terminal of the first transmission gate 10211.

[0044] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7 The second transmission gate 10212 includes a twenty-sixth MOSFET M26 and a twenty-seventh MOSFET M27. The source of the twenty-sixth MOSFET M26 and the source of the twenty-seventh MOSFET M27 are connected to serve as the input terminal of the second transmission gate 10212, and the drain of the twenty-sixth MOSFET M26 and the drain of the twenty-seventh MOSFET M27 are connected to serve as the output terminal of the second transmission gate 10212.

[0045] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7The control signals include a first control sub-signal S1, a fifth control sub-signal S3, and a ninth control sub-signal S5. In the first voltage input arithmetic unit 1021, the gate of the eighteenth MOS transistor M18 is connected to the first control sub-signal S1, the gate of the twenty-fourth MOS transistor M24 is connected to the first control sub-signal S1, the gate of the twenty-fifth MOS transistor M25 is connected to the third control sub-signal S1_BAR, the gate of the twenty-sixth MOS transistor M26 is connected to the fourth control sub-signal S2_BAR, and the gate of the twenty-seventh MOS transistor M27 is connected to the second control sub-signal S2.

[0046] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7 The control signals include a first control sub-signal S1, a fifth control sub-signal S3, and a ninth control sub-signal S5. In the second voltage input arithmetic unit 1022, the gate of the eighteenth MOS transistor M18 is connected to the fifth control sub-signal S3, the gate of the twenty-fourth MOS transistor M24 is connected to the fifth control sub-signal S3, the gate of the twenty-fifth MOS transistor M25 is connected to the seventh control sub-signal S3_BAR, the gate of the twenty-sixth MOS transistor M26 is connected to the eighth control sub-signal S4_BAR, and the gate of the twenty-seventh MOS transistor M27 is connected to the sixth control sub-signal S4.

[0047] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7 The control signals include a first control sub-signal S1, a fifth control sub-signal S3, and a ninth control sub-signal S5. In the third voltage input arithmetic unit 1023, the gate of the eighteenth MOS transistor M18 is connected to the ninth control sub-signal S5, the gate of the twenty-fourth MOS transistor M24 is connected to the ninth control sub-signal S5, the gate of the twenty-fifth MOS transistor M25 is connected to the eleventh control sub-signal S5_BAR, the gate of the twenty-sixth MOS transistor M26 is connected to the twelfth control sub-signal S6_BAR, and the gate of the twenty-seventh MOS transistor M27 is connected to the tenth control sub-signal S6.

[0048] Reference Figure 4 , Figure 5 , Figure 6 and Figure 7The calculation result processing unit 1025 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a capacitor reset unit (not shown in the figure), and a buffer unit (not shown in the figure). One end of the first capacitor C1 is connected to the buffer unit, the output terminal of the second transmission gate 10212 in the first voltage input calculation unit 1021, one end of the fourth capacitor C4, and one end of the fifth capacitor C5. The other end of the fourth capacitor C4 is connected to the output terminal of the second transmission gate 10212 in the second voltage input calculation unit 1022 and one end of the second capacitor C2. The other end of the fifth capacitor C5 is connected to the output terminal of the second transmission gate 10212 in the third voltage input arithmetic unit 1023 and one end of the third capacitor C3. The other ends of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are connected to the negative terminal of the power supply. The capacitor reset unit is connected to the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5, and is used to reset the voltages of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5.

[0049] Reference Figure 4 The buffer unit includes a twentieth MOSFET M20 and a bias current source IBIAS. The gate of the twentieth MOSFET M20 is connected to one end of the first capacitor C1. The drain of the twentieth MOSFET M20 is connected to the positive terminal of the power supply. The source of the twentieth MOSFET M20 is connected to the positive terminal of the bias current source IBIAS. The negative terminal of the bias current source IBIAS is connected to the negative terminal of the power supply. The voltage signal VC is output at the connection between the source of the twentieth MOSFET M20 and the positive terminal of the bias current source IBIAS.

[0050] Reference Figure 4 The capacitor reset unit includes a 21st MOSFET M2, a 22nd MOSFET M22, and a 23rd MOSFET M23. The drain of the 21st MOSFET M21 is connected to one end of the first capacitor C1, the drain of the 22nd MOSFET M22 is connected to one end of the second capacitor C2, and the drain of the 23rd MOSFET M23 is connected to one end of the third capacitor C3. The gate of the 21st MOSFET M21 is connected to the first reset signal RS1, the gate of the 22nd MOSFET M22 is connected to the second reset signal RS2, and the gate of the 23rd MOSFET M23 is connected to the third reset signal RS3. The sources of the 21st MOSFET M21, the 22nd MOSFET M22, and the 23rd MOSFET M23 are connected to the negative power supply.

[0051] In some embodiments, the first MOS transistor, the third MOS transistor, the fifth MOS transistor, the seventh MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, the twenty-fifth MOS transistor, the twenty-sixth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, the twenty-third MOS transistor, and the twenty-second MOS transistor are all NMOS transistors, and the remaining MOS transistors are all PMOS transistors.

[0052] Figure 8 This is a schematic diagram of the in-memory computation signal processing circuit in some embodiments of the present invention. (Refer to...) Figure 8 The in-memory computation signal processing circuit includes N column analog multiplier-accumulator units 101, N current-to-voltage converter units 102, and voltage-to-digital converter units 103.

[0053] Reference Figure 8 The first column analog multiply-accumulator unit 101 to the Nth column analog multiply-accumulator unit 101 each include K analog multiplication units 1011, where K is a positive integer.

[0054] Reference Figure 8 In the first analog multiplier-adder unit 101, the input terminal of the first inverter in the first analog multiplier unit 1011 is connected to the first word line WL1, and the drain of the twelfth MOS transistor in the first analog multiplier unit 1011 is connected to the bit line BL1. In the second analog multiplier unit 1011, the input terminal of the first inverter is connected to the second word line WL2, and the drain of the twelfth MOS transistor in the second analog multiplier unit 1011 is connected to the bit line BL1. In the Kth analog multiplier unit 1011, the input terminal of the first inverter is connected to the Kth word line WLK, and the drain of the twelfth MOS transistor in the Kth analog multiplier unit 1011 is connected to the bit line BL1.

[0055] Reference Figure 8 In the Nth analog multiplier-adder unit 101, the input terminal of the first inverter in the first analog multiplier unit 1011 is connected to the first word line WL1, and the drain of the twelfth MOS transistor in the first analog multiplier unit 1011 is connected to the bit line BLN. The input terminal of the first inverter in the second analog multiplier unit 1011 is connected to the second word line WL2, and the drain of the twelfth MOS transistor in the second analog multiplier unit 1011 is connected to the bit line BLN. The input terminal of the first inverter in the Kth analog multiplier unit 1011 is connected to the Kth word line WLK, and the drain of the twelfth MOS transistor in the Kth analog multiplier unit 1011 is connected to the bit line BLN.

[0056] Reference Figure 8 The drain of the fifteenth MOS transistor in the first current-to-voltage converter unit is connected to the first bit line BL1, and the drain of the fifteenth MOS transistor in the Nth current-to-voltage converter unit is connected to the Nth bit line BLN.

[0057] Reference Figure 8 The source of the twentieth MOS transistor in the first current-to-voltage converter unit 102 is connected to the voltage-to-analog-to-digital converter unit 103, and the source of the twentieth MOS transistor in the Nth current-to-voltage converter unit 102 is connected to the voltage-to-analog-to-digital converter unit 103.

[0058] Reference Figure 8 The voltages on the first word line WL1, the second word line WL2, and the Kth word line WLK are the input voltages VL1, VL2, and VLK, respectively.

[0059] Reference Figure 3 and Figure 8 Weight W1 is stored in the latch of the first analog multiplication unit 1011, and the fifteenth MOS transistor of the first analog multiplication unit 1011 controls whether a new weight is written to the latch 101121 of the first analog multiplication unit 1011; weight W2 is stored in the latch 101121 of the second analog multiplication unit 1011, and the fifteenth MOS transistor M15 of the second analog multiplication unit 1011 controls whether a new weight is written to the latch 101121 of the second analog multiplication unit 1011; and so on, weight WK is stored in the latch 101121 of the Kth analog multiplication unit 1011, and the fifteenth MOS transistor M15 of the Kth analog multiplication unit 1011 controls whether a new weight is written to the latch 101121 of the Kth analog multiplication unit 1011.

[0060] Reference Figure 3 and Figure 8 The input voltage VL1 is inverted by the first inverter 10113 to become an inverted voltage VL1_BAR. Then, the logic operation unit 10114 performs a OR-NOT operation on the inverted voltage VL1_BAR and the weight W11 to obtain a voltage value VF11, which is used as the gate voltage input of the thirteenth MOSFET M13. When the thirteenth MOSFET M13 is turned on, the multiplicative current IOUT11 at the drain of the twelfth MOSFET M12 is VL1*W11*100nA. Therefore, the multiplicative current I on the first bit line BL1 is (VL1*W11+VL2*W21+...VLK*WL1)*100nA.

[0061] In some embodiments, the analog multiplication units connected to the same word line all receive the same input voltage. Because the weights stored in different analog multiplication units are the same or different, they perform the same or different operations and thus output the same or different multiply-accumulate currents.

[0062] This application implements in-memory computing functionality. If the product of the weight and the input voltage is 1, the output current is fixed at 100nA. There is no current error caused by the resistance instability of the memristor, thus increasing the accuracy and stability of the current output. Furthermore, the current-to-voltage conversion unit uses voltage input bits of different digits for quantization with custom precision, which greatly increases the quantization speed while sacrificing some minor precision, and at the same time improves the energy efficiency ratio of the circuit.

[0063] Reference Figure 4 and Figure 8 The multiply-accumulated current I enters the first current-to-voltage conversion unit 102. The fifteenth MOSFET M15, the sixteenth MOSFET M16, the seventeenth MOSFET M17 in the first voltage input arithmetic unit 1021, and the nineteenth MOSFET M19 in the first voltage input arithmetic unit 1021 form a first current mirror, which proportionally replicates the multiply-accumulated current I into a first mirror current IC1. The fifteenth MOSFET M15, the sixteenth MOSFET M16, the seventeenth MOSFET M17 in the second voltage input arithmetic unit 1022, and the nineteenth MOSFET M19 in the second voltage input arithmetic unit 1022 form a second current mirror, which proportionally replicates the multiply-accumulated current I into a second mirror current IC2. The fifteenth MOSFET M15, the sixteenth MOSFET M16, the seventeenth MOSFET M17 in the third voltage input arithmetic unit 1023, and the nineteenth MOSFET M19 in the third voltage input arithmetic unit 1023 form a third current mirror, which proportionally replicates the multiply-accumulated current I into a third mirror current IC3. The replication ratios of the first current mirror, the second current mirror, and the third current mirror are different.

[0064] Reference Figure 4 and Figure 8The first voltage input calculation unit 1021 corresponds to the calculation part of VL1[7:6] of input voltage VL1, the calculation part of VL2[7:6] of input voltage VL2, and so on, as well as the calculation part of VLK[7:6] of input voltage VLK; the second voltage input calculation unit 1022 corresponds to the calculation part of VL1[5:3] of input voltage VL1, the calculation part of VL2[5:3] of input voltage VL2, and so on, as well as the calculation part of VLK[5:3] of input voltage VLK; the third voltage input calculation unit 1023 corresponds to the calculation part of VL1[2:0] of input voltage VL1, the calculation part of VL2[2:0] of input voltage VL2, and so on, as well as the calculation part of VLK[2:0] of input voltage VLK.

[0065] Reference Figure 4 The first transmission gate 10211 and the second transmission gate 10212 in the first voltage input arithmetic unit 1021, and the eighteenth MOS transistor M18 constitute the current sampling switch of the first voltage input arithmetic unit 1021. The current flows through the corresponding first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5 through the first control sub-signal S1, the second control sub-signal S2, the third control sub-signal S1_BAR, the fourth control sub-signal S2_BAR, the fifth control sub-signal S3, the sixth control sub-signal S4, the seventh control sub-signal S3_BAR, the eighth control sub-signal S4_BAR, the ninth control sub-signal S5, the tenth control sub-signal S6, the eleventh control sub-signal S5_BAR, and the twelfth control sub-signal S6_BAR to achieve sampling, charging, and accumulation. Each sampling allows current to flow through the corresponding capacitor. The voltage increase DELTAV from the capacitor's voltage value VCC can be expressed as DELTAV = (I * DELTAt) / C, where DELTAt is the sampling time, I is the current flowing through the capacitor, and C is the capacitance. The voltage value DELTAV serves as the gate voltage of the twentieth MOS transistor. The converted voltage signal VC1 is output via the buffer unit. Voltage signal VC1 includes the first sub-voltage signal V11 obtained by the first voltage input arithmetic unit 1021, the second sub-voltage signal V12 obtained by the second voltage input arithmetic unit 1022, and the third sub-voltage signal V13 obtained by the third voltage input arithmetic unit 1023.

[0066] Reference Figure 4For the first voltage input calculation unit 1021, the second voltage input calculation unit 1022 and the third voltage input calculation unit 1023, after the calculation of each part of the input voltage is completed, the voltages of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 are reset through the first reset signal RS1, the second reset signal RS2 and the third reset signal RS3.

[0067] In some embodiments, the first sub-voltage signal V11 is quantized into a first digital signal D11, the second voltage signal V12 is quantized into a second digital signal D12, and the third voltage signal V13 is quantized into a third digital signal D13, wherein the bit weight corresponding to the first digital signal D11 is 2. 5 The bit weight corresponding to the second digital signal D12 is 2. 3 The bit weight corresponding to the third digital signal D13 is 2. 0 The first digital signal D11, the second digital signal D12, and the third digital signal D13 are multiplied by their corresponding bit weights and then added together to obtain the final digital signal DOUT output by the voltage analog-to-digital converter unit. This can be expressed by the formula DOUT = D11 * 2. 5 +D12*2 3 +D13*2 0 .

[0068] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. An in-memory computation signal processing circuit, characterized in that, include: There are N column-based analog multiply-accumulator units, each receiving K input voltages to perform analog multiplication and addition operations on the input voltages and weights to obtain a multiply-accumulated current, where N and K are natural numbers greater than 0. Each column-based analog multiply-accumulator unit includes K analog multiplication units, each comprising a latch unit, a first inverter, a logic operation unit, and an output unit. The input of each latch unit receives the weights, and its output is connected to the first input of the logic operation unit. The input of the first inverter receives the input voltages, and its output is connected to the second input of the logic operation unit. The output of the logic operation unit is connected to the control terminal of the output unit, and the output of the output unit outputs the multiplication current. N current-to-voltage converter units, each connected to a corresponding column of analog multiply-accumulator units, are used to receive the multiply-accumulator current and convert it into a voltage signal. as well as A voltage analog-to-digital converter unit, connected to all the current-to-voltage converter units, is used to receive the voltage signal and convert the voltage signal into a digital signal.

2. The in-memory computation signal processing circuit according to claim 1, characterized in that, The latch unit includes a first MOS transistor and a latch. The source of the first MOS transistor is used to receive weights, the drain of the first MOS transistor is connected to the input terminal of the latch, and the output terminal of the latch is connected to the first input terminal of the logic operation unit. The latch is used to store the weights.

3. The in-memory computation signal processing circuit according to claim 1, characterized in that, The output unit includes a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor. The source of the fourteenth MOS transistor is connected to the negative terminal of the power supply, the gate of the fourteenth MOS transistor is connected to a bias voltage, the drain of the fourteenth MOS transistor is connected to the source of the thirteenth MOS transistor, the gate of the thirteenth MOS transistor is connected to the output terminal of the logic operation unit, the drain of the thirteenth MOS transistor is connected to the source of the twelfth MOS transistor, the gate of the twelfth MOS transistor is connected to a preset voltage, and the drain of the twelfth MOS transistor outputs the multiplication current.

4. The in-memory computation signal processing circuit according to claim 1, characterized in that, The current-to-voltage converter unit includes a first voltage input arithmetic unit, a second voltage input arithmetic unit, a third voltage input arithmetic unit, a multiply-accumulate current carrying unit, and an arithmetic result processing unit. The multiply-accumulate current carrying unit is connected to the analog multiplier-accumulator unit, the first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit, and is used to receive the multiply-accumulate current. The first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit are used to proportionally replicate the multiply-accumulate current. The arithmetic result processing unit is connected to the first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit, and is used to obtain the voltage signal based on the output current of the first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit.

5. The in-memory computation signal processing circuit according to claim 4, characterized in that, The multiply-accumulate current carrying unit includes a fifteenth MOS transistor and a sixteenth MOS transistor. The drain of the fifteenth MOS transistor is connected to the column analog multiply-accumulate unit to receive the multiply-accumulate current. The gate of the fifteenth MOS transistor is connected to a bias voltage. The source of the fifteenth MOS transistor is connected to the drain and gate of the sixteenth MOS transistor. The source of the sixteenth MOS transistor is connected to the positive power supply.

6. The in-memory computation signal processing circuit according to claim 5, characterized in that, The first voltage input arithmetic unit, the second voltage input arithmetic unit, and the third voltage input arithmetic unit each include a first transmission gate, a second transmission gate, a seventeenth MOSFET, an eighteenth MOSFET, and a nineteenth MOSFET. The input terminal of the first transmission gate is connected to the gate of the sixteenth MOSFET, and the output terminal of the first transmission gate is connected to the gate of the seventeenth MOSFET and the drain of the eighteenth MOSFET. The gate of the eighteenth MOSFET is connected to a control signal, and the sources of the eighteenth MOSFET and the seventeenth MOSFET are both connected to the positive terminal of the power supply. The drain of the seventeenth MOSFET is connected to the source of the nineteenth MOSFET, the gate of the nineteenth MOSFET is connected to a bias voltage, and the drain of the nineteenth MOSFET is connected to the input terminal of the second transmission gate.

7. The in-memory computation signal processing circuit according to claim 6, characterized in that, The calculation result processing unit includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a capacitor reset unit, and a buffer unit. One end of the first capacitor is connected to the buffer unit, the output terminal of the second transmission gate in the first voltage input calculation unit, one end of the fourth capacitor, and one end of the fifth capacitor. The other end of the fourth capacitor is connected to the output terminal of the second transmission gate in the second voltage input calculation unit and one end of the second capacitor. The other end of the fifth capacitor is connected to the output terminal of the second transmission gate in the third voltage input calculation unit and one end of the third capacitor. The other ends of the first capacitor, the second capacitor, and the third capacitor are connected to the negative terminal of the power supply. The capacitor reset unit is connected to the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor, and is used to reset the voltage of the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor.

8. The in-memory computation signal processing circuit according to claim 7, characterized in that, The buffer unit includes a twentieth MOS transistor and a bias current source. The gate of the twentieth MOS transistor is connected to one end of the first capacitor. The drain of the twentieth MOS transistor is connected to the positive terminal of the power supply. The source of the twentieth MOS transistor is connected to the positive terminal of the bias current source. The negative terminal of the bias current source is connected to the negative terminal of the power supply. The voltage signal is output at the connection between the source of the twentieth MOS transistor and the positive terminal of the bias current source.

9. The in-memory computation signal processing circuit according to claim 7, characterized in that, The capacitor reset unit includes a 21st MOSFET, a 22nd MOSFET, and a 23rd MOSFET. The drain of the 21st MOSFET is connected to one end of the first capacitor, the drain of the 22nd MOSFET is connected to one end of the second capacitor, and the drain of the 23rd MOSFET is connected to one end of the third capacitor. The gate of the 21st MOSFET is connected to a first reset signal, the gate of the 22nd MOSFET is connected to a second reset signal, and the gate of the 23rd MOSFET is connected to a third reset signal. The sources of the 21st MOSFET, the 22nd MOSFET, and the 23rd MOSFET are connected to the negative terminal of the power supply.

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